From nobody Tue May 7 16:52:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1591799399; cv=none; d=zohomail.com; s=zohoarc; b=blZ+JU1hYmgDgbvEYSg9/bCl97wOE4XfTMTz+75tYO/3s+pg7zCIzM8wNn7ncr8aQdrIlQu3x+bo29LA5o1VujUPR9g/nQQOlTcADCAGZUJF5x0gkRuChBUNSkkLH+Ulqj2npYG7c46eF0GMgd20hj002YIE0zymuJm7R7vlVBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591799399; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QM5PMtDxdXXVmpfGrrzPU8GfUi3w2RJNBoLy0EvEYGI=; b=YRHaYdmEu/jGofCUC+6zlRohQoZ7ACTC/XIwC3Oj8CtV+8Wltqyin9RwUVXdpy2xzKJDfAqWmJLU1N9Z+oKKOR58wSVFSr5hkEfp/1tljwqS23CluSS10s9y9dWrMSEFUAVxrrrSRfuQOt7A5JjvYKxS6IhGlbOQZYySgGUzUig= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1591799399116882.3861485683962; Wed, 10 Jun 2020 07:29:59 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jj1jd-0005mq-HO; Wed, 10 Jun 2020 14:29:45 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jj1jc-0005mB-3K for xen-devel@lists.xenproject.org; Wed, 10 Jun 2020 14:29:44 +0000 Received: from esa6.hc3370-68.iphmx.com (unknown [216.71.155.175]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id d1b5259a-ab26-11ea-b44c-12813bfff9fa; Wed, 10 Jun 2020 14:29:40 +0000 (UTC) X-Inumbo-ID: d1b5259a-ab26-11ea-b44c-12813bfff9fa Authentication-Results: esa6.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: GJLjP7ff4EuEieDZJLxNjrBIVSzjkb8E/aRLYSRCwvDs0aQ7cM9xfIB3V0T1kwJ4mVLMqOkCzU gG/ukGGjgU8EjEsZVF9MUSyk1jlH8GjxzlRynFmce1eHmkCMkj1ceVoOZlKgylG417kKDMUXX8 vdhb24ldULRaHlusPRMqB4pVOKOTkOSL3ixZS0vcYddO3CGOTHVbZ/nsWxUPHpuaTX8BHk2iLC f6CollDsE8BWm131ni9qc6LS+xPOzrodg6rYbXVHr3YC71daGG5uIs57HB2iRmRo9YAiuxZKvH kIA= X-SBRS: 2.7 X-MesageID: 20039447 X-Ironport-Server: esa6.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,496,1583211600"; d="scan'208";a="20039447" From: Roger Pau Monne To: Subject: [PATCH for-4.14 v2 1/2] x86/passthrough: do not assert edge triggered GSIs for PVH dom0 Date: Wed, 10 Jun 2020 16:29:22 +0200 Message-ID: <20200610142923.9074-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200610142923.9074-1-roger.pau@citrix.com> References: <20200610142923.9074-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Roger Pau Monne , Wei Liu , Jan Beulich , paul@xen.org Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Edge triggered interrupts do not assert the line, so the handling done in Xen should also avoid asserting it. Asserting the line prevents further edge triggered interrupts on the same vIO-APIC pin from being delivered, since the line is not de-asserted. One case of such kind of interrupt is the RTC timer, which is edge triggered and available to a PVH dom0. Note this should not affect domUs, as it only modifies the behavior of IDENTITY_GSI kind of passed through interrupts. Signed-off-by: Roger Pau Monn=C3=A9 Acked-by: Andrew Cooper Reviewed-by: Paul Durrant --- Changes since v1: - Compare the triggering against VIOAPIC_{EDGE/LEVEL}_TRIG. --- xen/arch/x86/hvm/irq.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 9c8adbc495..fd02cf2e8d 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -169,9 +169,10 @@ void hvm_pci_intx_deassert( =20 void hvm_gsi_assert(struct domain *d, unsigned int gsi) { + int trig =3D vioapic_get_trigger_mode(d, gsi); struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); =20 - if ( gsi >=3D hvm_irq->nr_gsis ) + if ( gsi >=3D hvm_irq->nr_gsis || trig < 0 ) { ASSERT_UNREACHABLE(); return; @@ -186,9 +187,10 @@ void hvm_gsi_assert(struct domain *d, unsigned int gsi) * to know if the GSI is pending or not. */ spin_lock(&d->arch.hvm.irq_lock); - if ( !hvm_irq->gsi_assert_count[gsi] ) + if ( trig =3D=3D VIOAPIC_EDGE_TRIG || !hvm_irq->gsi_assert_count[gsi] ) { - hvm_irq->gsi_assert_count[gsi] =3D 1; + if ( trig =3D=3D VIOAPIC_LEVEL_TRIG ) + hvm_irq->gsi_assert_count[gsi] =3D 1; assert_gsi(d, gsi); } spin_unlock(&d->arch.hvm.irq_lock); @@ -196,11 +198,12 @@ void hvm_gsi_assert(struct domain *d, unsigned int gs= i) =20 void hvm_gsi_deassert(struct domain *d, unsigned int gsi) { + int trig =3D vioapic_get_trigger_mode(d, gsi); struct hvm_irq *hvm_irq =3D hvm_domain_irq(d); =20 - if ( gsi >=3D hvm_irq->nr_gsis ) + if ( trig <=3D VIOAPIC_EDGE_TRIG || gsi >=3D hvm_irq->nr_gsis ) { - ASSERT_UNREACHABLE(); + ASSERT(trig =3D=3D VIOAPIC_EDGE_TRIG && gsi < hvm_irq->nr_gsis); return; } =20 --=20 2.26.2 From nobody Tue May 7 16:52:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1591799403914718.3245762413871; Wed, 10 Jun 2020 07:30:03 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jj1jh-0005oD-Pd; Wed, 10 Jun 2020 14:29:49 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jj1jh-0005mB-3K for xen-devel@lists.xenproject.org; Wed, 10 Jun 2020 14:29:49 +0000 Received: from esa3.hc3370-68.iphmx.com (unknown [216.71.145.155]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id d394e594-ab26-11ea-b44c-12813bfff9fa; Wed, 10 Jun 2020 14:29:44 +0000 (UTC) X-Inumbo-ID: d394e594-ab26-11ea-b44c-12813bfff9fa Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: D4DDbPAQIkhAcN7IgbISu0+cSqAjP8J12kawIFw0UslmU2T6Hr2bFH4GfAn/AuDorrBMJkuqfP /UobpnxSz8qST9WKNbI17BIQ+66CEt7DAujFAHd1bDfU+t4ixyDItt12OPWL9aJCqsPkGi3Bvq w4EMNlJv0XFwoMsKgYEphIGL9oZn0gRTeUhdwFfSp7BJADP6Y/SlDsRyeKI0uRqA+X4UJjjMai vnvB2ymqUGFbhI8M+QY2Wi+nvdW1g28uJR9Yti/WMVRf4uNPfDDDXBTMJxLD1P9NzrN07koVBg vQo= X-SBRS: 2.7 X-MesageID: 19690573 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,496,1583211600"; d="scan'208";a="19690573" From: Roger Pau Monne To: Subject: [PATCH for-4.14 v2 2/2] x86/passthrough: introduce a flag for GSIs not requiring an EOI or unmask Date: Wed, 10 Jun 2020 16:29:23 +0200 Message-ID: <20200610142923.9074-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200610142923.9074-1-roger.pau@citrix.com> References: <20200610142923.9074-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Roger Pau Monne , Wei Liu , Jan Beulich , paul@xen.org Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" There's no need to setup a timer for GSIs that are edge triggered, since those don't require any EIO or unmask, and hence couldn't block other interrupts. Note this is only used by PVH dom0, that can setup the passthrough of edge triggered interrupts from the vIO-APIC. One example of such kind of interrupt that can be used by a PVH dom0 would be the RTC timer. While there introduce an out label to do the unlock and reduce code duplication. Signed-off-by: Roger Pau Monn=C3=A9 Acked-by: Andrew Cooper Reviewed-by: Paul Durrant --- Changes since v1: - Introduce an out label that does the unlock. --- xen/drivers/passthrough/io.c | 24 +++++++++++++++--------- xen/include/asm-x86/hvm/irq.h | 2 ++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/xen/drivers/passthrough/io.c b/xen/drivers/passthrough/io.c index b292e79382..6b1305a3e5 100644 --- a/xen/drivers/passthrough/io.c +++ b/xen/drivers/passthrough/io.c @@ -138,7 +138,8 @@ static void pt_pirq_softirq_reset(struct hvm_pirq_dpci = *pirq_dpci) =20 bool pt_irq_need_timer(uint32_t flags) { - return !(flags & (HVM_IRQ_DPCI_GUEST_MSI | HVM_IRQ_DPCI_TRANSLATE)); + return !(flags & (HVM_IRQ_DPCI_GUEST_MSI | HVM_IRQ_DPCI_TRANSLATE | + HVM_IRQ_DPCI_NO_EOI)); } =20 static int pt_irq_guest_eoi(struct domain *d, struct hvm_pirq_dpci *pirq_d= pci, @@ -558,6 +559,12 @@ int pt_irq_create_bind( */ ASSERT(!mask); share =3D trigger_mode; + if ( trigger_mode =3D=3D VIOAPIC_EDGE_TRIG ) + /* + * Edge IO-APIC interrupt, no EOI or unmask to per= form + * and hence no timer needed. + */ + pirq_dpci->flags |=3D HVM_IRQ_DPCI_NO_EOI; } } =20 @@ -897,17 +904,13 @@ static void hvm_dirq_assist(struct domain *d, struct = hvm_pirq_dpci *pirq_dpci) send_guest_pirq(d, pirq); =20 if ( pirq_dpci->flags & HVM_IRQ_DPCI_GUEST_MSI ) - { - spin_unlock(&d->event_lock); - return; - } + goto out; } =20 if ( pirq_dpci->flags & HVM_IRQ_DPCI_GUEST_MSI ) { vmsi_deliver_pirq(d, pirq_dpci); - spin_unlock(&d->event_lock); - return; + goto out; } =20 list_for_each_entry ( digl, &pirq_dpci->digl_list, list ) @@ -920,6 +923,8 @@ static void hvm_dirq_assist(struct domain *d, struct hv= m_pirq_dpci *pirq_dpci) if ( pirq_dpci->flags & HVM_IRQ_DPCI_IDENTITY_GSI ) { hvm_gsi_assert(d, pirq->pirq); + if ( pirq_dpci->flags & HVM_IRQ_DPCI_NO_EOI ) + goto out; pirq_dpci->pending++; } =20 @@ -927,8 +932,7 @@ static void hvm_dirq_assist(struct domain *d, struct hv= m_pirq_dpci *pirq_dpci) { /* for translated MSI to INTx interrupt, eoi as early as possi= ble */ __msi_pirq_eoi(pirq_dpci); - spin_unlock(&d->event_lock); - return; + goto out; } =20 /* @@ -941,6 +945,8 @@ static void hvm_dirq_assist(struct domain *d, struct hv= m_pirq_dpci *pirq_dpci) ASSERT(pt_irq_need_timer(pirq_dpci->flags)); set_timer(&pirq_dpci->timer, NOW() + PT_IRQ_TIME_OUT); } + + out: spin_unlock(&d->event_lock); } =20 diff --git a/xen/include/asm-x86/hvm/irq.h b/xen/include/asm-x86/hvm/irq.h index d306cfeade..532880d497 100644 --- a/xen/include/asm-x86/hvm/irq.h +++ b/xen/include/asm-x86/hvm/irq.h @@ -121,6 +121,7 @@ struct dev_intx_gsi_link { #define _HVM_IRQ_DPCI_GUEST_PCI_SHIFT 4 #define _HVM_IRQ_DPCI_GUEST_MSI_SHIFT 5 #define _HVM_IRQ_DPCI_IDENTITY_GSI_SHIFT 6 +#define _HVM_IRQ_DPCI_NO_EOI_SHIFT 7 #define _HVM_IRQ_DPCI_TRANSLATE_SHIFT 15 #define HVM_IRQ_DPCI_MACH_PCI (1u << _HVM_IRQ_DPCI_MACH_PCI_SHIFT) #define HVM_IRQ_DPCI_MACH_MSI (1u << _HVM_IRQ_DPCI_MACH_MSI_SHIFT) @@ -129,6 +130,7 @@ struct dev_intx_gsi_link { #define HVM_IRQ_DPCI_GUEST_PCI (1u << _HVM_IRQ_DPCI_GUEST_PCI_SHIFT) #define HVM_IRQ_DPCI_GUEST_MSI (1u << _HVM_IRQ_DPCI_GUEST_MSI_SHIFT) #define HVM_IRQ_DPCI_IDENTITY_GSI (1u << _HVM_IRQ_DPCI_IDENTITY_GSI_SHI= FT) +#define HVM_IRQ_DPCI_NO_EOI (1u << _HVM_IRQ_DPCI_NO_EOI_SHIFT) #define HVM_IRQ_DPCI_TRANSLATE (1u << _HVM_IRQ_DPCI_TRANSLATE_SHIFT) =20 struct hvm_gmsi_info { --=20 2.26.2