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d="scan'208";a="17480036" From: Roger Pau Monne To: Subject: [PATCH v2] x86/idle: prevent entering C6 with in service interrupts on Intel Date: Mon, 11 May 2020 12:17:53 +0200 Message-ID: <20200511101753.36610-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Wei Liu , Andrew Cooper , Ian Jackson , George Dunlap , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Apply a workaround for Intel errata CLX30: "A Pending Fixed Interrupt May Be Dispatched Before an Interrupt of The Same Priority Completes". It's not clear which models are affected, as the errata is listed in the "Second Generation Intel Xeon Scalable Processors" specification update, but the issue has been seen as far back as Nehalem processors. Apply the workaround to all Intel processors, the condition can be relaxed later. Signed-off-by: Roger Pau Monn=C3=A9 --- Changes since v1: - Unify workaround with errata_c6_eoi_workaround. - Properly check state in both acpi and mwait drivers. --- docs/misc/xen-command-line.pandoc | 8 ++++++++ xen/arch/x86/acpi/cpu_idle.c | 23 ++++++++++++----------- xen/arch/x86/cpu/mwait-idle.c | 3 +++ xen/include/asm-x86/cpuidle.h | 1 + 4 files changed, 24 insertions(+), 11 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index ee12b0f53f..6e868a2185 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -652,6 +652,14 @@ Specify the size of the console debug trace buffer. By= specifying `cpu:` additionally a trace buffer of the specified size is allocated per cpu. The debug trace feature is only enabled in debugging builds of Xen. =20 +### disable-c6-isr +> `=3D ` + +> Default: `true for Intel CPUs` + +Workaround for Intel errata CLX30. Prevent entering C6 idle states with in +service local APIC interrupts. Enabled by default for all Intel CPUs. + ### dma_bits > `=3D ` =20 diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index b83446e77d..8ef05aeba3 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -555,20 +555,21 @@ void trace_exit_reason(u32 *irq_traced) * There was an errata with some Core i7 processors that an EOI transactio= n=20 * may not be sent if software enters core C6 during an interrupt service=20 * routine. So we don't enter deep Cx state if there is an EOI pending. + * + * Errata CLX30: A Pending Fixed Interrupt May Be Dispatched Before an + * Interrupt of The Same Priority Completes. + * + * Prevent entering C6 if there are pending lapic interrupts, or else the + * processor might dispatch further pending interrupts before the first on= e has + * been completed. */ -static bool errata_c6_eoi_workaround(void) +bool errata_c6_eoi_workaround(void) { - static int8_t fix_needed =3D -1; + static int8_t __read_mostly fix_needed =3D -1; + boolean_param("disable-c6-isr", fix_needed); =20 if ( unlikely(fix_needed =3D=3D -1) ) - { - int model =3D boot_cpu_data.x86_model; - fix_needed =3D (cpu_has_apic && !directed_eoi_enabled && - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && - (boot_cpu_data.x86 =3D=3D 6) && - ((model =3D=3D 0x1a) || (model =3D=3D 0x1e) || (mode= l =3D=3D 0x1f) || - (model =3D=3D 0x25) || (model =3D=3D 0x2c) || (mode= l =3D=3D 0x2f))); - } + fix_needed =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL; =20 return (fix_needed && cpu_has_pending_apic_eoi()); } @@ -676,7 +677,7 @@ static void acpi_processor_idle(void) return; } =20 - if ( (cx->type =3D=3D ACPI_STATE_C3) && errata_c6_eoi_workaround() ) + if ( (cx->type >=3D ACPI_STATE_C3) && errata_c6_eoi_workaround() ) cx =3D power->safe_state; =20 =20 diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index b81937966e..bb017c488f 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -770,6 +770,9 @@ static void mwait_idle(void) return; } =20 + if (cx->type >=3D 3 && errata_c6_eoi_workaround()) + cx =3D power->safe_state; + eax =3D cx->address; cstate =3D ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; =20 diff --git a/xen/include/asm-x86/cpuidle.h b/xen/include/asm-x86/cpuidle.h index 5d7dffd228..13879f58a1 100644 --- a/xen/include/asm-x86/cpuidle.h +++ b/xen/include/asm-x86/cpuidle.h @@ -26,4 +26,5 @@ void update_idle_stats(struct acpi_processor_power *, void update_last_cx_stat(struct acpi_processor_power *, struct acpi_processor_cx *, uint64_t); =20 +bool errata_c6_eoi_workaround(void); #endif /* __X86_ASM_CPUIDLE_H__ */ --=20 2.26.2