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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: NzTDGMX+nHT7lgCRmFpXIaAAlMbE74v4a8FfpBFqO8jqZkVPiTNV275vF85+kVH7egwwd3xEhr pq4gtmxVkIhlBUTHOVMq1tmnn11xd3s/F+04B3746mysXtKy1QRq4X+Gpi0KF0u4AQ35v1os7y XuZdDCP48BlmpkhswZgK0UUPWCljIKNLRigOQkoCnIjph5o0+9/FYlMBI7Rn2VJFzUt8WQQf2Z t/4dVIQEvc9GsEMEBk9AtONcm1Q2wRDz+qbciu695xD9aIA2mO/LXT8K+GoLk1ZtmfFvbanGxz ivA= X-SBRS: 2.7 X-MesageID: 17067254 X-Ironport-Server: esa1.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,356,1583211600"; d="scan'208";a="17067254" From: Andrew Cooper To: Xen-devel Subject: [PATCH] x86/svm: Use flush-by-asid when available Date: Tue, 5 May 2020 19:25:39 +0100 Message-ID: <20200505182539.12247-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) AMD Fam15h processors introduced the flush-by-asid feature, for more fine grain flushing purposes. Flushing everything including ASID 0 (i.e. Xen context) is an an unnecesser= ily large hammer, and never necessary in the context of guest TLBs needing invalidating. When available, use TLB_CTRL_FLUSH_ASID in preference to TLB_CTRL_FLUSH_ALL. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 The APM currently describes tlb_control encoding 1 as "Flush entire TLB (Should be used only by legacy hypervisors.)". AMD have agreed that th= is is misleading and should say "legacy hardware" instead. This change does come with a minor observed perf improvement on Fam17h hardware, of ~0.6s over ~22s for my XTF pagewalk test. This test will spot TLB flushing issues, but isn't optimal for spotting the perf increase from better flushing. There were no observed differences for Fam15h, but this could simply mean that the measured code footprint was larger than the TLB = on this CPU. --- xen/arch/x86/hvm/svm/asid.c | 9 ++++++--- xen/include/asm-x86/hvm/svm/svm.h | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 9be90058c7..ab06dd3f3a 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 void svm_asid_init(const struct cpuinfo_x86 *c) { @@ -47,15 +48,17 @@ void svm_asid_handle_vmrun(void) if ( p_asid->asid =3D=3D 0 ) { vmcb_set_guest_asid(vmcb, 1); - /* TODO: investigate using TLB_CTRL_FLUSH_ASID here instead. */ - vmcb->tlb_control =3D TLB_CTRL_FLUSH_ALL; + vmcb->tlb_control =3D + cpu_has_svm_flushbyasid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH= _ALL; return; } =20 if ( vmcb_get_guest_asid(vmcb) !=3D p_asid->asid ) vmcb_set_guest_asid(vmcb, p_asid->asid); =20 - vmcb->tlb_control =3D need_flush ? TLB_CTRL_FLUSH_ALL : TLB_CTRL_NO_FL= USH; + vmcb->tlb_control =3D + !need_flush ? TLB_CTRL_NO_FLUSH : + cpu_has_svm_flushbyasid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; } =20 /* diff --git a/xen/include/asm-x86/hvm/svm/svm.h b/xen/include/asm-x86/hvm/sv= m/svm.h index 16a994ec74..cd71402cbb 100644 --- a/xen/include/asm-x86/hvm/svm/svm.h +++ b/xen/include/asm-x86/hvm/svm/svm.h @@ -79,6 +79,7 @@ extern u32 svm_feature_flags; #define cpu_has_svm_svml cpu_has_svm_feature(SVM_FEATURE_SVML) #define cpu_has_svm_nrips cpu_has_svm_feature(SVM_FEATURE_NRIPS) #define cpu_has_svm_cleanbits cpu_has_svm_feature(SVM_FEATURE_VMCBCLEAN) +#define cpu_has_svm_flushbyasid cpu_has_svm_feature(SVM_FEATURE_FLUSHBYASI= D) #define cpu_has_svm_decode cpu_has_svm_feature(SVM_FEATURE_DECODEASSIST= S) #define cpu_has_svm_vgif cpu_has_svm_feature(SVM_FEATURE_VGIF) #define cpu_has_pause_filter cpu_has_svm_feature(SVM_FEATURE_PAUSEFILTER) --=20 2.11.0