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x-conformance=sidf_compatible IronPort-SDR: /JSZgeJBN8B6+g9eVWrT5wUa6A+V6EHzivDdQuAznTamy7nFtOybPIWxZwXuys64fD2bDZvocH 9o/I61CwuckcEWz7H7RCus3C1LldQQc7VuYarJIAEWC/yjK/KHfjOK+Vjao6iBKumxm/U7orYX RuAV1R81YcTUFrO1twgNZkPJKhzdn9TtAkjSRTHJ7WygbZue5GgnBOlNoviWSqNIgfJdD2xjrf 5WE9O+O1NgcMJsuOgBX1cAX6cKIPaeaoOGphoBylOROnnrIoPLTpXhWt1ulDuAEcNz3zT1OMMu kQM= X-SBRS: 2.7 X-MesageID: 16651872 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,352,1583211600"; d="scan'208";a="16651872" From: Andrew Cooper To: Xen-devel Subject: [PATCH] x86/ucode/intel: Writeback and invalidate caches before updating microcode Date: Mon, 4 May 2020 13:47:52 +0100 Message-ID: <20200504124752.29806-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Ashok Raj Updating microcode is less error prone when caches have been flushed and depending on what exactly the microcode is updating. For example, some of t= he issues around certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner [Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen] Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/microcode/intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index a9f4d6e829..d031196d4c 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -25,6 +25,7 @@ #include =20 #include +#include =20 #include "private.h" =20 @@ -267,6 +268,8 @@ static int apply_microcode(const struct microcode_patch= *patch) if ( microcode_update_match(patch) !=3D NEW_UCODE ) return -EINVAL; =20 + wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)patch->data); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL); --=20 2.11.0