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x-conformance=sidf_compatible IronPort-SDR: El3z5Pex9n1Vnt4iBED7+gKnfwSD+n80nkFwZBKKJeHx72O4VmnQQJopwFqDF1jVYu3hvQ6vRx fax7vP/VNOhqVsylSpv8nRmRXuGD/14Xk1HNIi+TaP9wbABNoPhGxLEPdlaXZIQrndvyTj7btL whjTfyK3ouxXHwoOZ7WQkPjpTPh1hKd/CA7PqOWG+7Eg0p4Shv1nX0ErAvledG7qaRWVWb0thF uaQyy+zPRVDLpPFd3HRMo2pm7/J6PY9b3eNMQrz9wU97zdPmANojtlVhgC7RuS5gYcJdvl0UGa /Kw= X-SBRS: 2.7 X-MesageID: 16893124 X-Ironport-Server: esa6.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,334,1583211600"; d="scan'208";a="16893124" From: Roger Pau Monne To: Subject: [PATCH] x86/hvm: allow for more fine grained assisted flush Date: Thu, 30 Apr 2020 11:17:25 +0200 Message-ID: <20200430091725.80656-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.26.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Wei Liu , Andrew Cooper , Ian Jackson , George Dunlap , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Improve the assisted flush by expanding the interface and allowing for more fine grained TLB flushes to be issued using the HVMOP_flush_tlbs hypercall. Support for such advanced flushes is signaled in CPUID using the XEN_HVM_CPUID_ADVANCED_FLUSH flag. The new features make use of the NULL parameter so far passed in the hypercall in order to convey extra data to perform more selective flushes: a virtual address, an order field, a flags field and finally a vCPU bitmap. Note that not all features are implemented as part of this patch, but are already added to the interface in order to avoid having to introduce yet a new CPUID flag when the new features are added. The feature currently implemented is the usage of a guest provided vCPU bitmap in order to signal which vCPUs require a TLB flush, instead of assuming all vCPUs must be flushed. Note that not implementing the rest of the features just make the flush less efficient, but it's still correct and safe. Finally add support for Xen running in guest mode (Xen on Xen or PV shim mode) to use the newly introduced flush options when available. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/guest/xen/xen.c | 22 +++++++++++++++++- xen/arch/x86/hvm/hvm.c | 35 ++++++++++++++++++++++++----- xen/arch/x86/traps.c | 4 +++- xen/include/public/arch-x86/cpuid.h | 2 ++ xen/include/public/hvm/hvm_op.h | 23 ++++++++++++++++++- 5 files changed, 78 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index 2ff63d370a..310ce0c6fb 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -326,7 +326,27 @@ static void __init e820_fixup(struct e820map *e820) =20 static int flush_tlb(const cpumask_t *mask, const void *va, unsigned int f= lags) { - return xen_hypercall_hvm_op(HVMOP_flush_tlbs, NULL); + xen_hvm_flush_tlbs_t op =3D { + .va =3D (unsigned long)va, + .order =3D (flags - 1) & FLUSH_ORDER_MASK, + .flags =3D ((flags & FLUSH_TLB_GLOBAL) ? HVMOP_flush_global : 0) | + ((flags & FLUSH_VA_VALID) ? HVMOP_flush_va_valid : 0), + .mask_size =3D BITS_TO_LONGS(nr_cpu_ids), + }; + static int8_t __read_mostly advanced_flush =3D -1; + + if ( advanced_flush =3D=3D -1 ) + { + uint32_t eax, ebx, ecx, edx; + + ASSERT(xen_cpuid_base); + cpuid(xen_cpuid_base + 4, &eax, &ebx, &ecx, &edx); + advanced_flush =3D (eax & XEN_HVM_CPUID_ADVANCED_FLUSH) ? 1 : 0; + } + + set_xen_guest_handle(op.vcpu_mask, cpumask_bits(mask)); + + return xen_hypercall_hvm_op(HVMOP_flush_tlbs, advanced_flush ? &op : N= ULL); } =20 static const struct hypervisor_ops __initconstrel ops =3D { diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 814b7020d8..1d41b6e2ea 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4011,17 +4011,42 @@ static void hvm_s3_resume(struct domain *d) } } =20 -static bool always_flush(void *ctxt, struct vcpu *v) +static bool flush_check(void *mask, struct vcpu *v) { - return true; + return mask ? test_bit(v->vcpu_id, (unsigned long *)mask) : true; } =20 -static int hvmop_flush_tlb_all(void) +static int hvmop_flush_tlb(XEN_GUEST_HANDLE_PARAM(xen_hvm_flush_tlbs_t) uo= p) { + xen_hvm_flush_tlbs_t op; + DECLARE_BITMAP(mask, HVM_MAX_VCPUS) =3D { }; + bool valid_mask =3D false; + if ( !is_hvm_domain(current->domain) ) return -EINVAL; =20 - return paging_flush_tlb(always_flush, NULL) ? 0 : -ERESTART; + if ( !guest_handle_is_null(uop) ) + { + if ( copy_from_guest(&op, uop, 1) ) + return -EFAULT; + + /* + * TODO: implement support for the other features present in + * xen_hvm_flush_tlbs_t: flushing a specific virtual address and n= ot + * flushing global mappings. + */ + + if ( op.mask_size > ARRAY_SIZE(mask) ) + return -EINVAL; + + if ( copy_from_guest(mask, op.vcpu_mask, op.mask_size) ) + return -EFAULT; + + valid_mask =3D true; + } + + return paging_flush_tlb(flush_check, valid_mask ? mask : NULL) ? 0 + : -ERES= TART; } =20 static int hvmop_set_evtchn_upcall_vector( @@ -5017,7 +5042,7 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PAR= AM(void) arg) break; =20 case HVMOP_flush_tlbs: - rc =3D guest_handle_is_null(arg) ? hvmop_flush_tlb_all() : -EINVAL; + rc =3D hvmop_flush_tlb(guest_handle_cast(arg, xen_hvm_flush_tlbs_t= )); break; =20 case HVMOP_get_mem_type: diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index e838846c6b..b07da2fd33 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -966,8 +966,10 @@ void cpuid_hypervisor_leaves(const struct vcpu *v, uin= t32_t leaf, /* * Indicate that memory mapped from other domains (either grants or * foreign pages) has valid IOMMU entries. + * + * Also signal support for more selective assisted flush support. */ - res->a |=3D XEN_HVM_CPUID_IOMMU_MAPPINGS; + res->a |=3D XEN_HVM_CPUID_IOMMU_MAPPINGS | XEN_HVM_CPUID_ADVANCED_= FLUSH; =20 /* Indicate presence of vcpu id and set it in ebx */ res->a |=3D XEN_HVM_CPUID_VCPU_ID_PRESENT; diff --git a/xen/include/public/arch-x86/cpuid.h b/xen/include/public/arch-= x86/cpuid.h index ce46305bee..b980ed91f6 100644 --- a/xen/include/public/arch-x86/cpuid.h +++ b/xen/include/public/arch-x86/cpuid.h @@ -102,6 +102,8 @@ #define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2) #define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in = EBX */ #define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in EC= X */ +/* Supports more fine grained assisted flush, see HVMOP_flush_tlbs. */ +#define XEN_HVM_CPUID_ADVANCED_FLUSH (1u << 5) =20 /* * Leaf 6 (0x40000x05) diff --git a/xen/include/public/hvm/hvm_op.h b/xen/include/public/hvm/hvm_o= p.h index 870ec52060..ca6ae678bc 100644 --- a/xen/include/public/hvm/hvm_op.h +++ b/xen/include/public/hvm/hvm_op.h @@ -99,8 +99,29 @@ DEFINE_XEN_GUEST_HANDLE(xen_hvm_set_pci_link_route_t); =20 #endif /* __XEN_INTERFACE_VERSION__ < 0x00040900 */ =20 -/* Flushes all VCPU TLBs: @arg must be NULL. */ +/* + * Flushes all VCPU TLBs: @arg can be NULL or xen_hvm_flush_tlbs_t. + * + * Support for passing a xen_hvm_flush_tlbs_t parameter is signaled in CPU= ID, + * see XEN_HVM_CPUID_ADVANCED_FLUSH. + */ #define HVMOP_flush_tlbs 5 +struct xen_hvm_flush_tlbs { + /* Virtual address to be flushed. */ + uint64_t va; + uint16_t order; + uint16_t flags; +/* Flush global mappings. */ +#define HVMOP_flush_global (1u << 0) +/* VA for the flush has a valid mapping. */ +#define HVMOP_flush_va_valid (1u << 1) + /* Number of uint64_t elements in vcpu_mask. */ + uint32_t mask_size; + /* Bitmask of vcpus that should be flushed. */ + XEN_GUEST_HANDLE(const_uint64) vcpu_mask; +}; +typedef struct xen_hvm_flush_tlbs xen_hvm_flush_tlbs_t; +DEFINE_XEN_GUEST_HANDLE(xen_hvm_flush_tlbs_t); =20 /* * hvmmem_type_t should not be defined when generating the corresponding --=20 2.26.0