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x-conformance=sidf_compatible IronPort-SDR: dIhjNs5TOxqhISzkCO6/P3I8cozFiAXEwDKOoTTuDVYbg8OcSHw7lQ64I73R3pY20uTR7c98kx bLw0FlxsT5RKsMMuHCFD+8YZdEhFL6rhAeXC377MotZqEQK4mXPdjEoUcVw4GvCjzKnk9JjIt7 pTLemi0p/XseFKKdArwvXNH7DGHt1vk81a1hiROyXaxK400KBAhl29+yvxN5pu9LBjH4MnB36Y ZOBV3byptgLouM0TqkVprq7n7uFeK4GCdMSNDgX7VMdErWhhWmmpxGxGW7PKiRiUcf3n8uQMy0 /1Y= X-SBRS: 2.7 X-MesageID: 15976207 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.72,407,1580792400"; d="scan'208";a="15976207" From: Andrew Cooper To: Xen-devel Subject: [PATCH] x86: Enumeration for Control-flow Enforcement Technology Date: Mon, 20 Apr 2020 20:08:29 +0100 Message-ID: <20200420190829.17874-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The CET spec has been published and guest kernels are starting to get suppo= rt. Introduce the CPUID and MSRs, and fully block the MSRs from guest use. Signed-off-by: Andrew Cooper Acked-by: Wei Liu Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- tools/libxl/libxl_cpuid.c | 2 ++ tools/misc/xen-cpuid.c | 3 ++- xen/arch/x86/msr.c | 6 ++++++ xen/include/asm-x86/msr-index.h | 8 ++++++++ xen/include/public/arch-x86/cpufeatureset.h | 2 ++ 5 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index b4f6fd590d..00262a3f8f 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -201,6 +201,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *c= puid, const char* str) {"pku", 0x00000007, 0, CPUID_REG_ECX, 3, 1}, {"ospke", 0x00000007, 0, CPUID_REG_ECX, 4, 1}, {"avx512-vbmi2", 0x00000007, 0, CPUID_REG_ECX, 6, 1}, + {"cet-ss", 0x00000007, 0, CPUID_REG_ECX, 7, 1}, {"gfni", 0x00000007, 0, CPUID_REG_ECX, 8, 1}, {"vaes", 0x00000007, 0, CPUID_REG_ECX, 9, 1}, {"vpclmulqdq", 0x00000007, 0, CPUID_REG_ECX, 10, 1}, @@ -213,6 +214,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *c= puid, const char* str) {"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1}, {"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1}, {"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1}, + {"cet-ibt", 0x00000007, 0, CPUID_REG_EDX, 20, 1}, {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 585b530b21..ff36d8cee1 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -123,7 +123,7 @@ static const char *const str_7c0[32] =3D [ 0] =3D "prefetchwt1", [ 1] =3D "avx512_vbmi", [ 2] =3D "umip", [ 3] =3D "pku", [ 4] =3D "ospke", [ 5] =3D "waitpkg", - [ 6] =3D "avx512_vbmi2", + [ 6] =3D "avx512_vbmi2", [ 7] =3D "cet-ss", [ 8] =3D "gfni", [ 9] =3D "vaes", [10] =3D "vpclmulqdq", [11] =3D "avx512_vnni", [12] =3D "avx512_bitalg", @@ -163,6 +163,7 @@ static const char *const str_7d0[32] =3D /* 12 */ [13] =3D "tsx-force-abort", =20 [18] =3D "pconfig", + [20] =3D "cet-ibt", =20 [26] =3D "ibrsb", [27] =3D "stibp", [28] =3D "l1d_flush", [29] =3D "arch_caps", diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index b4a1ab0fa6..dcacae58de 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -167,6 +167,9 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_CORE_CAPABILITIES: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: case MSR_PPIN_CTL: @@ -324,6 +327,9 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) case MSR_TEST_CTRL: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: case MSR_PPIN_CTL: diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index bb4e601445..85c5f20b76 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -66,6 +66,14 @@ #define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0) #define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1) =20 +#define MSR_U_CET 0x000006a0 +#define MSR_S_CET 0x000006a2 +#define MSR_PL0_SSP 0x000006a4 +#define MSR_PL1_SSP 0x000006a5 +#define MSR_PL2_SSP 0x000006a6 +#define MSR_PL3_SSP 0x000006a7 +#define MSR_INTERRUPT_SSP_TABLE 0x000006a8 + /* * Legacy MSR constants in need of cleanup. No new MSRs below this commen= t. */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 295b2b7aa8..c061133282 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -229,6 +229,7 @@ XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode I= nstruction Prevention */ XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace = */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte= Manipulation Instrs */ +XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */ XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */ XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */ XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplicati= on Instrs */ @@ -255,6 +256,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Mult= iply Accumulation Single XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural= buffers */ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT = */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by= Intel) */ +XEN_CPUFEATURE(CET_IBT, 6*32+20) /* CET - Indirect Branch Tracking= */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ --=20 2.11.0