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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: jXdlcSAfrcGp+tNv0XgzI+aOKK8aoY9xYgjNRJQHnFyinUhTe6OPol6afEd5ZXugydxkKShrUk Q+Ky74EnxbZt1muA2edI2lzxIGBrWzSJS2vSkIjHz50xYultnsXQ9r0XZP3wjNQIIZkqOEb/yz u4FYiBm4RZSO5P/Zvbul0qYUGBdHW53WLbgYffkqfc93uEmJRyHSKOihQfA8hDc3ngAS7jBSeR 9HI5XPd4UiDBkx94FcmoIQwFbpVr/56hnQXGWvSZ0FRU9rweygq9gNlk+5cOM5VcHkhCKzClHb Tjc= X-SBRS: 2.7 X-MesageID: 15928930 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.72,406,1580792400"; d="scan'208";a="15928930" From: Andrew Cooper To: Xen-devel Subject: [PATCH 3/3] x86/pv: Don't use IST for NMI/#MC/#DB in !CONFIG_PV builds Date: Mon, 20 Apr 2020 15:59:11 +0100 Message-ID: <20200420145911.5708-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200420145911.5708-1-andrew.cooper3@citrix.com> References: <20200420145911.5708-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) ISTs are used to force a stack switch on CPL0=3D>0 interrupts/exceptions. = They however come with a nasty corner case in the case of reentrancy where the outer exception frame gets clobbered. When the SYSCALL/SYSRET instructions aren't used, there is no need to use I= ST for anything other than #DF, which reduces the number of corner cases. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/common.c | 8 +++++--- xen/include/asm-x86/processor.h | 12 +++++++++++- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 7b093cb421..d45495c701 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -732,15 +732,17 @@ void load_system_tables(void) .rsp2 =3D 0x8600111111111111ul, =20 /* - * MCE, NMI and Double Fault handlers get their own stacks. + * #DF always uses a separate stack. NMI/#MC/#DB only need a + * separate stacks when PV guests are used. * All others poisoned. */ .ist =3D { - [IST_MCE - 1] =3D stack_top + IST_MCE * PAGE_SIZE, [IST_DF - 1] =3D stack_top + IST_DF * PAGE_SIZE, +#ifdef CONFIG_PV [IST_NMI - 1] =3D stack_top + IST_NMI * PAGE_SIZE, + [IST_MCE - 1] =3D stack_top + IST_MCE * PAGE_SIZE, [IST_DB - 1] =3D stack_top + IST_DB * PAGE_SIZE, - +#endif [IST_MAX ... ARRAY_SIZE(tss->ist) - 1] =3D 0x8600111111111111ul, }, diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index ea6e5497f4..33f2052c8e 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -441,12 +441,18 @@ struct tss_page { }; DECLARE_PER_CPU(struct tss_page, tss_page); =20 +/* + * Interrupt Stack Tables. Used to force a stack switch on a CPL0=3D>0 + * interrupt/exception. #DF uses IST all the time to detect stack overflo= ws + * cleanly. NMI/#MC/#DB only need IST to cover the SYSCALL gap, and there= fore + * only necessary with PV guests. + */ #define IST_NONE 0UL #define IST_DF 1UL #define IST_NMI 2UL #define IST_MCE 3UL #define IST_DB 4UL -#define IST_MAX 4UL +#define IST_MAX (IS_ENABLED(CONFIG_PV) ? 4ul : 1ul) =20 /* Set the Interrupt Stack Table used by a particular IDT entry. */ static inline void set_ist(idt_entry_t *idt, unsigned int ist) @@ -461,6 +467,8 @@ static inline void set_ist(idt_entry_t *idt, unsigned i= nt ist) static inline void enable_each_ist(idt_entry_t *idt) { set_ist(&idt[TRAP_double_fault], IST_DF); + if ( !IS_ENABLED(CONFIG_PV) ) + return; set_ist(&idt[TRAP_nmi], IST_NMI); set_ist(&idt[TRAP_machine_check], IST_MCE); set_ist(&idt[TRAP_debug], IST_DB); @@ -469,6 +477,8 @@ static inline void enable_each_ist(idt_entry_t *idt) static inline void disable_each_ist(idt_entry_t *idt) { set_ist(&idt[TRAP_double_fault], IST_NONE); + if ( !IS_ENABLED(CONFIG_PV) ) + return; set_ist(&idt[TRAP_nmi], IST_NONE); set_ist(&idt[TRAP_machine_check], IST_NONE); set_ist(&idt[TRAP_debug], IST_NONE); --=20 2.11.0