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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: ZoQGFsLuSCPaNyAAiPkRhKvoCCMw54cHtgUr6hRBr6bj4lX36NjoFiE+i5Fb9FbuzGtXZndonk z3kShYFu1IXYo1lNM1IKBvH3rHQRf0I75+X/7RxghZBEgFLvwrvU9z4+xKmdiCVbPxd9h7X5i+ 3yTPjDHAuNogy3b5RwQhMOaGKOeuRwKQR0Hm/g4NqQpGcGhvqTCUVbE6XQ2TaqQ+PvvXRsGbDY RT+Iymb2o1xgBgh+dNZdJhM+kii/TCPcVbaAz7lmf4DyE+zkKxdtBZYtFDBb1GnK2Ew9z7i3E0 /Io= X-SBRS: 2.7 X-MesageID: 14703418 X-Ironport-Server: esa6.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.70,572,1574139600"; d="scan'208";a="14703418" From: Andrew Cooper To: Xen-devel Date: Thu, 19 Mar 2020 15:26:20 +0000 Message-ID: <20200319152622.31758-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200319152622.31758-1-andrew.cooper3@citrix.com> References: <20200319152622.31758-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 4/6] x86/ucode: Rationalise startup and family/model checks X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Drop microcode_init_{intel,amd}(), export {intel,amd}_ucode_ops, and use a switch statement in early_microcode_init() rather than probing each vendor = in turn. This allows the microcode_ops pointer to become local to core.c. As there are no external users of microcode_ops, there is no need for collect_cpu_info() to implement sanity checks. Move applicable checks to early_microcode_init() so they are performed once, rather than repeatedly. Items to note: * The AMD ucode driver does have an upper familiy limit of 0x17, as a side effect of the logic in verify_patch_size() which does need updating for each new model. * The Intel logic guarding the read of MSR_PLATFORM_ID is contrary to the SDM, which states that the MSR has been architectural since the Pentium Pro (06-01-xx), and lists no family/model restrictions in the pseudocode for microcode loading. Either way, Xen's 64bit-only nature already makes this check redundant. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 The MSR_PLATFORM_ID guard was inherited from Linux, and has existed there since the code's introduction. My best guess is that the MSR list in the S= DM got altered at some point between then and now. --- xen/arch/x86/cpu/microcode/amd.c | 21 ++------------------ xen/arch/x86/cpu/microcode/core.c | 37 ++++++++++++++++++++++----------= ---- xen/arch/x86/cpu/microcode/intel.c | 26 +++---------------------- xen/arch/x86/cpu/microcode/private.h | 5 +---- 4 files changed, 29 insertions(+), 60 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 9028889813..768fbcf322 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -76,22 +76,12 @@ struct mpbhdr { /* See comment in start_update() for cases when this routine fails */ static int collect_cpu_info(struct cpu_signature *csig) { - unsigned int cpu =3D smp_processor_id(); - struct cpuinfo_x86 *c =3D &cpu_data[cpu]; - memset(csig, 0, sizeof(*csig)); =20 - if ( (c->x86_vendor !=3D X86_VENDOR_AMD) || (c->x86 < 0x10) ) - { - printk(KERN_ERR "microcode: CPU%d not a capable AMD processor\n", - cpu); - return -EINVAL; - } - rdmsrl(MSR_AMD_PATCHLEVEL, csig->rev); =20 pr_debug("microcode: CPU%d collect_cpu_info: patch_id=3D%#x\n", - cpu, csig->rev); + smp_processor_id(), csig->rev); =20 return 0; } @@ -601,7 +591,7 @@ static int start_update(void) } #endif =20 -static const struct microcode_ops microcode_amd_ops =3D { +const struct microcode_ops amd_ucode_ops =3D { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, @@ -613,10 +603,3 @@ static const struct microcode_ops microcode_amd_ops = =3D { .compare_patch =3D compare_patch, .match_cpu =3D match_cpu, }; - -int __init microcode_init_amd(void) -{ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) - microcode_ops =3D µcode_amd_ops; - return 0; -} diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index ac5da6b2fe..61e4b9b7ab 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -210,7 +210,7 @@ void __init microcode_grab_module( microcode_scan_module(module_map, mbi); } =20 -const struct microcode_ops *microcode_ops; +static const struct microcode_ops __read_mostly *microcode_ops; =20 static DEFINE_SPINLOCK(microcode_mutex); =20 @@ -798,23 +798,32 @@ static int __init early_microcode_update_cpu(void) =20 int __init early_microcode_init(void) { - int rc; - - rc =3D microcode_init_intel(); - if ( rc ) - return rc; - - rc =3D microcode_init_amd(); - if ( rc ) - return rc; + const struct cpuinfo_x86 *c =3D &boot_cpu_data; + int rc =3D 0; =20 - if ( microcode_ops ) + switch ( c->x86_vendor ) { - microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); + case X86_VENDOR_AMD: + if ( c->x86 >=3D 0x10 && c->x86 <=3D 0x17 ) + microcode_ops =3D &amd_ucode_ops; + break; + + case X86_VENDOR_INTEL: + if ( c->x86 >=3D 6 ) + microcode_ops =3D &intel_ucode_ops; + break; + } =20 - if ( ucode_mod.mod_end || ucode_blob.size ) - rc =3D early_microcode_update_cpu(); + if ( !microcode_ops ) + { + printk(XENLOG_WARNING "Microcode loading not available\n"); + return -ENODEV; } =20 + microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); + + if ( ucode_mod.mod_end || ucode_blob.size ) + rc =3D early_microcode_update_cpu(); + return rc; } diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index 90fb006c94..48544e8d6d 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -93,27 +93,14 @@ struct extended_sigtable { =20 static int collect_cpu_info(struct cpu_signature *csig) { - unsigned int cpu_num =3D smp_processor_id(); - struct cpuinfo_x86 *c =3D &cpu_data[cpu_num]; uint64_t msr_content; =20 memset(csig, 0, sizeof(*csig)); =20 - if ( (c->x86_vendor !=3D X86_VENDOR_INTEL) || (c->x86 < 6) ) - { - printk(KERN_ERR "microcode: CPU%d not a capable Intel " - "processor\n", cpu_num); - return -1; - } - csig->sig =3D cpuid_eax(0x00000001); =20 - if ( (c->x86_model >=3D 5) || (c->x86 > 6) ) - { - /* get processor flags from MSR 0x17 */ - rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); - csig->pf =3D 1 << ((msr_content >> 50) & 7); - } + rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); + csig->pf =3D 1 << ((msr_content >> 50) & 7); =20 wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL); /* As documented in the SDM: Do a CPUID 1 here */ @@ -405,7 +392,7 @@ static struct microcode_patch *cpu_request_microcode(co= nst void *buf, return patch; } =20 -static const struct microcode_ops microcode_intel_ops =3D { +const struct microcode_ops intel_ucode_ops =3D { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, @@ -413,10 +400,3 @@ static const struct microcode_ops microcode_intel_ops = =3D { .compare_patch =3D compare_patch, .match_cpu =3D match_cpu, }; - -int __init microcode_init_intel(void) -{ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) - microcode_ops =3D µcode_intel_ops; - return 0; -} diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microc= ode/private.h index 459b6a4c54..c32ddc8d19 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -32,9 +32,6 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *o= ld); }; =20 -extern const struct microcode_ops *microcode_ops; - -int microcode_init_intel(void); -int microcode_init_amd(void); +extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; =20 #endif /* ASM_X86_MICROCODE_PRIVATE_H */ --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel