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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: R/nZ2afLo15uGMeGINHGhkwWeu+Zio9YCfDuOW3bRZ3d9136gSrLIlZ19YBwccab2itFZMUHx/ ZwtQbgQAKMIL/Yg7dd/SX9Ea58qD3E0t9RWrF7W6ueQcIfmNvd1xt5jq1mICt55k9DNEAY+vKz MMSwhzMRdzfWN7l0/8L2vo0uCQdCuPlrl24goBk7RA2FMwTsm2vsao1sNNEVUdo7xOWZ3YI1Wc GcAF8PVAliHEupxNlJdDYh8p2TrZ3AeWJ4N4DKWo78Gmu68tGigJBlWYiyFLZPAyWTT4zfh6yo ONg= X-SBRS: 2.7 X-MesageID: 12828026 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.70,468,1574139600"; d="scan'208";a="12828026" From: Andrew Cooper To: Xen-devel Date: Fri, 21 Feb 2020 15:19:48 +0000 Message-ID: <20200221151948.6209-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH] x86/msr: Start cleaning up msr-index.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Make a start on cleaning up the constants in msr-index.h. No functional change - only formatting changes. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 Pulled out of a longer series which really ought to start making some progress. --- xen/include/asm-x86/msr-index.h | 123 ++++++++++++++++++++++--------------= ---- 1 file changed, 68 insertions(+), 55 deletions(-) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index c320846c06..c831cd2c60 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -1,7 +1,74 @@ #ifndef __ASM_MSR_INDEX_H #define __ASM_MSR_INDEX_H =20 -/* CPU model specific register (MSR) numbers */ +/* + * CPU model specific register (MSR) numbers + * + * Definitions for an MSR should follow this style: + * + * #define MSR_$NAME 0x$INDEX + * #define $NAME_$BIT1 (_AC(1, ULL) << $POS1) + * #define $NAME_$BIT2 (_AC(1, ULL) << $POS2) + * + * Blocks of related constants should be sorted by MSR index. The constant + * names should be as concise as possible, and the bit names may have an + * abbreviated name. + */ + +#define MSR_APIC_BASE 0x0000001b +#define APIC_BASE_BSP (_AC(1, ULL) << 8) +#define APIC_BASE_EXTD (_AC(1, ULL) << 10) +#define APIC_BASE_ENABLE (_AC(1, ULL) << 11) +#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL + +#define MSR_TEST_CTRL 0x00000033 +#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) +#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) + +#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 +#define MSR_CTC_THREAD_MASK 0x0000ffff +#define MSR_CTC_CORE_MASK 0xffff0000 + +#define MSR_SPEC_CTRL 0x00000048 +#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) +#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) +#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2) + +#define MSR_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB (_AC(1, ULL) << 0) + +#define MSR_PPIN_CTL 0x0000004e +#define PPIN_LOCKOUT (_AC(1, ULL) << 0) +#define PPIN_ENABLE (_AC(1, ULL) << 1) +#define MSR_PPIN 0x0000004f + +#define MSR_CORE_CAPABILITIES 0x000000cf +#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) + +#define MSR_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) +#define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1) +#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) +#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3) +#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4) +#define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5) +#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6) +#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7) +#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8) + +#define MSR_FLUSH_CMD 0x0000010b +#define FLUSH_CMD_L1D (_AC(1, ULL) << 0) + +#define MSR_TSX_FORCE_ABORT 0x0000010f +#define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0) + +#define MSR_TSX_CTRL 0x00000122 +#define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0) +#define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1) + +/* + * Legacy MSR constants in need of cleanup. No new code below this commen= t. + */ =20 /* x86-64 specific MSRs */ #define MSR_EFER 0xc0000080 /* extended feature register */ @@ -32,54 +99,6 @@ #define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \ EFER_SVME | EFER_FFXSE) =20 -#define MSR_TEST_CTRL 0x00000033 -#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) -#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) - -#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 -#define MSR_CTC_THREAD_MASK 0x0000ffff -#define MSR_CTC_CORE_MASK 0xffff0000 - -/* Speculation Controls. */ -#define MSR_SPEC_CTRL 0x00000048 -#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) -#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) -#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2) - -#define MSR_PRED_CMD 0x00000049 -#define PRED_CMD_IBPB (_AC(1, ULL) << 0) - -/* Intel Protected Processor Inventory Number */ -#define MSR_PPIN_CTL 0x0000004e -#define MSR_PPIN 0x0000004f - -#define PPIN_LOCKOUT (_AC(1, ULL) << 0) -#define PPIN_ENABLE (_AC(1, ULL) << 1) - -#define MSR_CORE_CAPABILITIES 0x000000cf -#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) - -#define MSR_ARCH_CAPABILITIES 0x0000010a -#define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) -#define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1) -#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) -#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3) -#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4) -#define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5) -#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6) -#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7) -#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8) - -#define MSR_FLUSH_CMD 0x0000010b -#define FLUSH_CMD_L1D (_AC(1, ULL) << 0) - -#define MSR_TSX_FORCE_ABORT 0x0000010f -#define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0) - -#define MSR_TSX_CTRL 0x00000122 -#define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0) -#define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1) - /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_A_PERFCTR0 0x000004c1 @@ -359,12 +378,6 @@ =20 #define MSR_IA32_TSC_ADJUST 0x0000003b =20 -#define MSR_APIC_BASE 0x0000001b -#define APIC_BASE_BSP (1<<8) -#define APIC_BASE_EXTD (1<<10) -#define APIC_BASE_ENABLE (1<<11) -#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ul - #define MSR_X2APIC_FIRST 0x00000800 #define MSR_X2APIC_LAST 0x00000bff =20 --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel