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x-conformance=sidf_compatible IronPort-SDR: cefN6MU4UJdcZDp7O2ceV9fmsaOSXudMeJ0M6T7FfIvgLcR5ODaN9Ayh415diyGmWw2XSXMXnV lOaSoQ4nOXeXVE6QhhCr7yvnNL5ygFbySjE7sD5o+foTVgVTEsnfDJH6LsB4Fv44J8wRRX2L6R G622ttpkcGjvc4zAL+11zOwQNtiWnvZeUA4DQYuuSjtSOHZEJ8siKdjQFjvv58wslAyXb3yGL1 hH531Ckk/iX39W5kxp6U/V67XQWyezpucTITqd28bOr33nH8z2AppsuYfSphmtrjUq0bKuM9C3 ghs= X-SBRS: 2.7 X-MesageID: 12783358 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.70,465,1574139600"; d="scan'208";a="12783358" From: Andrew Cooper To: Xen-devel Date: Thu, 20 Feb 2020 19:58:45 +0000 Message-ID: <20200220195845.5676-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH] x86/splitlock: CPUID and MSR details X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) A splitlock is an atomic operation which crosses a cache line boundary. It serialises operations in the cache coherency fabric and comes with a multi-thousand cycle stall. Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specif= ic features, and MSR_TEST_CTRL to adjust the behaviour in the case of a splitlock. Virtualising this for guests is distinctly tricky owing to the fact that MSR_TEST_CTRL has core rather than thread scope. In the meantime however, prevent the MSR values leaking into guests. Signed-off-by: Andrew Cooper Reviewed-by: Wei Liu --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- tools/libxl/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 +- xen/arch/x86/msr.c | 4 ++++ xen/include/asm-x86/msr-index.h | 7 +++++++ xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 062750102e..b4f6fd590d 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -217,6 +217,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *c= puid, const char* str) {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1}, {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1}, + {"core-caps", 0x00000007, 0, CPUID_REG_EDX, 30, 1}, {"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1}, =20 {"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 8be03d81ce..7726c4ed3c 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -166,7 +166,7 @@ static const char *const str_7d0[32] =3D =20 [26] =3D "ibrsb", [27] =3D "stibp", [28] =3D "l1d_flush", [29] =3D "arch_caps", - /* 30 */ [31] =3D "ssbd", + [30] =3D "core_caps", [31] =3D "ssbd", }; =20 static const char *const str_7a1[32] =3D diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 1cea777680..dd26c87758 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -132,6 +132,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_TEST_CTRL: + case MSR_CORE_CAPABILITIES: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: @@ -283,10 +285,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_= t val) uint64_t rsvd; =20 case MSR_IA32_PLATFORM_ID: + case MSR_CORE_CAPABILITIES: case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* Read-only */ + case MSR_TEST_CTRL: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index bbca3289ca..c320846c06 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -32,6 +32,10 @@ #define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \ EFER_SVME | EFER_FFXSE) =20 +#define MSR_TEST_CTRL 0x00000033 +#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) +#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) + #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 #define MSR_CTC_THREAD_MASK 0x0000ffff #define MSR_CTC_CORE_MASK 0xffff0000 @@ -52,6 +56,9 @@ #define PPIN_LOCKOUT (_AC(1, ULL) << 0) #define PPIN_ENABLE (_AC(1, ULL) << 1) =20 +#define MSR_CORE_CAPABILITIES 0x000000cf +#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) + #define MSR_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) #define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index bd2f21cb85..086736ac7b 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -258,6 +258,7 @@ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IB= PB support (used by Intel XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ +XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel