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[54.240.197.235]) by smtp.gmail.com with ESMTPSA id a62sm949407wmh.33.2020.02.17.14.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2020 14:20:42 -0800 (PST) X-Inumbo-ID: bcacfbca-51d3-11ea-bc8e-bc764e2007e4 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MCOMsDh9TMSdidqT0X6rioOpB7v4ZQr7P5uf//iKqfA=; b=msVajEA9fQov0/juDt2SQnZN8An8Q7hds0IX2w5btLGc8lvn27pPlGgFE+XejDq2xg l22r9bMpitJHsyelVyLGO4RfDLz0DEej12T/Qa6+DqAemcjGR8lM2sOUWa4w+eVtpA3O 23Y5gGYoZwGWZ387Ub77XciGh5bpJs9iS38GRXCVLxSACkmztIrsOFh012ZAFgFuCJKU /lc68pm4pk1aF99FZE6nukWEWiGPXjnBVlDIMZI+PIMLPgn20P2CwrvjthYGTG/5AoZf 9kd1UEwqTpi4SiFuDA1NWehEIOw+fS2ysjaMmdo1MCH/AKI6GaLjRZDYd1aKut6S1wQK U9rw== X-Gm-Message-State: APjAAAVpXX7uyGKgBHDHOAiO8pmjwaF9FvrI0YE+wvmhsouvQWg+81QC UIQeo6i8BBI1AtR8SECv54XDt+sylOc8lw== X-Google-Smtp-Source: APXvYqw7BRWF8plI8O/TYyQdHUdkIajr8S9D6VR5kNxCl4bHnrCkciV250Nz2+Io0BjYX0oErKlfOA== X-Received: by 2002:a05:600c:224a:: with SMTP id a10mr1033302wmm.143.1581978042723; Mon, 17 Feb 2020 14:20:42 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 17 Feb 2020 22:20:34 +0000 Message-Id: <20200217222034.11949-1-julien@xen.org> X-Mailer: git-send-email 2.17.1 Subject: [Xen-devel] [PATCH] xen/arm: Workaround clang/armclang support for register allocation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Andrii Anisov MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Clang 8.0 (see [1]) and by extent some of the version of armclang does not support register allocation using the syntax rN. Thankfully, both GCC [2] and clang are able to support the xN syntax for Arm64. Introduce a new macro ASM_REG() and use in common code for register allocation. [1] https://reviews.llvm.org/rL328829 [2] https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html Cc: Andrii Anisov Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Tested-by: Stefano Stabellini --- xen/include/asm-arm/asm_defns.h | 8 +++- xen/include/asm-arm/smccc.h | 74 ++++++++++++++++----------------- 2 files changed, 44 insertions(+), 38 deletions(-) diff --git a/xen/include/asm-arm/asm_defns.h b/xen/include/asm-arm/asm_defn= s.h index b4fbcdae1d..29a9dbb002 100644 --- a/xen/include/asm-arm/asm_defns.h +++ b/xen/include/asm-arm/asm_defns.h @@ -7,11 +7,17 @@ #endif #include =20 -/* For generic assembly code: use macros to define operand sizes. */ +/* Macros for generic assembly code */ #if defined(CONFIG_ARM_32) # define __OP32 +# define ASM_REG(index) asm("r" # index) #elif defined(CONFIG_ARM_64) # define __OP32 "w" +/* + * Clang < 8.0 doesn't support register alllocation using the syntax rN. + * See https://reviews.llvm.org/rL328829. + */ +# define ASM_REG(index) asm("x" # index) #else # error "unknown ARM variant" #endif diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 126399dd70..9d94beb3df 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -120,59 +120,59 @@ struct arm_smccc_res { #define __constraint_read_6 __constraint_read_5, "r" (r6) #define __constraint_read_7 __constraint_read_6, "r" (r7) =20 -#define __declare_arg_0(a0, res) \ - struct arm_smccc_res *___res =3D res; \ - register unsigned long r0 asm("r0") =3D (uint32_t)a0;\ - register unsigned long r1 asm("r1"); \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") - -#define __declare_arg_1(a0, a1, res) \ - typeof(a1) __a1 =3D a1; \ - struct arm_smccc_res *___res =3D res; \ - register unsigned long r0 asm("r0") =3D (uint32_t)a0;\ - register unsigned long r1 asm("r1") =3D __a1; \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") - -#define __declare_arg_2(a0, a1, a2, res) \ - typeof(a1) __a1 =3D a1; \ - typeof(a2) __a2 =3D a2; \ - struct arm_smccc_res *___res =3D res; \ - register unsigned long r0 asm("r0") =3D (uint32_t)a0;\ - register unsigned long r1 asm("r1") =3D __a1; \ - register unsigned long r2 asm("r2") =3D __a2; \ - register unsigned long r3 asm("r3") - -#define __declare_arg_3(a0, a1, a2, a3, res) \ - typeof(a1) __a1 =3D a1; \ - typeof(a2) __a2 =3D a2; \ - typeof(a3) __a3 =3D a3; \ - struct arm_smccc_res *___res =3D res; \ - register unsigned long r0 asm("r0") =3D (uint32_t)a0;\ - register unsigned long r1 asm("r1") =3D __a1; \ - register unsigned long r2 asm("r2") =3D __a2; \ - register unsigned long r3 asm("r3") =3D __a3 +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res =3D res; \ + register unsigned long r0 ASM_REG(0) =3D (uint32_t)a0; \ + register unsigned long r1 ASM_REG(1); \ + register unsigned long r2 ASM_REG(2); \ + register unsigned long r3 ASM_REG(3) + +#define __declare_arg_1(a0, a1, res) \ + typeof(a1) __a1 =3D a1; \ + struct arm_smccc_res *___res =3D res; \ + register unsigned long r0 ASM_REG(0) =3D (uint32_t)a0; \ + register unsigned long r1 ASM_REG(1) =3D __a1; \ + register unsigned long r2 ASM_REG(2); \ + register unsigned long r3 ASM_REG(3) + +#define __declare_arg_2(a0, a1, a2, res) \ + typeof(a1) __a1 =3D a1; \ + typeof(a2) __a2 =3D a2; \ + struct arm_smccc_res *___res =3D res; \ + register unsigned long r0 ASM_REG(0) =3D (uint32_t)a0; \ + register unsigned long r1 ASM_REG(1) =3D __a1; \ + register unsigned long r2 ASM_REG(2) =3D __a2; \ + register unsigned long r3 ASM_REG(3) + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + typeof(a1) __a1 =3D a1; \ + typeof(a2) __a2 =3D a2; \ + typeof(a3) __a3 =3D a3; \ + struct arm_smccc_res *___res =3D res; \ + register unsigned long r0 ASM_REG(0) =3D (uint32_t)a0; \ + register unsigned long r1 ASM_REG(1) =3D __a1; \ + register unsigned long r2 ASM_REG(2) =3D __a2; \ + register unsigned long r3 ASM_REG(3) =3D __a3 =20 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ typeof(a4) __a4 =3D a4; \ __declare_arg_3(a0, a1, a2, a3, res); \ - register unsigned long r4 asm("r4") =3D __a4 + register unsigned long r4 ASM_REG(4) =3D __a4 =20 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ typeof(a5) __a5 =3D a5; \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register typeof(a5) r5 asm("r5") =3D __a5 + register typeof(a5) r5 ASM_REG(5) =3D __a5 =20 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ typeof(a6) __a6 =3D a6; \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register typeof(a6) r6 asm("r6") =3D __a6 + register typeof(a6) r6 ASM_REG(6) =3D __a6 =20 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ typeof(a7) __a7 =3D a7; \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register typeof(a7) r7 asm("r7") =3D __a7 + register typeof(a7) r7 ASM_REG(7) =3D __a7 =20 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) --=20 2.17.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel