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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:09 -0800 (PST) X-Inumbo-ID: c1a07d22-16ec-11ea-aea8-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jgWMYHD023tAXPY9yBvY7HlxUi3NtG7yB+YFJsFM+4s=; b=GnME/3GQIkWEOnq+HnWtjzDW7KOeACVPsdHQBWSmyQiiOW1JrEqbNdO1yXHOHEGGLa uiDQATmlJ+LFhPgQXv8Zf0F4NJElVwhSGKvmCcAUMQv+wEkB+XJDpMyg6iSNtxNh7VMy 4YRsLqt/0+myzBWoF8xlK6sHJAEmEPWcOsskDtof8qDxEGxli6obH0/ql8HXvOYyNOx0 E4CqVF/g/r8Y9BXPjdTCfVR8SCXfFoQnrtKWfB6fqzn7mEoF7LZSIahhhG8TlbwvWdi0 eV1TWGsF+FoGohnl0fwH163lctm1VQfxvAxKHjBKsqfJP8bqMssseBKgpDoDEsAqYzvT ACgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jgWMYHD023tAXPY9yBvY7HlxUi3NtG7yB+YFJsFM+4s=; b=OyIfgJYauUL2HigduwTsnkA7ATKr/Ta+CcZSp/L481yu/w2doFEviF+zzzzgUCiVWg hqWM9M6PEqtXYAVaBpoxIyuSqy1/Xkh5pmmv3cv7IGOQissOZqhMMqUdIHWmBGZXyc5I IZodEJ7H4UAgLCI4WwjuAQPxua+MrEs9tsBI1GUz+7YwLd0Cd7dCSs648rJQCzjaBb8z j6LnWLo3b4+IPmFXrCaWqmjsnhIu3aeP2NXf/stTHhCJB2M9F6M6HWTmjG5Bh7uLJ4mC XIxyIplgp2KBN5lwtWoE2Vsj7QDyGpr9rsSQdXz1tUPj4ZgzyAph9E7o3WhbxOEl2J0X Slmw== X-Gm-Message-State: APjAAAVMrE5UR+QgTWpvEQvpj3agGk58MshIk5YPeV8s2bqMTEyLMdoc ztBc529Xpd6v3XjklxUvCU6SvA== X-Google-Smtp-Source: APXvYqxYW3lHiAaEktvIv9R2Rs4Q7wh7u41fkOvqH028QUBhjHchCrv3OL1EskvJ6xR8p1wI4qmnmw== X-Received: by 2002:a05:620a:102e:: with SMTP id a14mr5398925qkk.159.1575501670158; Wed, 04 Dec 2019 15:21:10 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:57 -0500 Message-Id: <20191204232058.2500117-6-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The assmbly functions __asm_flush_cache_user_range and __asm_invalidate_icache_range have alternatives: alternative_if ARM64_HAS_CACHE_DIC ... alternative_if ARM64_HAS_CACHE_IDC ... But, the implementation of those alternatives is trivial and therefore can be done in the C inline wrappers. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/arm64/mm/cache.S | 27 +++++---------------------- arch/arm64/mm/flush.c | 1 + 3 files changed, 25 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/c= acheflush.h index ea563344b4ad..4eb244ee7154 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -75,8 +75,22 @@ extern void sync_icache_aliases(void *kaddr, unsigned lo= ng len); static inline void __flush_cache_user_range(unsigned long start, unsigned long end) { + if (cpus_have_const_cap(ARM64_HAS_CACHE_IDC)) { + dsb(ishst); + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return; + } + } + uaccess_ttbr0_enable(); __asm_flush_cache_user_range(start, end); + + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) + isb(); + else + __asm_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); } =20 @@ -90,6 +104,11 @@ static inline int invalidate_icache_range(unsigned long= start, { int ret; =20 + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return 0; + } + uaccess_ttbr0_enable(); ret =3D __asm_invalidate_icache_range(start, end); uaccess_ttbr0_disable(); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 1981cbaf5d92..0093bb9fcd12 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -25,30 +25,18 @@ * - end - virtual end address of region */ ENTRY(__asm_flush_cache_user_range) -alternative_if ARM64_HAS_CACHE_IDC - dsb ishst - b 7f -alternative_else_nop_endif dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 -1: -user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE +1: user_alt 3f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CA= CHE add x4, x4, x2 cmp x4, x1 b.lo 1b dsb ish - -7: -alternative_if ARM64_HAS_CACHE_DIC - isb - b 8f -alternative_else_nop_endif - invalidate_icache_by_line x0, x1, x2, x3, 9f -8: mov x0, #0 -1: ret -9: mov x0, #-EFAULT - b 1b + mov x0, #0 +2: ret +3: mov x0, #-EFAULT + b 2b ENDPROC(__asm_flush_cache_user_range) =20 /* @@ -60,11 +48,6 @@ ENDPROC(__asm_flush_cache_user_range) * - end - virtual end address of region */ ENTRY(__asm_invalidate_icache_range) -alternative_if ARM64_HAS_CACHE_DIC - mov x0, xzr - isb - ret -alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr 1: ret diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index 61521285f27d..adfdacb163ad 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -76,6 +76,7 @@ EXPORT_SYMBOL(flush_dcache_page); * Additional functions defined in assembly. */ EXPORT_SYMBOL(__asm_flush_cache_user_range); +EXPORT_SYMBOL(__asm_invalidate_icache_range); =20 #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel