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x-conformance=sidf_compatible IronPort-SDR: iPksKnYeTMhYWE/QZoznU8HotAXdvRMmeE3koLD2pULWUZGrtZQrLJtQK2HzB0al299lrqNFnL WsVBEr6linaRf9lNboSwI+w4D+xz2OUbN7/bLft0jQ5iZFkdLJEwHp5+TBVzf9BGeGBAJ0TC4o NniGPtufpkyZIrNv+AxCivhZaFybHPXh/QCh48RbVAHS50Iad7r8d0KWTLfFwKEtA+mcDPgcij sVfBG8lp1HIjlJvnpjFrvFeE98Goqhv6EMGXxCFJRkz8x/7jwSY0qCMysswkzeHSQcNpux4Y9l x04= X-SBRS: 2.7 X-MesageID: 8801970 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,242,1571716800"; d="scan'208";a="8801970" From: Roger Pau Monne To: Date: Mon, 25 Nov 2019 18:22:12 +0100 Message-ID: <20191125172213.1904-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191125172213.1904-1-roger.pau@citrix.com> References: <20191125172213.1904-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] x86/tlbflush: do not toggle the PGE CR4 bit unless necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) When PCID is not available Xen does a full tlbflush by toggling the PGE bit in CR4. This is not necessary if PGE is not enabled, since a flush can be performed by writing to CR3 in that case. Change the code in do_tlb_flush to only toggle the PGE bit in CR4 if it's already enabled, otherwise do the tlb flush by writing to CR3. This is relevant when running virtualized, since hypervisors don't usually trap accesses to CR3 when using hardware assisted paging, but do trap accesses to CR4 specially on AMD hardware, which makes such accesses much more expensive. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/flushtlb.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index c1ae0d9467..540209c856 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -84,6 +84,7 @@ static void post_flush(u32 t) static void do_tlb_flush(void) { unsigned long flags; + unsigned long cr4; u32 t; =20 /* This non-reentrant function is sometimes called in interrupt contex= t. */ @@ -93,13 +94,13 @@ static void do_tlb_flush(void) =20 if ( use_invpcid ) invpcid_flush_all(); - else + else if ( (cr4 =3D read_cr4()) & X86_CR4_PGE ) { - unsigned long cr4 =3D read_cr4(); - - write_cr4(cr4 ^ X86_CR4_PGE); + write_cr4(cr4 & ~X86_CR4_PGE); write_cr4(cr4); } + else + write_cr3(read_cr3()); =20 post_flush(t); =20 --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel