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x-conformance=sidf_compatible IronPort-SDR: iPksKnYeTMhYWE/QZoznU8HotAXdvRMmeE3koLD2pULWUZGrtZQrLJtQK2HzB0al299lrqNFnL WsVBEr6linaRf9lNboSwI+w4D+xz2OUbN7/bLft0jQ5iZFkdLJEwHp5+TBVzf9BGeGBAJ0TC4o NniGPtufpkyZIrNv+AxCivhZaFybHPXh/QCh48RbVAHS50Iad7r8d0KWTLfFwKEtA+mcDPgcij sVfBG8lp1HIjlJvnpjFrvFeE98Goqhv6EMGXxCFJRkz8x/7jwSY0qCMysswkzeHSQcNpux4Y9l x04= X-SBRS: 2.7 X-MesageID: 8801970 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,242,1571716800"; d="scan'208";a="8801970" From: Roger Pau Monne To: Date: Mon, 25 Nov 2019 18:22:12 +0100 Message-ID: <20191125172213.1904-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191125172213.1904-1-roger.pau@citrix.com> References: <20191125172213.1904-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] x86/tlbflush: do not toggle the PGE CR4 bit unless necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) When PCID is not available Xen does a full tlbflush by toggling the PGE bit in CR4. This is not necessary if PGE is not enabled, since a flush can be performed by writing to CR3 in that case. Change the code in do_tlb_flush to only toggle the PGE bit in CR4 if it's already enabled, otherwise do the tlb flush by writing to CR3. This is relevant when running virtualized, since hypervisors don't usually trap accesses to CR3 when using hardware assisted paging, but do trap accesses to CR4 specially on AMD hardware, which makes such accesses much more expensive. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/flushtlb.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index c1ae0d9467..540209c856 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -84,6 +84,7 @@ static void post_flush(u32 t) static void do_tlb_flush(void) { unsigned long flags; + unsigned long cr4; u32 t; =20 /* This non-reentrant function is sometimes called in interrupt contex= t. */ @@ -93,13 +94,13 @@ static void do_tlb_flush(void) =20 if ( use_invpcid ) invpcid_flush_all(); - else + else if ( (cr4 =3D read_cr4()) & X86_CR4_PGE ) { - unsigned long cr4 =3D read_cr4(); - - write_cr4(cr4 ^ X86_CR4_PGE); + write_cr4(cr4 & ~X86_CR4_PGE); write_cr4(cr4); } + else + write_cr3(read_cr3()); =20 post_flush(t); =20 --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Thu Apr 18 15:30:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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x-conformance=sidf_compatible IronPort-SDR: DwPu4g3a0xLC+dlfVkFIyK61jwVo0XMhVmRAkoU4toz52thRMGVNQX7lGhX13GXNnvQ+JqTLrh NnOjXmbcoW0PKlXD/2X9C1i4yYdh6YQUfFJUCSYEhz1rJCd3VigqcBKKo7xVkWRxA5oAclSDcR i79eFft1BlFzIJaRWaxWwR/ag56g9+UJKumocP/yrGX+Dx+6kq50cd9hVEZLnZkY6no1JLSa5q f3p9UlgGr64JF9nVdzaC9RR/hkcdLe8h1toFUtOZ0W2nf88ULl2BR4HOi+XTTv3+6laJSDDEDy ibo= X-SBRS: 2.7 X-MesageID: 9352181 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,242,1571716800"; d="scan'208";a="9352181" From: Roger Pau Monne To: Date: Mon, 25 Nov 2019 18:22:13 +0100 Message-ID: <20191125172213.1904-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191125172213.1904-1-roger.pau@citrix.com> References: <20191125172213.1904-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/2] x86/pvshim: do not enable global pages in shim mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) When using global pages a full tlb flush can only be performed by toggling the PGE bit in CR4, which is usually quite expensive in terms of performance when running virtualized. This is specially relevant on AMD hardware, which doesn't have the ability to do selective CR4 trapping, but can also be relevant on Intel if the underlying hypervisor also traps on accesses to the PGE CR4 bit. In order to avoid this performance penalty, do not use global pages when running in shim mode. Note this is done when running on both Intel or AMD hardware, since older versions of Xen capable of running the shim don't make use of Intel selective CR4 trapping feature and will vmexit on every access to CR4. The above figures are from a PV shim running on AMD hardware with 32 vCPUs: PGE enabled, x2APIC mode: (XEN) Global lock flush_lock: addr=3Dffff82d0804b01c0, lockval=3D1adb1adb, = not locked (XEN) lock:1841883(1375128998543), block:1658716(10193054890781) Average lock time: 746588ns Average block time: 6145147ns PGE disabled, x2APIC mode: (XEN) Global lock flush_lock: addr=3Dffff82d0804af1c0, lockval=3Da8bfa8bf, = not locked (XEN) lock:2730175(657505389886), block:2039716(2963768247738) Average lock time: 240829ns Average block time: 1453029ns As seen from the above figures the block time of the flush lock is reduced to approximately 1/3 of the original value. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/pv/domain.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 4b6f48dea2..36f3903dcb 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -13,6 +13,7 @@ #include #include #include +#include #include =20 static __read_mostly enum { @@ -130,7 +131,7 @@ unsigned long pv_make_cr4(const struct vcpu *v) */ if ( d->arch.pv.pcid ) cr4 |=3D X86_CR4_PCIDE; - else if ( !d->arch.pv.xpti ) + else if ( !d->arch.pv.xpti && !pv_shim ) cr4 |=3D X86_CR4_PGE; =20 /* --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel