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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: agOf/DVA1bB2E4rTKnKYH7BlLyWQynXlD8MNHTkwsoRKSnbwxQeSs79Xc13MY1vf8wUP4QNK0S asAd38W89CG85UsuLL9Ow8GLaYKtvfrstZsy70hSkQnDM2E75Ug3XNDiaGItmFTxmdK4UYF8Qm M4gxCnp8SaNSUL48PErZpbskEjZHwTIMwUDHYFoyJI2cVd/UNTHCB6wasCzm3QIA9KMaJ7Dp6C Fe6OVOh8H0/H06zO+J4RiwX41fzn2DHs9MWBHLv+u6Z2Kj+xcqPiWAAhVH9dnGu3vu+z0R6vEe G+k= X-SBRS: 2.7 X-MesageID: 9042800 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,227,1571716800"; d="scan'208";a="9042800" From: Andrew Cooper To: Xen-devel Date: Thu, 21 Nov 2019 22:15:51 +0000 Message-ID: <20191121221551.1175-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191121221551.1175-1-andrew.cooper3@citrix.com> References: <20191121221551.1175-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/2] x86/svm: Write the correct %eip into the outgoing task X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The TASK_SWITCH vmexit has fault semantics, and doesn't provide any NRIPs assistance with instruction length. As a result, any instruction-induced t= ask switch has the outgoing task's %eip pointing at the instruction switch caus= ed the switch, rather than after it. This causes explicit use of task gates to livelock (as when the task return= s, it executes the task-switching instruction again), and any restartable task= to become a nop after its first instantiation (the entry state points at the ret/iret instruction used to exit the task). 32bit Windows in particular is known to use task gates for NMI handling, and to use NMI IPIs. In the task switch handler, distinguish instruction-induced from interrupt/exception-induced task switches, and decode the instruction under %rip to calculate its length. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 CC: Juergen Gross The implementation of svm_get_task_switch_insn_len() is bug-compatible with svm_get_insn_len() when it comes to conditional #GP'ing. I still haven't h= ad time to address this more thoroughly. AMD does permit TASK_SWITCH not to be intercepted and, I'm informed does do the right thing when it comes to a TSS crossing a page boundary. However, = it is not actually safe to leave task switches unintercepted. Any NPT or shad= ow page fault, even from logdirty/paging/etc will corrupt guest state in an unrecoverable manner. --- xen/arch/x86/hvm/svm/emulate.c | 55 +++++++++++++++++++++++++++++++= ++++ xen/arch/x86/hvm/svm/svm.c | 46 ++++++++++++++++++++++------- xen/include/asm-x86/hvm/svm/emulate.h | 1 + 3 files changed, 92 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/hvm/svm/emulate.c b/xen/arch/x86/hvm/svm/emulate.c index 3e52592847..176c25f60d 100644 --- a/xen/arch/x86/hvm/svm/emulate.c +++ b/xen/arch/x86/hvm/svm/emulate.c @@ -117,6 +117,61 @@ unsigned int svm_get_insn_len(struct vcpu *v, unsigned= int instr_enc) } =20 /* + * TASK_SWITCH vmexits never provide an instruction length. We must always + * decode under %rip to find the answer. + */ +unsigned int svm_get_task_switch_insn_len(struct vcpu *v) +{ + struct hvm_emulate_ctxt ctxt; + struct x86_emulate_state *state; + unsigned int emul_len, modrm_reg; + + ASSERT(v =3D=3D current); + hvm_emulate_init_once(&ctxt, NULL, guest_cpu_user_regs()); + hvm_emulate_init_per_insn(&ctxt, NULL, 0); + state =3D x86_decode_insn(&ctxt.ctxt, hvmemul_insn_fetch); + if ( IS_ERR_OR_NULL(state) ) + return 0; + + emul_len =3D x86_insn_length(state, &ctxt.ctxt); + + /* + * Check for an instruction which can cause a task switch. Any far + * jmp/call/ret, any software interrupt/exception, and iret. + */ + switch ( ctxt.ctxt.opcode ) + { + case 0xff: /* Grp 5 */ + /* call / jmp (far, absolute indirect) */ + if ( x86_insn_modrm(state, NULL, &modrm_reg) !=3D 3 || + (modrm_reg !=3D 3 && modrm_reg !=3D 5) ) + { + /* Wrong instruction. Throw #GP back for now. */ + default: + hvm_inject_hw_exception(TRAP_gp_fault, 0); + emul_len =3D 0; + break; + } + /* Fallthrough */ + case 0x62: /* bound */ + case 0x9a: /* call (far, absolute) */ + case 0xca: /* ret imm16 (far) */ + case 0xcb: /* ret (far) */ + case 0xcc: /* int3 */ + case 0xcd: /* int imm8 */ + case 0xce: /* into */ + case 0xcf: /* iret */ + case 0xea: /* jmp (far, absolute) */ + case 0xf1: /* icebp */ + break; + } + + x86_emulate_free_state(state); + + return emul_len; +} + +/* * Local variables: * mode: C * c-file-style: "BSD" diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 049b800e20..ba9c24a70c 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -2776,7 +2776,41 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) =20 case VMEXIT_TASK_SWITCH: { enum hvm_task_switch_reason reason; - int32_t errcode =3D -1; + int32_t errcode =3D -1, insn_len =3D -1; + + /* + * All TASK_SWITCH intercepts have fault-like semantics. NRIP is + * never provided, even for instruction-induced task switches, but= we + * need to know the instruction length in order to set %eip suitab= ly + * in the outgoing TSS. + * + * For a task switch which vectored through the IDT, look at the t= ype + * to distinguish interrupts/exceptions from instruction based + * switches. + */ + if ( vmcb->eventinj.fields.v ) + { + /* + * HW_EXCEPTION, NMI and EXT_INTR are not instruction based. = All + * others are. + */ + if ( vmcb->eventinj.fields.type <=3D X86_EVENTTYPE_HW_EXCEPTIO= N ) + insn_len =3D 0; + + /* + * Clobber the vectoring information, as we are going to emula= te + * the task switch in full. + */ + vmcb->eventinj.bytes =3D 0; + } + + /* + * insn_len being -1 indicates that we have an instruction-induced + * task switch. Decode under %rip to find its length. + */ + if ( insn_len < 0 && (insn_len =3D svm_get_task_switch_insn_len(v)= ) =3D=3D 0 ) + break; + if ( (vmcb->exitinfo2 >> 36) & 1 ) reason =3D TSW_iret; else if ( (vmcb->exitinfo2 >> 38) & 1 ) @@ -2786,15 +2820,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) if ( (vmcb->exitinfo2 >> 44) & 1 ) errcode =3D (uint32_t)vmcb->exitinfo2; =20 - /* - * Some processors set the EXITINTINFO field when the task switch - * is caused by a task gate in the IDT. In this case we will be - * emulating the event injection, so we do not want the processor - * to re-inject the original event! - */ - vmcb->eventinj.bytes =3D 0; - - hvm_task_switch(vmcb->exitinfo1, reason, errcode, 0); + hvm_task_switch(vmcb->exitinfo1, reason, errcode, insn_len); break; } =20 diff --git a/xen/include/asm-x86/hvm/svm/emulate.h b/xen/include/asm-x86/hv= m/svm/emulate.h index 9af10061c5..d7364f774a 100644 --- a/xen/include/asm-x86/hvm/svm/emulate.h +++ b/xen/include/asm-x86/hvm/svm/emulate.h @@ -51,6 +51,7 @@ struct vcpu; =20 unsigned int svm_get_insn_len(struct vcpu *v, unsigned int instr_enc); +unsigned int svm_get_task_switch_insn_len(struct vcpu *v); =20 #endif /* __ASM_X86_HVM_SVM_EMULATE_H__ */ =20 --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel