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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id t2sm1811634qkt.95.2019.11.21.10.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 10:48:12 -0800 (PST) X-Inumbo-ID: 788e2f10-0c8f-11ea-9631-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=axPPUV0SB+vUmPVZgPMEMsCF47yjKoLE+O1nnwx+cnE=; b=VnTNhd+EatzRBtm1XcR533FrbwGf6aLw7QhpytJvJy4EhUmmV/2yP3xUqt7lFpIi/t i00tZ43HaUGN66rML32ooET+jxlZHfUjfezLLaqjb7KDsRbZ7lg/mO/o8wZieqN8iJUT +QoonEXW0BfZhSTjghR2etYtEmgTJR3swErv6QzioOTvVMnXj1TSHJA4iDWgQiLXhhjH 9LVv9m7VPOB1+Fmoo+7VAGCOJFyx6j4MokamjH8mcuP9caILW96vLHR71+Lg0ILl+jFT j2/ggw1yYD1pJ6Q7PnBcZPDVgy5c5TxvQGBJeoep+U8Q8XLVu0QurJEAGj5Be6Zayhiq V3fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=axPPUV0SB+vUmPVZgPMEMsCF47yjKoLE+O1nnwx+cnE=; b=ZsQgCUvg/BAOz0b9R7NKw5yRkak0emRkkwA+EruaJGKgtIz3JbpYpgt9lHBdVOXgfW JYBNi7/cbj93O/XCkjwkALxH6xsD11+8Zu3RKLJGRtT+BXM4ZUEYS4X1//XgOPBPm+6g ylTIuAJnFcEJSKpdf30g5555EwZPjdMyI7jrO+4lDUUPO7YuD1MhhGj335HowcFMc9kz qbyroLTu9lHSG5ZNeXTxQtSsrdzS06rHpI/THdcvYbfz3sbr8Clhi/8NjKD6aUalooEr VJLBV3TsXyzd30YD7HCKTrf4MvwBUcEzctjBN+FU3qds6AF+SziCk7I8zdILtjP2MVSR YSPA== X-Gm-Message-State: APjAAAVUnYKiU3ccCEMmgByiZWvj1sDpOYIIQI9XgzTMVWImycD+l6TU UWb/Mz/5DRFxJuYRKKlS0uapXw== X-Google-Smtp-Source: APXvYqysL5MlYKABTCqCZbfEZQ5tWNC+olDXlMCWgPK4umyOQbgkypKnzsUF0Z83ZrFlAdJbpxiFTw== X-Received: by 2002:ac8:2d2d:: with SMTP id n42mr10008350qta.119.1574362092735; Thu, 21 Nov 2019 10:48:12 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk Date: Thu, 21 Nov 2019 13:48:05 -0500 Message-Id: <20191121184805.414758-4-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121184805.414758-1-pasha.tatashin@soleen.com> References: <20191121184805.414758-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 22 Nov 2019 05:17:22 +0000 Subject: [Xen-devel] [PATCH 3/3] arm64: remove the rest of asm-uaccess.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The __uaccess_ttbr0_disable and __uaccess_ttbr0_enable, are the last two macros defined in asm-uaccess.h. Replace them with C wrappers and call C functions from kernel_entry and kernel_exit. Signed-off-by: Pavel Tatashin Acked-by: Max Filippov # for xtensa bits --- arch/arm64/include/asm/asm-uaccess.h | 38 ---------------------------- arch/arm64/kernel/entry.S | 6 ++--- arch/arm64/lib/clear_user.S | 2 +- arch/arm64/lib/copy_from_user.S | 2 +- arch/arm64/lib/copy_in_user.S | 2 +- arch/arm64/lib/copy_to_user.S | 2 +- arch/arm64/mm/cache.S | 1 - arch/arm64/mm/context.c | 12 +++++++++ arch/xtensa/kernel/coprocessor.S | 1 - 9 files changed, 19 insertions(+), 47 deletions(-) delete mode 100644 arch/arm64/include/asm/asm-uaccess.h diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/= asm-uaccess.h deleted file mode 100644 index 8f763e5b41b1..000000000000 --- a/arch/arm64/include/asm/asm-uaccess.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ASM_UACCESS_H -#define __ASM_ASM_UACCESS_H - -#include -#include -#include -#include -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK - sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swap= per_pg_dir - msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 - isb - add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE - msr ttbr1_el1, \tmp1 // set reserved ASID - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1, tmp2 - get_current_task \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - mrs \tmp2, ttbr1_el1 - extr \tmp2, \tmp2, \tmp1, #48 - ror \tmp2, \tmp2, #16 - msr ttbr1_el1, \tmp2 // set the active ASID - isb - msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 - isb - .endm -#endif -#endif diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 583f71abbe98..c7b571e6d0f2 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include =20 /* @@ -219,7 +219,7 @@ alternative_else_nop_endif and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR .endif =20 - __uaccess_ttbr0_disable x21 + bl __uaccess_ttbr0_disable_c 1: #endif =20 @@ -293,7 +293,7 @@ alternative_else_nop_endif tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT i= s set .endif =20 - __uaccess_ttbr0_enable x0, x1 + bl __uaccess_ttbr0_enable_c =20 .if \el =3D=3D 0 /* diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index aeafc03e961a..b0b4a86a09e2 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -6,7 +6,7 @@ */ #include =20 -#include +#include #include =20 .text diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_use= r.S index ebb3c06cbb5d..142bc7505518 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 3d8153a1ebce..04dc48ca26f7 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -7,7 +7,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 357eae2c18eb..8f3218ae88ab 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 408d317a47d2..7940d6ef5da5 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -12,7 +12,6 @@ #include #include #include -#include =20 /* * __arch_flush_icache_range(start,end) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b5e329fde2dd..4fc32c504dea 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -237,6 +237,18 @@ void check_and_switch_context(struct mm_struct *mm, un= signed int cpu) cpu_switch_mm(mm->pgd, mm); } =20 +#ifdef CONFIG_ARM64_SW_TTBR0_PAN +asmlinkage void __uaccess_ttbr0_enable_c(void) +{ + __uaccess_ttbr0_enable(); +} + +asmlinkage void __uaccess_ttbr0_disable_c(void) +{ + __uaccess_ttbr0_disable(); +} +#endif + /* Errata workaround post TTBRx_EL1 update. */ asmlinkage void post_ttbr_update_workaround(void) { diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index 80828b95a51f..6329d17e2aa0 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel