From nobody Fri May 10 01:11:00 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1574399898; cv=none; d=zoho.com; s=zohoarc; b=YD/C8i3+4Pggrsqhv8iWP+hrtaJ0BmS6VQ0Oj2/SbwwfO3ntpdZZLedbz6tjhiM2i/4yJ/dV1tWLE4JZnuTXlA85n9bqWNfNHV79Oq55maq6RF9gmUMsOz7n96+F2QqKwTQLdAHshgq0KlF8OiNQnUY4jEhZ3lm6C1vNJPp4ssc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574399898; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aFnTC1klJ0eIFZ9SzQI6rloJJvkOuw4mcckNAz9IoHs=; b=Y6pDe2GsYeieZKm6+AeC38gLyUzhkAtcVlmuawQPS8eeKYkjQss1Y+2Zbw1wvj8T4TrGmVDC9LqazUg0iavVhNON/CbxqwD6gt0Tde3MDc8fbrR1JVfMwQGMgENrzhN54VF83VXpFt6HTR2ePQA7TszLduV/rmSgQjVT2xzNSe4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1574399898203543.7874690759139; Thu, 21 Nov 2019 21:18:18 -0800 (PST) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iY1Jr-0006CJ-NH; Fri, 22 Nov 2019 05:17:23 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iXrUz-0006Oh-P0 for xen-devel@lists.xenproject.org; Thu, 21 Nov 2019 18:48:13 +0000 Received: from mail-qv1-xf42.google.com (unknown [2607:f8b0:4864:20::f42]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 76af8356-0c8f-11ea-9631-bc764e2007e4; Thu, 21 Nov 2019 18:48:09 +0000 (UTC) Received: by mail-qv1-xf42.google.com with SMTP id s18so1853348qvr.4 for ; Thu, 21 Nov 2019 10:48:09 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t2sm1811634qkt.95.2019.11.21.10.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 10:48:08 -0800 (PST) X-Inumbo-ID: 76af8356-0c8f-11ea-9631-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6SUpT/Cq7WAcFMI7EYou95uAqCpN60QbhWisTQcUAZE=; b=dH7iy4beDQA0dlnL78YTIs1dGMcBcpDEizGZylqSWQJeyua11ap3URFttiAu/XsDpw uGhONdmEzz1V61aPrClJAF0x4CMm0s/eZ2Au+DZLfBX+sye9mdDqbNx6RNOMoFk7Cv3e G/IBd/It6LWi2PQ9i1n6EDAA/NCvxgP4kytwwT53Qsw5a1Bs4Mz/dzvIZHbdlEfV7Xml Q2+R9+vCRQXedpAVJ9CYG7BcByVgmJ+MFiAh1rMS8sjOULTohB/xGlV+KowLwZ15vuVB +gsRPbtV7gvbSCTrTDy0hIj+pn+t6BjWbW2G3+ValNHGifxejI4aI9CDnh/9t7Jr+4Ft L/0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6SUpT/Cq7WAcFMI7EYou95uAqCpN60QbhWisTQcUAZE=; b=CT3YF74ordmOwN4Pf/3ohfqcrewHG79lErKEAwJRY7LTvw1bh62ZTpUYzuuLIUywDT katXezPXwWBEQcUJ/KCMZrAgbflcwleF33qX6HuGmA7Twuj+F1CeVG597X/bdVLpJ0zj tZBq6ZfdLet8y0QtFzuEG5Z5RMzraFTt5w8Yma7daSpge5KZNbJv+xB4uFubMMvOlND9 0Q15cEkA/NtSryC0eAOsUKxWVJO0QMFFjk4FlRBeSJpVf3x8cIQnyeYqZuB9IK15byjc vKihQskXE6GrCLOQ3YmAumkfck1Ot9xGG2Gv95dJHYTGBRSOVDFtSRLiMaM9RNzSQhCw EVXA== X-Gm-Message-State: APjAAAXoPMtse12Qizn366QvfUrfPP9kbCGhzJWXYm/HWc78QSf3YsFJ wk1TTII62maSDazRcdypombl6A== X-Google-Smtp-Source: APXvYqwHPZo6IUc+mQlModGko0y+bUwKpgW94ZH45M2odE42WQE3R6U+OVG3m1WRxN6oOvJcf7Ymkw== X-Received: by 2002:ad4:44af:: with SMTP id n15mr358027qvt.174.1574362089507; Thu, 21 Nov 2019 10:48:09 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk Date: Thu, 21 Nov 2019 13:48:03 -0500 Message-Id: <20191121184805.414758-2-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121184805.414758-1-pasha.tatashin@soleen.com> References: <20191121184805.414758-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 22 Nov 2019 05:17:22 +0000 Subject: [Xen-devel] [PATCH 1/3] arm/arm64/xen: use C inlines for privcmd_call X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) privcmd_call requires to enable access to userspace for the duration of the hypercall. Currently, this is done via assembly macros. Change it to C inlines instead. Signed-off-by: Pavel Tatashin --- arch/arm/include/asm/assembler.h | 2 +- arch/arm/include/asm/uaccess.h | 32 ++++++++++++++++++++++++++------ arch/arm/xen/enlighten.c | 2 +- arch/arm/xen/hypercall.S | 15 ++------------- arch/arm64/xen/hypercall.S | 19 ++----------------- include/xen/arm/hypercall.h | 23 ++++++++++++++++++++--- 6 files changed, 52 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assemb= ler.h index 99929122dad7..8e9262a0f016 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -480,7 +480,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .macro uaccess_disable, tmp, isb=3D1 #ifdef CONFIG_CPU_SW_DOMAIN_PAN /* - * Whenever we re-enter userspace, the domains should always be + * Whenever we re-enter kernel, the domains should always be * set appropriately. */ mov \tmp, #DACR_UACCESS_DISABLE diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 98c6b91be4a8..79d4efa3eb62 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -16,6 +16,23 @@ =20 #include =20 +#ifdef CONFIG_CPU_SW_DOMAIN_PAN +static __always_inline void uaccess_enable(void) +{ + unsigned long val =3D DACR_UACCESS_ENABLE; + + asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); + isb(); +} + +static __always_inline void uaccess_disable(void) +{ + unsigned long val =3D DACR_UACCESS_ENABLE; + + asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); + isb(); +} + /* * These two functions allow hooking accesses to userspace to increase * system integrity by ensuring that the kernel can not inadvertantly @@ -24,7 +41,6 @@ */ static __always_inline unsigned int uaccess_save_and_enable(void) { -#ifdef CONFIG_CPU_SW_DOMAIN_PAN unsigned int old_domain =3D get_domain(); =20 /* Set the current domain access to permit user accesses */ @@ -32,18 +48,22 @@ static __always_inline unsigned int uaccess_save_and_en= able(void) domain_val(DOMAIN_USER, DOMAIN_CLIENT)); =20 return old_domain; -#else - return 0; -#endif } =20 static __always_inline void uaccess_restore(unsigned int flags) { -#ifdef CONFIG_CPU_SW_DOMAIN_PAN /* Restore the user access mask */ set_domain(flags); -#endif } +#else +static __always_inline void uaccess_enable(void) {} +static __always_inline void uaccess_disable(void) {} +static __always_inline unsigned int uaccess_save_and_enable(void) +{ + return 0; +} +static __always_inline void uaccess_restore(unsigned int flags) {} +#endif /* CONFIG_CPU_SW_DOMAIN_PAN */ =20 /* * These two are intentionally not defined anywhere - if the kernel diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index dd6804a64f1a..e87280c6d25d 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -440,4 +440,4 @@ EXPORT_SYMBOL_GPL(HYPERVISOR_platform_op_raw); EXPORT_SYMBOL_GPL(HYPERVISOR_multicall); EXPORT_SYMBOL_GPL(HYPERVISOR_vm_assist); EXPORT_SYMBOL_GPL(HYPERVISOR_dm_op); -EXPORT_SYMBOL_GPL(privcmd_call); +EXPORT_SYMBOL_GPL(arch_privcmd_call); diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S index b11bba542fac..2f5be0dc6195 100644 --- a/arch/arm/xen/hypercall.S +++ b/arch/arm/xen/hypercall.S @@ -94,29 +94,18 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); =20 -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) stmdb sp!, {r4} mov r12, r0 mov r0, r1 mov r1, r2 mov r2, r3 ldr r3, [sp, #8] - /* - * Privcmd calls are issued by the userspace. We need to allow the - * kernel to access the userspace memory before issuing the hypercall. - */ - uaccess_enable r4 =20 /* r4 is loaded now as we use it as scratch register before */ ldr r4, [sp, #4] __HVC(XEN_IMM) =20 - /* - * Disable userspace access from kernel. This is fine to do it - * unconditionally as no set_fs(KERNEL_DS) is called before. - */ - uaccess_disable r4 - ldm sp!, {r4} ret lr -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index c5f05c4a4d00..921611778d2a 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -49,7 +49,6 @@ =20 #include #include -#include #include =20 =20 @@ -86,27 +85,13 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); =20 -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) mov x16, x0 mov x0, x1 mov x1, x2 mov x2, x3 mov x3, x4 mov x4, x5 - /* - * Privcmd calls are issued by the userspace. The kernel needs to - * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 - * translations to user memory via AT instructions. Since AT - * instructions are not affected by the PAN bit (ARMv8.1), we only - * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation - * is enabled (it implies that hardware UAO and PAN disabled). - */ - uaccess_ttbr0_enable x6, x7, x8 hvc XEN_IMM - - /* - * Disable userspace access from kernel once the hyp call completed. - */ - uaccess_ttbr0_disable x6, x7 ret -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/include/xen/arm/hypercall.h b/include/xen/arm/hypercall.h index b40485e54d80..cfb704fd78c8 100644 --- a/include/xen/arm/hypercall.h +++ b/include/xen/arm/hypercall.h @@ -34,16 +34,33 @@ #define _ASM_ARM_XEN_HYPERCALL_H =20 #include +#include =20 #include #include #include =20 struct xen_dm_op_buf; +long arch_privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5); =20 -long privcmd_call(unsigned call, unsigned long a1, - unsigned long a2, unsigned long a3, - unsigned long a4, unsigned long a5); +static inline long privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5) +{ + long rv; + + /* + * Privcmd calls are issued by the userspace. We need to allow the + * kernel to access the userspace memory before issuing the hypercall. + */ + uaccess_enable(); + rv =3D arch_privcmd_call(call, a1, a2, a3, a4, a5); + uaccess_disable(); + + return rv; +} int HYPERVISOR_xen_version(int cmd, void *arg); int HYPERVISOR_console_io(int cmd, int count, char *str); int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int co= unt); --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 10 01:11:00 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1574399896; cv=none; d=zoho.com; s=zohoarc; b=dRurNaDsHSro3JoltReugzvDJAH32j9eVWvp/NpNM48D2v5zYzYGMNci3EBOdn87py0Sz7sS1CpW1s+W3PDQ32gKkosSNPxI7Xq8dQGFrvWfUUfXF2DEJRxXKgPqNC1J0KaKPpIoBFq+qW9LiG/Cd1ddONR6qw/V9spf93S4n0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574399896; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ikPGLul4H5wWwn09GK6HxzSuqMMpIyeYICynmobg45w=; b=DU3tX/8Y1f3xRj/MDkWpm9fdjTCCpxoWOaN0Nx6GHcMFxasfF7HmU2JuUYKS4MJJXYBzsmq5uy/vxpdrBwnMk167vaE4gbtm8Hh0ukVmpsT1DHhhqNHQMSZlbYABJmRPKJElJKlo6j3UJ5JiQoypE0x5oAUYRncwbfYnfHM2HWI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1574399896627479.4801231519484; Thu, 21 Nov 2019 21:18:16 -0800 (PST) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iY1Jr-0006CP-Vt; Fri, 22 Nov 2019 05:17:23 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iXrV4-0006P0-OV for xen-devel@lists.xenproject.org; Thu, 21 Nov 2019 18:48:18 +0000 Received: from mail-qt1-x842.google.com (unknown [2607:f8b0:4864:20::842]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 77a3a576-0c8f-11ea-b678-bc764e2007e4; Thu, 21 Nov 2019 18:48:11 +0000 (UTC) Received: by mail-qt1-x842.google.com with SMTP id q8so2180118qtr.10 for ; Thu, 21 Nov 2019 10:48:11 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t2sm1811634qkt.95.2019.11.21.10.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 10:48:10 -0800 (PST) X-Inumbo-ID: 77a3a576-0c8f-11ea-b678-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HgQtjc5acLHzjiwVf/zPdL0W3rJRgxp/Mq6B1WIDDxY=; b=D8TF57oZonJsJ7ptNQX1Oql+1bGPweH7IQDgGXFghl6XLlpJMfByo9jtn6lWNVKneh s2cJgTr1kQWATQJrBvnkf95d+I3h7dwVBG/raggpy0IJob7OGHVHg9IPdtDdarosd954 KFR3q4XmVCuDk6cTsFQy47BxZ22+ZDDQIEsZIop543H+GCFV/vAHhe7jJIwfww5UYbL5 Gs9GL4HTjVd2fG46M2jukbPbRS4huhvRfKChueNRZEhzrnriSSgwr01jRIkK+k34OPaf xGvsJeSVsHNnl3tY0THdt6/yxjIzUUj/KIQb1SVBDN0kj4MtWe+F1Muehw4EuSxPRpXX 0l4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HgQtjc5acLHzjiwVf/zPdL0W3rJRgxp/Mq6B1WIDDxY=; b=K34paoVHvImqjjtestqcgTY7oksngYz9w+Pb1eUlu2JH/dG3UzMBntdVhYpu54tpES OazCUZItSQCGIDEo54OD2LEtY8wPu+Tx9D+XU+hIaLRZMGxuS3QNyOStZvrUfNvppRQg ZLlHif+GIYkJl3pR/MyoS3+V7F0NcnGwjsVUYjNDNEWI/LnPFN/1CB+YO/rLa4ih9cZs GtaL38rLW9/QuVMtiEn5OMkZIagj6EiBfeA/uBo0qDlnHsBVJaa3fGvNCOz/RqlKTtLW dOEZKgA2yuTz8JbeAnnCl6gOlk1aQAbS5KKQ1QNSG3eriq3cs8TeT/gdgJbLb+lGc7OD k9dw== X-Gm-Message-State: APjAAAU0yJR9YhP7fw4+f5VwWvvfanVmY+kHmLOK6sp9k1qx9iQy/JQC fBlB1RvQqEjJ6tRry3rhZcKcCw== X-Google-Smtp-Source: APXvYqyC5mwODRFAu6hCA10XUD/HEGjTmVXQZnPp2NesFrAjEuQLsTPPaA4uJEbcoHdfWmybnns7cA== X-Received: by 2002:ac8:7444:: with SMTP id h4mr10138097qtr.102.1574362091132; Thu, 21 Nov 2019 10:48:11 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk Date: Thu, 21 Nov 2019 13:48:04 -0500 Message-Id: <20191121184805.414758-3-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121184805.414758-1-pasha.tatashin@soleen.com> References: <20191121184805.414758-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 22 Nov 2019 05:17:22 +0000 Subject: [Xen-devel] [PATCH 2/3] arm64: remove uaccess_ttbr0 asm macros from cache functions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Replace the uaccess_ttbr0_disable/uaccess_ttbr0_enable via inline variants, and remove asm macros. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/asm-uaccess.h | 22 ---------------- arch/arm64/include/asm/cacheflush.h | 38 +++++++++++++++++++++++++--- arch/arm64/mm/cache.S | 30 ++++++++-------------- arch/arm64/mm/flush.c | 2 +- 4 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/= asm-uaccess.h index 35e6145e1402..8f763e5b41b1 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -34,27 +34,5 @@ msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 isb .endm - - .macro uaccess_ttbr0_disable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_disable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp3 // avoid preemption - __uaccess_ttbr0_enable \tmp1, \tmp2 - restore_irq \tmp3 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1, tmp2 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 - .endm #endif #endif diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/c= acheflush.h index 665c78e0665a..cdd4a8eb8708 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,16 +61,48 @@ * - kaddr - page address * - size - region size */ -extern void __flush_icache_range(unsigned long start, unsigned long end); -extern int invalidate_icache_range(unsigned long start, unsigned long end= ); +extern void __arch_flush_icache_range(unsigned long start, unsigned long e= nd); +extern long __arch_flush_cache_user_range(unsigned long start, + unsigned long end); +extern int arch_invalidate_icache_range(unsigned long start, + unsigned long end); + extern void __flush_dcache_area(void *addr, size_t len); extern void __inval_dcache_area(void *addr, size_t len); extern void __clean_dcache_area_poc(void *addr, size_t len); extern void __clean_dcache_area_pop(void *addr, size_t len); extern void __clean_dcache_area_pou(void *addr, size_t len); -extern long __flush_cache_user_range(unsigned long start, unsigned long en= d); extern void sync_icache_aliases(void *kaddr, unsigned long len); =20 +static inline void __flush_icache_range(unsigned long start, unsigned long= end) +{ + uaccess_ttbr0_enable(); + __arch_flush_icache_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline void __flush_cache_user_range(unsigned long start, + unsigned long end) +{ + uaccess_ttbr0_enable(); + __arch_flush_cache_user_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline int invalidate_icache_range(unsigned long start, + unsigned long end) +{ + int rv; +#if ARM64_HAS_CACHE_DIC + rv =3D arch_invalidate_icache_range(start, end); +#else + uaccess_ttbr0_enable(); + rv =3D arch_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); +#endif + return rv; +} + static inline void flush_icache_range(unsigned long start, unsigned long e= nd) { __flush_icache_range(start, end); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index db767b072601..408d317a47d2 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -15,7 +15,7 @@ #include =20 /* - * flush_icache_range(start,end) + * __arch_flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -24,11 +24,11 @@ * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_icache_range) +ENTRY(__arch_flush_icache_range) /* FALLTHROUGH */ =20 /* - * __flush_cache_user_range(start,end) + * __arch_flush_cache_user_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -37,8 +37,7 @@ ENTRY(__flush_icache_range) * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3, x4 +ENTRY(__arch_flush_cache_user_range) alternative_if ARM64_HAS_CACHE_IDC dsb ishst b 7f @@ -60,14 +59,11 @@ alternative_if ARM64_HAS_CACHE_DIC alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 9f 8: mov x0, #0 -1: - uaccess_ttbr0_disable x1, x2 - ret -9: - mov x0, #-EFAULT +1: ret +9: mov x0, #-EFAULT b 1b -ENDPROC(__flush_icache_range) -ENDPROC(__flush_cache_user_range) +ENDPROC(__arch_flush_icache_range) +ENDPROC(__arch_flush_cache_user_range) =20 /* * invalidate_icache_range(start,end) @@ -83,16 +79,10 @@ alternative_if ARM64_HAS_CACHE_DIC isb ret alternative_else_nop_endif - - uaccess_ttbr0_enable x2, x3, x4 - invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr -1: - uaccess_ttbr0_disable x1, x2 - ret -2: - mov x0, #-EFAULT +1: ret +2: mov x0, #-EFAULT b 1b ENDPROC(invalidate_icache_range) =20 diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index ac485163a4a7..66249fca2092 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__flush_icache_range); +EXPORT_SYMBOL(__arch_flush_icache_range); =20 #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 10 01:11:00 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1574399894; cv=none; d=zoho.com; s=zohoarc; b=kMayhblV7DI3ZiSabJQotmfJbE4dR6A6qCX2yhJjGAy1caI5Su6a6eJCLpeb79YwVbhFT9m939b+SRo1znCtGnOvUiBBtKZWMw4v50s6eYz3AVyjFQc84bozQPLCu4Xp0dbxHClZambvBMfThWPo1ynLBPi7I2dpzkBoE2xz5Xo= ARC-Message-Signature: i=1; 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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id t2sm1811634qkt.95.2019.11.21.10.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 10:48:12 -0800 (PST) X-Inumbo-ID: 788e2f10-0c8f-11ea-9631-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=axPPUV0SB+vUmPVZgPMEMsCF47yjKoLE+O1nnwx+cnE=; b=VnTNhd+EatzRBtm1XcR533FrbwGf6aLw7QhpytJvJy4EhUmmV/2yP3xUqt7lFpIi/t i00tZ43HaUGN66rML32ooET+jxlZHfUjfezLLaqjb7KDsRbZ7lg/mO/o8wZieqN8iJUT +QoonEXW0BfZhSTjghR2etYtEmgTJR3swErv6QzioOTvVMnXj1TSHJA4iDWgQiLXhhjH 9LVv9m7VPOB1+Fmoo+7VAGCOJFyx6j4MokamjH8mcuP9caILW96vLHR71+Lg0ILl+jFT j2/ggw1yYD1pJ6Q7PnBcZPDVgy5c5TxvQGBJeoep+U8Q8XLVu0QurJEAGj5Be6Zayhiq V3fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=axPPUV0SB+vUmPVZgPMEMsCF47yjKoLE+O1nnwx+cnE=; b=ZsQgCUvg/BAOz0b9R7NKw5yRkak0emRkkwA+EruaJGKgtIz3JbpYpgt9lHBdVOXgfW JYBNi7/cbj93O/XCkjwkALxH6xsD11+8Zu3RKLJGRtT+BXM4ZUEYS4X1//XgOPBPm+6g ylTIuAJnFcEJSKpdf30g5555EwZPjdMyI7jrO+4lDUUPO7YuD1MhhGj335HowcFMc9kz qbyroLTu9lHSG5ZNeXTxQtSsrdzS06rHpI/THdcvYbfz3sbr8Clhi/8NjKD6aUalooEr VJLBV3TsXyzd30YD7HCKTrf4MvwBUcEzctjBN+FU3qds6AF+SziCk7I8zdILtjP2MVSR YSPA== X-Gm-Message-State: APjAAAVUnYKiU3ccCEMmgByiZWvj1sDpOYIIQI9XgzTMVWImycD+l6TU UWb/Mz/5DRFxJuYRKKlS0uapXw== X-Google-Smtp-Source: APXvYqysL5MlYKABTCqCZbfEZQ5tWNC+olDXlMCWgPK4umyOQbgkypKnzsUF0Z83ZrFlAdJbpxiFTw== X-Received: by 2002:ac8:2d2d:: with SMTP id n42mr10008350qta.119.1574362092735; Thu, 21 Nov 2019 10:48:12 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk Date: Thu, 21 Nov 2019 13:48:05 -0500 Message-Id: <20191121184805.414758-4-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121184805.414758-1-pasha.tatashin@soleen.com> References: <20191121184805.414758-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 22 Nov 2019 05:17:22 +0000 Subject: [Xen-devel] [PATCH 3/3] arm64: remove the rest of asm-uaccess.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The __uaccess_ttbr0_disable and __uaccess_ttbr0_enable, are the last two macros defined in asm-uaccess.h. Replace them with C wrappers and call C functions from kernel_entry and kernel_exit. Signed-off-by: Pavel Tatashin Acked-by: Max Filippov # for xtensa bits --- arch/arm64/include/asm/asm-uaccess.h | 38 ---------------------------- arch/arm64/kernel/entry.S | 6 ++--- arch/arm64/lib/clear_user.S | 2 +- arch/arm64/lib/copy_from_user.S | 2 +- arch/arm64/lib/copy_in_user.S | 2 +- arch/arm64/lib/copy_to_user.S | 2 +- arch/arm64/mm/cache.S | 1 - arch/arm64/mm/context.c | 12 +++++++++ arch/xtensa/kernel/coprocessor.S | 1 - 9 files changed, 19 insertions(+), 47 deletions(-) delete mode 100644 arch/arm64/include/asm/asm-uaccess.h diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/= asm-uaccess.h deleted file mode 100644 index 8f763e5b41b1..000000000000 --- a/arch/arm64/include/asm/asm-uaccess.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ASM_UACCESS_H -#define __ASM_ASM_UACCESS_H - -#include -#include -#include -#include -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK - sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swap= per_pg_dir - msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 - isb - add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE - msr ttbr1_el1, \tmp1 // set reserved ASID - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1, tmp2 - get_current_task \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - mrs \tmp2, ttbr1_el1 - extr \tmp2, \tmp2, \tmp1, #48 - ror \tmp2, \tmp2, #16 - msr ttbr1_el1, \tmp2 // set the active ASID - isb - msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 - isb - .endm -#endif -#endif diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 583f71abbe98..c7b571e6d0f2 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include =20 /* @@ -219,7 +219,7 @@ alternative_else_nop_endif and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR .endif =20 - __uaccess_ttbr0_disable x21 + bl __uaccess_ttbr0_disable_c 1: #endif =20 @@ -293,7 +293,7 @@ alternative_else_nop_endif tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT i= s set .endif =20 - __uaccess_ttbr0_enable x0, x1 + bl __uaccess_ttbr0_enable_c =20 .if \el =3D=3D 0 /* diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index aeafc03e961a..b0b4a86a09e2 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -6,7 +6,7 @@ */ #include =20 -#include +#include #include =20 .text diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_use= r.S index ebb3c06cbb5d..142bc7505518 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 3d8153a1ebce..04dc48ca26f7 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -7,7 +7,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 357eae2c18eb..8f3218ae88ab 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include #include #include =20 diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 408d317a47d2..7940d6ef5da5 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -12,7 +12,6 @@ #include #include #include -#include =20 /* * __arch_flush_icache_range(start,end) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b5e329fde2dd..4fc32c504dea 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -237,6 +237,18 @@ void check_and_switch_context(struct mm_struct *mm, un= signed int cpu) cpu_switch_mm(mm->pgd, mm); } =20 +#ifdef CONFIG_ARM64_SW_TTBR0_PAN +asmlinkage void __uaccess_ttbr0_enable_c(void) +{ + __uaccess_ttbr0_enable(); +} + +asmlinkage void __uaccess_ttbr0_disable_c(void) +{ + __uaccess_ttbr0_disable(); +} +#endif + /* Errata workaround post TTBRx_EL1 update. */ asmlinkage void post_ttbr_update_workaround(void) { diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index 80828b95a51f..6329d17e2aa0 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include --=20 2.24.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel