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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: SZcS0DGyQKLuaYmLAf6OXr3TzhNvthHqBX4C2IRVcetpsWEtQgCc+x4dXgO87bE6svFtmzzHTc zUTq4OT1qvTqTDmXiTnqb8nNyHch7g9lp5Nk8vYZ1JgU+oERG+Rs9tvrDbqDC1bfZiqdUVOrUo e0LJZDsLTi5RfRGM9WMMuqyZhYHOLaZD8DWMLzDxr1Y/FMp2GhBL7hDjFrAKebq0TO2fc4AHCp sg6Ls9cwX/RY8X+p3owmLkiLiWoZsOuDWV5cbI+u0w4lnGh1BlOdPRcFpF3u0Mh4dSbSEpV+mP o/8= X-SBRS: 2.7 X-MesageID: 8543847 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,218,1571716800"; d="scan'208";a="8543847" From: Andrew Cooper To: Xen-devel Date: Tue, 19 Nov 2019 17:00:19 +0000 Message-ID: <20191119170019.18450-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-4.13] x86/cpuid: Fix Lisbon/Magny-Cours Opterons WRT SSSE3/SSE4A X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) c/s ff66ccefe5 "x86/CPUID: adjust SSEn dependencies" made SSE4A depend on SSSE3, but these processors really do have have SSE4A without SSSE3. This manifests as an upgrade regression, as the SSE4A feature disappears fr= om view. Adjust the SSE4A feature to depend on SSE3 rather than SSSE3. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 CC: Juergen Gross For 4.13. Regression from 4.12 --- xen/tools/gen-cpuid.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 434a6ebf04..2e76f9abc0 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -205,9 +205,10 @@ def crunch_numbers(state): # than to SSE. SSE2: [SSE3, LM, AESNI, PCLMULQDQ, SHA, GFNI], =20 - # Other SSEn each depend on their predecessor versions. - SSE3: [SSSE3], - SSSE3: [SSE4_1, SSE4A], + # Other SSEn each depend on their predecessor versions. AMD + # Lisbon/Magny-Cours processors implemented SSE4A without SSSE3. + SSE3: [SSSE3, SSE4A], + SSSE3: [SSE4_1], SSE4_1: [SSE4_2], =20 # AMD specify no relationship between POPCNT and SSE4.2. Intel --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel