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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: Fm3I7O+gYOo6b6Mlc228AJtGKUrz75ao0/azZGIswBM3uHhAdVmBU1Zixv2Tx/gchUhmasYPCu aNivhkYCHVdmfCk5h3CY7wRgr9D9oyvlmsfmZcn+SFKu5bKuJsfX4zIFFUNUrIVlmXDb7xl38B 0UnKBY7B47Fdy1/YrVrHdqOd88zmp1B3MKEikk9P16bMRcVSNT1UJc6f1oR2rmJbbz4zutIaKb Nrle9F+s20CczqM6YzflAXbeV9jS66cO4TUkyWLB3V+xYqI/vzeO8IBdjyWhXJMEFO01a+emGn pDk= X-SBRS: 2.7 X-MesageID: 4679224 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,405,1559534400"; d="scan'208";a="4679224" From: Andrew Cooper To: Xen-devel Date: Mon, 19 Aug 2019 19:26:11 +0100 Message-ID: <20190819182612.16706-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190819182612.16706-1-andrew.cooper3@citrix.com> References: <20190819182612.16706-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] x86/feature: Generalise synth and introduce a bug word X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Future changes are going to want to use cpu_bug_* in a mannor similar to Linux. Introduce one bug word, and generalise the calculation of NCAPINTS. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 v2: * Rebase --- xen/include/asm-x86/cpufeatures.h | 67 ++++++++++++++++++++++-------------= ---- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufea= tures.h index 57f3e61fd5..ab3650f73b 100644 --- a/xen/include/asm-x86/cpufeatures.h +++ b/xen/include/asm-x86/cpufeatures.h @@ -4,35 +4,44 @@ =20 #include =20 +/* Number of capability words covered by the featureset words. */ #define FSCAPINTS FEATURESET_NR_ENTRIES =20 -#define NCAPINTS (FSCAPINTS + 1) /* N 32-bit words worth of info */ +/* Synthetic words follow the featureset words. */ +#define X86_NR_SYNTH 1 +#define X86_SYNTH(x) (FSCAPINTS * 32 + (x)) =20 -/* Other features, Xen-defined mapping. */ -/* This range is used for feature bits which conflict or are synthesized */ -XEN_CPUFEATURE(CONSTANT_TSC, (FSCAPINTS+0)*32+ 0) /* TSC ticks at a con= stant rate */ -XEN_CPUFEATURE(NONSTOP_TSC, (FSCAPINTS+0)*32+ 1) /* TSC does not stop = in C states */ -XEN_CPUFEATURE(ARAT, (FSCAPINTS+0)*32+ 2) /* Always running API= C timer */ -XEN_CPUFEATURE(ARCH_PERFMON, (FSCAPINTS+0)*32+ 3) /* Intel Architectura= l PerfMon */ -XEN_CPUFEATURE(TSC_RELIABLE, (FSCAPINTS+0)*32+ 4) /* TSC is known to be= reliable */ -XEN_CPUFEATURE(XTOPOLOGY, (FSCAPINTS+0)*32+ 5) /* cpu topology enum = extensions */ -XEN_CPUFEATURE(CPUID_FAULTING, (FSCAPINTS+0)*32+ 6) /* cpuid faulting */ -XEN_CPUFEATURE(CLFLUSH_MONITOR, (FSCAPINTS+0)*32+ 7) /* clflush reqd with = monitor */ -XEN_CPUFEATURE(APERFMPERF, (FSCAPINTS+0)*32+ 8) /* APERFMPERF */ -XEN_CPUFEATURE(MFENCE_RDTSC, (FSCAPINTS+0)*32+ 9) /* MFENCE synchronize= s RDTSC */ -XEN_CPUFEATURE(XEN_SMEP, (FSCAPINTS+0)*32+10) /* SMEP gets used by = Xen itself */ -XEN_CPUFEATURE(XEN_SMAP, (FSCAPINTS+0)*32+11) /* SMAP gets used by = Xen itself */ -XEN_CPUFEATURE(LFENCE_DISPATCH, (FSCAPINTS+0)*32+12) /* lfence set as Disp= atch Serialising */ -XEN_CPUFEATURE(IND_THUNK_LFENCE,(FSCAPINTS+0)*32+13) /* Use IND_THUNK_LFEN= CE */ -XEN_CPUFEATURE(IND_THUNK_JMP, (FSCAPINTS+0)*32+14) /* Use IND_THUNK_JMP = */ -XEN_CPUFEATURE(SC_L1TF_VULN, (FSCAPINTS+0)*32+15) /* L1TF protection re= quired */ -XEN_CPUFEATURE(SC_MSR_PV, (FSCAPINTS+0)*32+16) /* MSR_SPEC_CTRL used= by Xen for PV */ -XEN_CPUFEATURE(SC_MSR_HVM, (FSCAPINTS+0)*32+17) /* MSR_SPEC_CTRL used= by Xen for HVM */ -XEN_CPUFEATURE(SC_RSB_PV, (FSCAPINTS+0)*32+18) /* RSB overwrite need= ed for PV */ -XEN_CPUFEATURE(SC_RSB_HVM, (FSCAPINTS+0)*32+19) /* RSB overwrite need= ed for HVM */ -XEN_CPUFEATURE(XEN_SELFSNOOP, (FSCAPINTS+0)*32+20) /* SELFSNOOP gets use= d by Xen itself */ -XEN_CPUFEATURE(SC_MSR_IDLE, (FSCAPINTS+0)*32+21) /* (SC_MSR_PV || SC_M= SR_HVM) && default_xen_spec_ctrl */ -XEN_CPUFEATURE(XEN_LBR, (FSCAPINTS+0)*32+22) /* Xen uses MSR_DEBUG= CTL.LBR */ -XEN_CPUFEATURE(SC_VERW_PV, (FSCAPINTS+0)*32+23) /* VERW used by Xen f= or PV */ -XEN_CPUFEATURE(SC_VERW_HVM, (FSCAPINTS+0)*32+24) /* VERW used by Xen f= or HVM */ -XEN_CPUFEATURE(SC_VERW_IDLE, (FSCAPINTS+0)*32+25) /* VERW used by Xen f= or idle */ +/* Synthetic features */ +XEN_CPUFEATURE(CONSTANT_TSC, X86_SYNTH( 0)) /* TSC ticks at a constan= t rate */ +XEN_CPUFEATURE(NONSTOP_TSC, X86_SYNTH( 1)) /* TSC does not stop in C= states */ +XEN_CPUFEATURE(ARAT, X86_SYNTH( 2)) /* Always running APIC ti= mer */ +XEN_CPUFEATURE(ARCH_PERFMON, X86_SYNTH( 3)) /* Intel Architectural Pe= rfMon */ +XEN_CPUFEATURE(TSC_RELIABLE, X86_SYNTH( 4)) /* TSC is known to be rel= iable */ +XEN_CPUFEATURE(XTOPOLOGY, X86_SYNTH( 5)) /* cpu topology enum exte= nsions */ +XEN_CPUFEATURE(CPUID_FAULTING, X86_SYNTH( 6)) /* cpuid faulting */ +XEN_CPUFEATURE(CLFLUSH_MONITOR, X86_SYNTH( 7)) /* clflush reqd with moni= tor */ +XEN_CPUFEATURE(APERFMPERF, X86_SYNTH( 8)) /* APERFMPERF */ +XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RD= TSC */ +XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen = itself */ +XEN_CPUFEATURE(XEN_SMAP, X86_SYNTH(11)) /* SMAP gets used by Xen = itself */ +XEN_CPUFEATURE(LFENCE_DISPATCH, X86_SYNTH(12)) /* lfence set as Dispatch= Serialising */ +XEN_CPUFEATURE(IND_THUNK_LFENCE, X86_SYNTH(13)) /* Use IND_THUNK_LFENCE */ +XEN_CPUFEATURE(IND_THUNK_JMP, X86_SYNTH(14)) /* Use IND_THUNK_JMP */ +XEN_CPUFEATURE(SC_L1TF_VULN, X86_SYNTH(15)) /* L1TF protection requir= ed */ +XEN_CPUFEATURE(SC_MSR_PV, X86_SYNTH(16)) /* MSR_SPEC_CTRL used by = Xen for PV */ +XEN_CPUFEATURE(SC_MSR_HVM, X86_SYNTH(17)) /* MSR_SPEC_CTRL used by = Xen for HVM */ +XEN_CPUFEATURE(SC_RSB_PV, X86_SYNTH(18)) /* RSB overwrite needed f= or PV */ +XEN_CPUFEATURE(SC_RSB_HVM, X86_SYNTH(19)) /* RSB overwrite needed f= or HVM */ +XEN_CPUFEATURE(XEN_SELFSNOOP, X86_SYNTH(20)) /* SELFSNOOP gets used by= Xen itself */ +XEN_CPUFEATURE(SC_MSR_IDLE, X86_SYNTH(21)) /* (SC_MSR_PV || SC_MSR_H= VM) && default_xen_spec_ctrl */ +XEN_CPUFEATURE(XEN_LBR, X86_SYNTH(22)) /* Xen uses MSR_DEBUGCTL.= LBR */ +XEN_CPUFEATURE(SC_VERW_PV, X86_SYNTH(23)) /* VERW used by Xen for P= V */ +XEN_CPUFEATURE(SC_VERW_HVM, X86_SYNTH(24)) /* VERW used by Xen for H= VM */ +XEN_CPUFEATURE(SC_VERW_IDLE, X86_SYNTH(25)) /* VERW used by Xen for i= dle */ + +/* Bug words follow the synthetic words. */ +#define X86_NR_BUG 1 +#define X86_BUG(x) ((FSCAPINTS + X86_NR_SYNTH) * 32 + (x)) + +/* Total number of capability words, inc synth and bug words. */ +#define NCAPINTS (FSCAPINTS + X86_NR_SYNTH + X86_NR_BUG) /* N 32-bit words= worth of info */ --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Tue May 7 05:55:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; 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Ag6ydAjPr6TkZPbJnqXPQ1ln97qAxKttPfAEF3froGw6lvH29h3XRX6CiBzwZQiQaYWI7QidpV fzSQdRGpvCglgPlYmMCr7ulzOYJ4zmpTLs5ZRCM1GcUoJhOB2WXv3BBEYGYp1ebiNxbunZG4Aw boBo3TQwc1HpQztRtS1WIrZH5ZhU3a9bDCukNwECQUqlIRhKqVIuclEtailFRJYqAPaUTxoRXb 10db1Khi5toYXC8BBP17/3BxUTzJS/VRE70C1Kyme1UTUkyD71b21n6l1I7WHSS5XpOwyYbebS HO0= X-SBRS: 2.7 X-MesageID: 4484232 X-Ironport-Server: esa1.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,405,1559534400"; d="scan'208";a="4484232" From: Andrew Cooper To: Xen-devel Date: Mon, 19 Aug 2019 19:26:12 +0100 Message-ID: <20190819182612.16706-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190819182612.16706-1-andrew.cooper3@citrix.com> References: <20190819182612.16706-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/2] x86/AMD: Fix handling of x87 exception pointers on Fam17h hardware X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) AMD Pre-Fam17h CPUs "optimise" {F,}X{SAVE,RSTOR} by not saving/restoring FOP/FIP/FDP if an x87 exception isn't pending. This causes an information leak, CVE-2006-1056, and worked around by several OSes, including Xen. AMD Fam17h CPUs no longer have this leak, and advertise so in a CPUID bit. Introduce the RSTR_FP_ERR_PTRS feature, as specified by AMD, and expose to = all guests by default. While adjusting libxl's cpuid table, add CLZERO which looks to have been omitted previously. Also introduce an X86_BUG bit to trigger the (F)XRSTOR workaround, and set = it on AMD hardware where RSTR_FP_ERR_PTRS is not advertised. Optimise the workaround path by dropping the data-dependent unpredictable conditions whi= ch will evalute to true for all 64bit OSes and most 32bit ones. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 v2: * Use the AMD naming, not that I am convinced this is a sensible name to u= se. * Adjust the i387 codepaths as well as the xstate ones. * Add xen-cpuid/libxl data for the CPUID bit. --- tools/libxl/libxl_cpuid.c | 3 +++ tools/misc/xen-cpuid.c | 1 + xen/arch/x86/cpu/amd.c | 7 +++++++ xen/arch/x86/i387.c | 14 +++++--------- xen/arch/x86/xstate.c | 6 ++---- xen/include/asm-x86/cpufeature.h | 3 +++ xen/include/asm-x86/cpufeatures.h | 2 ++ xen/include/public/arch-x86/cpufeatureset.h | 1 + 8 files changed, 24 insertions(+), 13 deletions(-) diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index a8d07fac50..acc92fd46c 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -256,7 +256,10 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *= cpuid, const char* str) =20 {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1}, =20 + {"clzero", 0x80000008, NA, CPUID_REG_EBX, 0, 1}, + {"rstr-fp-err-ptrs", 0x80000008, NA, CPUID_REG_EBX, 2, 1}, {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, + {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4}, =20 diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index b0db0525a9..04cdd9aa95 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -145,6 +145,7 @@ static const char *const str_e7d[32] =3D static const char *const str_e8b[32] =3D { [ 0] =3D "clzero", + [ 2] =3D "rstr-fp-err-ptrs", =20 [12] =3D "ibpb", }; diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index a2f83c79a5..463f9776c7 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -580,6 +580,13 @@ static void init_amd(struct cpuinfo_x86 *c) } =20 /* + * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception + * is pending. Xen works around this at (F)XRSTOR time. + */ + if ( !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS) ) + setup_force_cpu_cap(X86_BUG_FPU_PTR_LEAK); + + /* * Attempt to set lfence to be Dispatch Serialising. This MSR almost * certainly isn't virtualised (and Xen at least will leak the real * value in but silently discard writes), as well as being per-core diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 88178485cb..82dbc461c3 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -43,20 +43,17 @@ static inline void fpu_fxrstor(struct vcpu *v) const typeof(v->arch.xsave_area->fpu_sse) *fpu_ctxt =3D v->arch.fpu_ct= xt; =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception * is pending. Clear the x87 state here by setting it to fixed * values. The hypervisor data segment can be sometimes 0 and * sometimes new user value. Both should be ok. Use the FPU saved * data block as a safe address because it should be in L1. */ - if ( !(fpu_ctxt->fsw & ~fpu_ctxt->fcw & 0x003f) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) - { + if ( cpu_bug_fpu_ptr_leak ) asm volatile ( "fnclex\n\t" "ffree %%st(7)\n\t" /* clear stack tag */ "fildl %0" /* load to clear state */ : : "m" (*fpu_ctxt) ); - } =20 /* * FXRSTOR can fault if passed a corrupted data block. We handle this @@ -169,11 +166,10 @@ static inline void fpu_fxsave(struct vcpu *v) : "=3Dm" (*fpu_ctxt) : "R" (fpu_ctxt) ); =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception - * is pending. + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception is + * pending. The restore code fills in suitable defaults. */ - if ( !(fpu_ctxt->fsw & 0x0080) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( cpu_bug_fpu_ptr_leak && !(fpu_ctxt->fsw & 0x0080) ) return; =20 /* diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 3293ef834f..fd3c0c5a36 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -369,15 +369,13 @@ void xrstor(struct vcpu *v, uint64_t mask) unsigned int faults, prev_faults; =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception * is pending. Clear the x87 state here by setting it to fixed * values. The hypervisor data segment can be sometimes 0 and * sometimes new user value. Both should be ok. Use the FPU saved * data block as a safe address because it should be in L1. */ - if ( (mask & ptr->xsave_hdr.xstate_bv & X86_XCR0_FP) && - !(ptr->fpu_sse.fsw & ~ptr->fpu_sse.fcw & 0x003f) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( cpu_bug_fpu_ptr_leak ) asm volatile ( "fnclex\n\t" /* clear exceptions */ "ffree %%st(7)\n\t" /* clear stack tag */ "fildl %0" /* load to clear state */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index 906dd59c4b..5d7b819314 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -136,6 +136,9 @@ =20 #define cpu_has_msr_tsc_aux (cpu_has_rdtscp || cpu_has_rdpid) =20 +/* Bugs. */ +#define cpu_bug_fpu_ptr_leak boot_cpu_has(X86_BUG_FPU_PTR_LEAK) + enum _cache_type { CACHE_TYPE_NULL =3D 0, CACHE_TYPE_DATA =3D 1, diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufea= tures.h index ab3650f73b..afb861f588 100644 --- a/xen/include/asm-x86/cpufeatures.h +++ b/xen/include/asm-x86/cpufeatures.h @@ -43,5 +43,7 @@ XEN_CPUFEATURE(SC_VERW_IDLE, X86_SYNTH(25)) /* VERW = used by Xen for idle */ #define X86_NR_BUG 1 #define X86_BUG(x) ((FSCAPINTS + X86_NR_SYNTH) * 32 + (x)) =20 +#define X86_BUG_FPU_PTR_LEAK X86_BUG( 0) /* (F)XRSTOR doesn't load FO= P/FIP/FDP. */ + /* Total number of capability words, inc synth and bug words. */ #define NCAPINTS (FSCAPINTS + X86_NR_SYNTH + X86_NR_BUG) /* N 32-bit words= worth of info */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index e2c82a4554..babaf4b375 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -243,6 +243,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF= Read Only interface */ =20 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always sav= es/restores FPU Error pointers. */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, us= ed by AMD) */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Tue May 7 05:55:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: oC3ACnvQxj9MpdBlFDf+kR9DfCICksYk88pYJpgzU8aldyMw21VUq04Z+j42GZVQVOvox7Kzu9 bjqutr3CD8S5GpLQJoRJP83gl0NmbE+ugEL5vhgztDie11IOZ7KVdLFTXfSgVmEK32j8Iu7nuk 6/vhQh5KDU2O1h8D2P8nP13uvHkkH/aNFH9j95VT73aMdl511a1NxGlP5q560m3RG9uJ/7QLcW 5VSVrzTkYeuKRw8dvD7axlygLQuEI+2GwStkYJDfEFoaR6w+/RfUeKEnWUxgFr93jEoyMWNAjU 0LI= X-SBRS: 2.7 X-MesageID: 5321569 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,467,1559534400"; d="scan'208";a="5321569" From: Andrew Cooper To: Xen-devel Date: Wed, 4 Sep 2019 18:57:08 +0100 Message-ID: <20190904175708.18853-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190819182612.16706-1-andrew.cooper3@citrix.com> References: <20190819182612.16706-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3 2/2] x86/AMD: Fix handling of x87 exception pointers on Fam17h hardware X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) AMD Pre-Fam17h CPUs "optimise" {F,}X{SAVE,RSTOR} by not saving/restoring FOP/FIP/FDP if an x87 exception isn't pending. This causes an information leak, CVE-2006-1056, and worked around by several OSes, including Xen. AMD Fam17h CPUs no longer have this leak, and advertise so in a CPUID bit. Introduce the RSTR_FP_ERR_PTRS feature, as specified by AMD, and expose to = all guests by default. While adjusting libxl's cpuid table, add CLZERO which looks to have been omitted previously. Also introduce an X86_BUG bit to trigger the (F)XRSTOR workaround, and set = it on AMD hardware where RSTR_FP_ERR_PTRS is not advertised. Optimise the conditions for the workaround paths. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 v3: * Rename to X86_BUG_FPU_PTRS * Reinstate, contrary to personal opinion, the fsw/fcw checks. v2: * Use the AMD naming, not that I am convinced this is a sensible name to u= se. * Adjust the i387 codepaths as well as the xstate ones. * Add xen-cpuid/libxl data for the CPUID bit. --- tools/libxl/libxl_cpuid.c | 3 +++ tools/misc/xen-cpuid.c | 1 + xen/arch/x86/cpu/amd.c | 7 +++++++ xen/arch/x86/i387.c | 16 +++++++--------- xen/arch/x86/xstate.c | 7 +++---- xen/include/asm-x86/cpufeature.h | 3 +++ xen/include/asm-x86/cpufeatures.h | 2 ++ xen/include/public/arch-x86/cpufeatureset.h | 1 + 8 files changed, 27 insertions(+), 13 deletions(-) diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index f1c6ce2076..953a3bbd8c 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -257,8 +257,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *= cpuid, const char* str) =20 {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1}, =20 + {"clzero", 0x80000008, NA, CPUID_REG_EBX, 0, 1}, + {"rstr-fp-err-ptrs", 0x80000008, NA, CPUID_REG_EBX, 2, 1}, {"wbnoinvd", 0x80000008, NA, CPUID_REG_EBX, 9, 1}, {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, + {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4}, =20 diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index be6a8d27a5..f51facffb6 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -145,6 +145,7 @@ static const char *const str_e7d[32] =3D static const char *const str_e8b[32] =3D { [ 0] =3D "clzero", + [ 2] =3D "rstr-fp-err-ptrs", =20 /* [ 8] */ [ 9] =3D "wbnoinvd", =20 diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index a2f83c79a5..dc9ed55ba6 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -580,6 +580,13 @@ static void init_amd(struct cpuinfo_x86 *c) } =20 /* + * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception + * is pending. Xen works around this at (F)XRSTOR time. + */ + if ( !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS) ) + setup_force_cpu_cap(X86_BUG_FPU_PTRS); + + /* * Attempt to set lfence to be Dispatch Serialising. This MSR almost * certainly isn't virtualised (and Xen at least will leak the real * value in but silently discard writes), as well as being per-core diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 88178485cb..e4f0965eed 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -43,20 +43,18 @@ static inline void fpu_fxrstor(struct vcpu *v) const typeof(v->arch.xsave_area->fpu_sse) *fpu_ctxt =3D v->arch.fpu_ct= xt; =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception * is pending. Clear the x87 state here by setting it to fixed * values. The hypervisor data segment can be sometimes 0 and * sometimes new user value. Both should be ok. Use the FPU saved * data block as a safe address because it should be in L1. */ - if ( !(fpu_ctxt->fsw & ~fpu_ctxt->fcw & 0x003f) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) - { + if ( cpu_bug_fpu_ptrs && + !(fpu_ctxt->fsw & ~fpu_ctxt->fcw & 0x003f) ) asm volatile ( "fnclex\n\t" "ffree %%st(7)\n\t" /* clear stack tag */ "fildl %0" /* load to clear state */ : : "m" (*fpu_ctxt) ); - } =20 /* * FXRSTOR can fault if passed a corrupted data block. We handle this @@ -169,11 +167,11 @@ static inline void fpu_fxsave(struct vcpu *v) : "=3Dm" (*fpu_ctxt) : "R" (fpu_ctxt) ); =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception - * is pending. + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception is + * pending. In this case, the restore side will arrange safe valu= es, + * and there is no point trying to restore FCS/FDS in addition. */ - if ( !(fpu_ctxt->fsw & 0x0080) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( cpu_bug_fpu_ptrs && !(fpu_ctxt->fsw & 0x0080) ) return; =20 /* diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 3293ef834f..10016a05d0 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -369,15 +369,14 @@ void xrstor(struct vcpu *v, uint64_t mask) unsigned int faults, prev_faults; =20 /* - * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception + * Some CPUs don't save/restore FDP/FIP/FOP unless an exception * is pending. Clear the x87 state here by setting it to fixed * values. The hypervisor data segment can be sometimes 0 and * sometimes new user value. Both should be ok. Use the FPU saved * data block as a safe address because it should be in L1. */ - if ( (mask & ptr->xsave_hdr.xstate_bv & X86_XCR0_FP) && - !(ptr->fpu_sse.fsw & ~ptr->fpu_sse.fcw & 0x003f) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( cpu_bug_fpu_ptrs && + !(ptr->fpu_sse.fsw & ~ptr->fpu_sse.fcw & 0x003f) ) asm volatile ( "fnclex\n\t" /* clear exceptions */ "ffree %%st(7)\n\t" /* clear stack tag */ "fildl %0" /* load to clear state */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index 7e1ff17ad4..00d22caac7 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -138,6 +138,9 @@ =20 #define cpu_has_msr_tsc_aux (cpu_has_rdtscp || cpu_has_rdpid) =20 +/* Bugs. */ +#define cpu_bug_fpu_ptrs boot_cpu_has(X86_BUG_FPU_PTRS) + enum _cache_type { CACHE_TYPE_NULL =3D 0, CACHE_TYPE_DATA =3D 1, diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufea= tures.h index ab3650f73b..91eccf5161 100644 --- a/xen/include/asm-x86/cpufeatures.h +++ b/xen/include/asm-x86/cpufeatures.h @@ -43,5 +43,7 @@ XEN_CPUFEATURE(SC_VERW_IDLE, X86_SYNTH(25)) /* VERW = used by Xen for idle */ #define X86_NR_BUG 1 #define X86_BUG(x) ((FSCAPINTS + X86_NR_SYNTH) * 32 + (x)) =20 +#define X86_BUG_FPU_PTRS X86_BUG( 0) /* (F)X{SAVE,RSTOR} doesn't = save/restore FOP/FIP/FDP. */ + /* Total number of capability words, inc synth and bug words. */ #define NCAPINTS (FSCAPINTS + X86_NR_SYNTH + X86_NR_BUG) /* N 32-bit words= worth of info */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index f2ec470179..48d8d1f4e2 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -244,6 +244,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF= Read Only interface */ =20 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always sav= es/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, us= ed by AMD) */ =20 --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel