From nobody Tue Feb 10 15:45:50 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1565631098; cv=none; d=zoho.com; s=zohoarc; b=D7W8HEhpNNHKQmysghCenOeHr1mCTW8ezL9JjeOTsbck6DPP/txZParaPioZT8RS4sJJprG3i+4VpmfZZ/62D2VpYwOqtnjbSbDQf/NQcBPTszEylBs69sVUebE6O2Sw2lJmr+1ZNdwRUo/a6N7gAe2FcaNqkXWuDZqKlvmC8/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565631098; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GAqhDTTnX88Fu6DP3MqRSeCdELS4Himqqxj8V/SycJE=; b=AQJQXZO5d1PkYyG7vsC/CoVk9XYF9zbi0g3q9Lhi+nyLdMMF0RzvWSXRuC3oeFdVs5CsIiUu+AG8VH1F2GY08+FSevuzzL+uLl6GoaaXkIXP0wvqPCs/BnwhEPC4vdR8L8hS9NpqePdTlRu7AaaeW+hASSwNB6VPdsoLZuV5KvQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 156563109886099.48367990308395; Mon, 12 Aug 2019 10:31:38 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9Z-0006mC-MO; Mon, 12 Aug 2019 17:30:41 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9Y-0006kA-5h for xen-devel@lists.xenproject.org; Mon, 12 Aug 2019 17:30:40 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e6f4937b-bd26-11e9-8980-bc764e045a96; Mon, 12 Aug 2019 17:30:39 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 144D115AB; Mon, 12 Aug 2019 10:30:39 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 62A153F706; Mon, 12 Aug 2019 10:30:38 -0700 (PDT) X-Inumbo-ID: e6f4937b-bd26-11e9-8980-bc764e045a96 From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:30:04 +0100 Message-Id: <20190812173019.11956-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 13/28] xen/arm32: head: Introduce distinct paths for the boot CPU and secondary CPUs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The boot code is currently quite difficult to go through because of the lack of documentation and a number of indirection to avoid executing some path in either the boot CPU or secondary CPUs. In an attempt to make the boot code easier to follow, each parts of the boot are now in separate functions. Furthermore, the paths for the boot CPU and secondary CPUs are now distinct and for now will call each functions. Follow-ups will remove unnecessary calls and do further improvement (such as adding documentation and reshuffling). Note that the switch from using the ID mapping to the runtime mapping is duplicated for each path. This is because in the future we will need to stay longer in the ID mapping for the boot CPU. Lastly, it is now required to save lr in cpu_init() becauswe the function will call other functions and therefore clobber lr. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Remove hard tab - s/ID map/1:1 mapping/ Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 65 +++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index c4ee06ba93..4285f76463 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -148,7 +148,19 @@ past_zImage: =20 mov r12, #0 /* r12 :=3D is_secondary_cpu */ =20 - b common_start + bl check_cpu_mode + bl zero_bss + bl cpu_init + bl create_page_tables + bl enable_mmu + + /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ + ldr r0, =3Dprimary_switched + mov pc, r0 +primary_switched: + bl setup_fixmap + b launch +ENDPROC(start) =20 GLOBAL(init_secondary) cpsid aif /* Disable all interrupts */ @@ -179,8 +191,22 @@ GLOBAL(init_secondary) print_reg r7 PRINT(" booting -\r\n") #endif - -common_start: + bl check_cpu_mode + bl zero_bss + bl cpu_init + bl create_page_tables + bl enable_mmu + + + /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ + ldr r0, =3Dsecondary_switched + mov pc, r0 +secondary_switched: + bl setup_fixmap + b launch +ENDPROC(init_secondary) + +check_cpu_mode: /* Check that this CPU has Hyp mode */ mrc CP32(r0, ID_PFR1) and r0, r0, #0xf000 /* Bits 12-15 define virt extensions = */ @@ -202,7 +228,10 @@ common_start: b fail =20 hyp: PRINT("- Xen starting in Hyp mode -\r\n") + mov pc, lr +ENDPROC(check_cpu_mode) =20 +zero_bss: /* Zero BSS On the boot CPU to avoid nasty surprises */ teq r12, #0 bne skip_bss @@ -219,8 +248,14 @@ hyp: PRINT("- Xen starting in Hyp mode -\r\n") blo 1b =20 skip_bss: + mov pc, lr +ENDPROC(zero_bss) + +cpu_init: PRINT("- Setting up control registers -\r\n") =20 + mov r5, lr /* r5 :=3D return address */ + /* Get processor specific proc info into r1 */ bl __lookup_processor_type teq r1, #0 @@ -231,7 +266,6 @@ skip_bss: PRINT(" -\r\n") b fail 1: - /* Jump to cpu_init */ ldr r1, [r1, #PROCINFO_cpu_init] /* r1 :=3D vaddr(init func) */ adr lr, cpu_init_done /* Save return address */ @@ -256,6 +290,10 @@ cpu_init_done: ldr r0, =3DHSCTLR_SET mcr CP32(r0, HSCTLR) =20 + mov pc, r5 /* Return address is in r5 */ +ENDPROC(cpu_init) + +create_page_tables: /* * Rebuild the boot pagetable's first-level entries. The structure * is described in mm.c. @@ -359,15 +397,16 @@ cpu_init_done: /* boot pagetable setup complete */ =20 cmp r6, #1 /* Did we manage to create an identity= mapping ? */ - beq 1f + moveq pc, lr PRINT("Unable to build boot page tables - Failed to identity map X= en.\r\n") b fail virtphys_clash: /* Identity map clashes with boot_third, which we cannot handle ye= t */ PRINT("- Unable to build boot page tables - virt and phys addresse= s clash. -\r\n") b fail +ENDPROC(create_page_tables) =20 -1: +enable_mmu: PRINT("- Turning on paging -\r\n") =20 /* @@ -377,16 +416,16 @@ virtphys_clash: mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ dsb nsh =20 - ldr r1, =3Dpaging /* Explicit vaddr, not RIP-relative= */ mrc CP32(r0, HSCTLR) /* Enable MMU and D-cache */ orr r0, r0, #(SCTLR_Axx_ELx_M|SCTLR_Axx_ELx_C) dsb /* Flush PTE writes and finish reads = */ mcr CP32(r0, HSCTLR) /* now paging is enabled */ isb /* Now, flush the icache */ - mov pc, r1 /* Get a proper vaddr into PC */ -paging: + mov pc, lr +ENDPROC(enable_mmu) =20 +setup_fixmap: /* * Now we can install the fixmap and dtb mappings, since we * don't need the 1:1 map any more @@ -436,12 +475,15 @@ paging: mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ dsb /* Ensure completion of TLB flush */ isb + mov pc, lr +ENDPROC(setup_fixmap) =20 +launch: PRINT("- Ready -\r\n") =20 /* The boot CPU should go straight into C now */ teq r12, #0 - beq launch + beq 1f =20 /* * Non-boot CPUs need to move on to the proper pagetables, which w= ere @@ -460,7 +502,7 @@ paging: dsb /* Ensure completion of TLB+BP flush = */ isb =20 -launch: +1: ldr r0, =3Dinit_data add r0, #INITINFO_stack /* Find the boot-time stack */ ldr sp, [r0] @@ -471,6 +513,7 @@ launch: moveq r1, r8 /* - DTB address */ beq start_xen /* and disappear into the land of C */ b start_secondary /* (to the appropriate entry point) */ +ENDPROC(launch) =20 /* Fail-stop */ fail: PRINT("- Boot failed -\r\n") --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel