From nobody Sat May 4 23:19:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1564422006; cv=none; d=zoho.com; s=zohoarc; b=R+JRADKMeqJbeYki7erAc+hyuE5q2TnXx+138ioH3MVWcb5SygE3bhyM/zYGoUlwUeg6S7LyYcWed/pJsH2y79R4rG9kiZrJmuMdzH8dGBOIHsmX4Jnbs+mjJtgxopKUOjnAs9fb8ZkXdmhcbGe1vY7t+VeIVS9GMSIjoT5wE38= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564422006; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GcAHyE/Z4mEUGAZjojlodUbVIuCRr8SjLsAPqNyC3WA=; b=P+1RhII4KA2m2JSRKMG0TZ1ZVvTN645rzkmIM/lqwC/cdW5OhqxSuxIVPjt0cXULJ2N12w6Mrwfff2QEUQEZq6hAgdfgBPNUxEp02R3ci22IlU9C/IjXLEc4HK1H/ACD7XYG5wVX8h3cZDcveG1RG/5l4OFcEBCxF2DIbEeEdVY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 156442200647885.84721547282959; Mon, 29 Jul 2019 10:40:06 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hs9bp-0005q8-6N; Mon, 29 Jul 2019 17:38:53 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hs9bn-0005px-O0 for xen-devel@lists.xenproject.org; Mon, 29 Jul 2019 17:38:51 +0000 Received: from esa4.hc3370-68.iphmx.com (unknown [216.71.155.144]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id b881cb08-b227-11e9-98ba-7304cec94108; Mon, 29 Jul 2019 17:38:48 +0000 (UTC) X-Inumbo-ID: b881cb08-b227-11e9-98ba-7304cec94108 Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=andrew.cooper3@citrix.com; spf=Pass smtp.mailfrom=Andrew.Cooper3@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: None (esa4.hc3370-68.iphmx.com: no sender authenticity information available from domain of andrew.cooper3@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="andrew.cooper3@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa4.hc3370-68.iphmx.com: domain of Andrew.Cooper3@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="Andrew.Cooper3@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ~all" Received-SPF: None (esa4.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: BFYegNC79QyB5Cbm8C5L1TwasP5ujm3DKklJwdsGvV9xdRrpL4mi/bHPZXsByB9k5dBTWXuzLH M64gNa1Veaes+XBMiZ1zyXAfvE7nXaRRzfxP6E/dBoqn3XRA6QNfULgqq0DCZ0qwX5PwzXeiZh aiBCvrG+yUU1PluVA1J/dw6YC2lXXtWbkSNwp2YrgPgVaLqMVye9/jrXz5ZDO4pKU4yQsB5sJo s4rDVr7PhE4YmHOAzgKb2BEmAWVo6yV9gZgn5KB62AU4W2hgxJFmdQhK1dn7167p7VZlrOCc3m Z7w= X-SBRS: 2.7 X-MesageID: 3716348 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,323,1559534400"; d="scan'208";a="3716348" From: Andrew Cooper To: Xen-devel Date: Mon, 29 Jul 2019 18:38:42 +0100 Message-ID: <20190729173843.21586-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190729173843.21586-1-andrew.cooper3@citrix.com> References: <20190729173843.21586-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3 1/2] xen/link: Introduce .bss.percpu.page_aligned X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Wei Liu , Andrew Cooper , Julien Grall , Jan Beulich , Volodymyr Babchuk , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Future changes are going to need to page align some percpu data. Shuffle the exact link order of items within the BSS to give .bss.percpu.page_aligned appropriate alignment, even on CPU0, which uses .bss.percpu itself. Insert explicit alignment such that the result is safe even with objects shorter than a page in length. The POINTER_ALIGN for __bss_end is to cover the lack of SMP_CACHE_BYTES alignment, as the loops which zero the BSS use pointer-sized stores on all architectures. In addition, we need to be able to specify an alignment attribute to __DEFINE_PER_CPU(). Rework it so the caller passes in all attributes, and adjust DEFINE_PER_CPU{,_READ_MOSTLY}() to match. This has the added bonus that it is now possible to grep for .bss.percpu and find all the users. Finally, introduce DEFINE_PER_CPU_PAGE_ALIGNED() which uses both section and alignment attributes. Signed-off-by: Andrew Cooper Acked-by: Julien Grall --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk A sample build including the subsequent patch is now: ffff82d08092d000 B zero_page ffff82d08092e000 B per_cpu__init_tss ffff82d08092e000 B __per_cpu_start ffff82d08092f000 B per_cpu__cpupool ffff82d08092f008 b per_cpu__continue_info ffff82d08092f010 b per_cpu__grant_rwlock which demonstrates the correct alignment of data in .bss.percpu even when following a non-page-sized object in .bss.percpu.page_aligned. v3: * Insert explicit alignment. * Reduce __bss_end's alignment to just POINTER_ALIGN. v2: * Rework __DEFINE_PER_CPU() to allow for further attributes to be passed. * Specify __aligned(PAGE_SIZE) as part of DEFINE_PER_CPU_PAGE_ALIGNED(). --- xen/arch/arm/xen.lds.S | 7 +++++-- xen/arch/x86/xen.lds.S | 7 +++++-- xen/include/asm-arm/percpu.h | 6 ++---- xen/include/asm-x86/percpu.h | 6 ++---- xen/include/xen/percpu.h | 10 ++++++++-- 5 files changed, 22 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index 12c107f45d..cc27131d5e 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -201,14 +201,17 @@ SECTIONS *(.bss.stack_aligned) . =3D ALIGN(PAGE_SIZE); *(.bss.page_aligned) - *(.bss) - . =3D ALIGN(SMP_CACHE_BYTES); + . =3D ALIGN(PAGE_SIZE); __per_cpu_start =3D .; + *(.bss.percpu.page_aligned) + . =3D ALIGN(PAGE_SIZE); *(.bss.percpu) . =3D ALIGN(SMP_CACHE_BYTES); *(.bss.percpu.read_mostly) . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_data_end =3D .; + *(.bss) + . =3D ALIGN(POINTER_ALIGN); __bss_end =3D .; } :text _end =3D . ; diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index a73139cd29..3bf21975a2 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -293,14 +293,17 @@ SECTIONS __bss_start =3D .; *(.bss.stack_aligned) *(.bss.page_aligned*) - *(.bss) - . =3D ALIGN(SMP_CACHE_BYTES); + . =3D ALIGN(PAGE_SIZE); __per_cpu_start =3D .; + *(.bss.percpu.page_aligned) + . =3D ALIGN(PAGE_SIZE); *(.bss.percpu) . =3D ALIGN(SMP_CACHE_BYTES); *(.bss.percpu.read_mostly) . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_data_end =3D .; + *(.bss) + . =3D ALIGN(POINTER_ALIGN); __bss_end =3D .; } :text _end =3D . ; diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index 9584b830d4..264120b192 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -10,10 +10,8 @@ extern char __per_cpu_start[], __per_cpu_data_end[]; extern unsigned long __per_cpu_offset[NR_CPUS]; void percpu_init_areas(void); =20 -/* Separate out the type, so (int[3], foo) works. */ -#define __DEFINE_PER_CPU(type, name, suffix) \ - __section(".bss.percpu" #suffix) \ - __typeof__(type) per_cpu_##name +#define __DEFINE_PER_CPU(attr, type, name) \ + attr __typeof__(type) per_cpu_ ## name =20 #define per_cpu(var, cpu) \ (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset[cpu])) diff --git a/xen/include/asm-x86/percpu.h b/xen/include/asm-x86/percpu.h index ff34dc7897..5b6cef04c4 100644 --- a/xen/include/asm-x86/percpu.h +++ b/xen/include/asm-x86/percpu.h @@ -7,10 +7,8 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; void percpu_init_areas(void); #endif =20 -/* Separate out the type, so (int[3], foo) works. */ -#define __DEFINE_PER_CPU(type, name, suffix) \ - __section(".bss.percpu" #suffix) \ - __typeof__(type) per_cpu_##name +#define __DEFINE_PER_CPU(attr, type, name) \ + attr __typeof__(type) per_cpu_ ## name =20 /* var is in discarded region: offset to particular copy we want */ #define per_cpu(var, cpu) \ diff --git a/xen/include/xen/percpu.h b/xen/include/xen/percpu.h index aeec5c19d6..71a31cc361 100644 --- a/xen/include/xen/percpu.h +++ b/xen/include/xen/percpu.h @@ -9,9 +9,15 @@ * The _##name concatenation is being used here to prevent 'name' from get= ting * macro expanded, while still allowing a per-architecture symbol name pre= fix. */ -#define DEFINE_PER_CPU(type, name) __DEFINE_PER_CPU(type, _##name, ) +#define DEFINE_PER_CPU(type, name) \ + __DEFINE_PER_CPU(__section(".bss.percpu"), type, _ ## name) + +#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \ + __DEFINE_PER_CPU(__section(".bss.percpu.page_aligned") \ + __aligned(PAGE_SIZE), type, _ ## name) + #define DEFINE_PER_CPU_READ_MOSTLY(type, name) \ - __DEFINE_PER_CPU(type, _##name, .read_mostly) + __DEFINE_PER_CPU(__section(".bss.percpu.read_mostly"), type, _ ## name) =20 #define get_per_cpu_var(var) (per_cpu__##var) =20 --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sat May 4 23:19:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1564422006; cv=none; d=zoho.com; s=zohoarc; b=ccYDWziGO/kNPxI99CR8eQ6jUNHydfRhIbP8u/mVHVvCmQXbtj1z5LN31NPGy6FsULGLzKybmeqBV3t2tIAJ1GX/Cwa+aOh+LMqPNukwTCgtR3CB2qFQEIvVy8FZ57krb7wuEoDeCFrzGc7hZZuaAXlNSbxqgi26T6rqdbJ6zd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564422006; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=puRDHCMdQH/OYGctgfEhCIApPS+THtzCIfxk2DNKZjI=; b=c4jQuvJB9eO402pmhG9DCghIkM83Wvo+vtrnx17Z9CtHIcRIiwxV50RYXIlgC6m6Fzf6PBVgn3zrb6yejj0Bt+eMrl3s+SSNE+oXRh1qSF/89dVZKr1CegijXt+gh9LyPvuxhJQsshcyD+ZLn0J0MkfQkX6a11Z5vL+UZpo60I4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1564422006549421.83305062140687; Mon, 29 Jul 2019 10:40:06 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hs9bl-0005pq-U2; Mon, 29 Jul 2019 17:38:49 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hs9bk-0005pd-Um for xen-devel@lists.xenproject.org; Mon, 29 Jul 2019 17:38:48 +0000 Received: from esa4.hc3370-68.iphmx.com (unknown [216.71.155.144]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id b8756226-b227-11e9-8980-bc764e045a96; Mon, 29 Jul 2019 17:38:48 +0000 (UTC) X-Inumbo-ID: b8756226-b227-11e9-8980-bc764e045a96 Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=andrew.cooper3@citrix.com; spf=Pass smtp.mailfrom=Andrew.Cooper3@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: None (esa4.hc3370-68.iphmx.com: no sender authenticity information available from domain of andrew.cooper3@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="andrew.cooper3@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa4.hc3370-68.iphmx.com: domain of Andrew.Cooper3@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="Andrew.Cooper3@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ~all" Received-SPF: None (esa4.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa4.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: SBEQXRPqaaF2q6SJRLvi0kSRI+nVITMi6P8bipKP/cNpEwwCsr/ZX/rWOAapw8btZFBB4JsWwQ Xu0/nWB/Z4hiOGq2aKpLLGCnKMMCWjkQGn+4QEsWA3FuUheLUtRpWc6+U+X02SLMvalXm2AETe g+R/tmzt6DWIYf3XC2qbDApkonf71PQOgDk6VCcB+RGzaQc3zxEDyKKOd2ZT0+3poY1irR6GrZ 52xo3L+c/znJSBBP21elJKvIpVdkjD+kyIEpBBzUsMSEyf5sYYsXtanr0gjlC7CHMhl/+7Hrpw LsI= X-SBRS: 2.7 X-MesageID: 3716346 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,323,1559534400"; d="scan'208";a="3716346" From: Andrew Cooper To: Xen-devel Date: Mon, 29 Jul 2019 18:38:43 +0100 Message-ID: <20190729173843.21586-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190729173843.21586-1-andrew.cooper3@citrix.com> References: <20190729173843.21586-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3 2/2] x86/xpti: Don't leak TSS-adjacent percpu data via Meltdown X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The XPTI work restricted the visibility of most of memory, but missed a few aspects when it came to the TSS. Given that the TSS is just an object in percpu data, the 4k mapping for it created in setup_cpu_root_pgt() maps adjacent percpu data, making it all leakable via Meltdown, even when XPTI is in use. Furthermore, no care is taken to check that the TSS doesn't cross a page boundary. As it turns out, struct tss_struct is aligned on its size which does prevent it straddling a page boundary. Move the TSS into the page aligned percpu area, so no adjacent data can be leaked. Move the definition from setup.c to traps.c, which is a more appropriate place for it to live. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 v3: * Drop the remark about CET. It is no longer accurate in the latest versi= on of the CET spec. v2: * Rebase over changes to include __aligned() within DEFINE_PER_CPU_PAGE_ALIGNED() * Drop now-unused xen/percpu.h from setup.c --- xen/arch/x86/setup.c | 3 --- xen/arch/x86/traps.c | 6 ++++++ xen/arch/x86/xen.lds.S | 2 ++ xen/include/asm-x86/processor.h | 4 ++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d2011910fa..f9d38155d3 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -100,8 +99,6 @@ unsigned long __read_mostly xen_phys_start; =20 unsigned long __read_mostly xen_virt_end; =20 -DEFINE_PER_CPU(struct tss_struct, init_tss); - char __section(".bss.stack_aligned") __aligned(STACK_SIZE) cpu0_stack[STACK_SIZE]; =20 diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 38d12013db..de3ac135f5 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -108,6 +108,12 @@ idt_entry_t __section(".bss.page_aligned") __aligned(P= AGE_SIZE) /* Pointer to the IDT of every CPU. */ idt_entry_t *idt_tables[NR_CPUS] __read_mostly; =20 +/* + * The TSS is smaller than a page, but we give it a full page to avoid + * adjacent per-cpu data leaking via Meltdown when XPTI is in use. + */ +DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, init_tss); + bool (*ioemul_handle_quirk)( u8 opcode, char *io_emul_stub, struct cpu_user_regs *regs); =20 diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index 3bf21975a2..2732f30be5 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -370,6 +370,8 @@ ASSERT(IS_ALIGNED(__2M_rwdata_end, SECTION_ALIGN), "_= _2M_rwdata_end misaligned =20 ASSERT(IS_ALIGNED(cpu0_stack, STACK_SIZE), "cpu0_stack misaligned") =20 +ASSERT(IS_ALIGNED(per_cpu__init_tss, PAGE_SIZE), "per_cpu(init_tss) misali= gned") + ASSERT(IS_ALIGNED(__init_begin, PAGE_SIZE), "__init_begin misaligned") ASSERT(IS_ALIGNED(__init_end, PAGE_SIZE), "__init_end misaligned") =20 diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 2862321eee..b5bee94931 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -411,7 +411,7 @@ static always_inline void __mwait(unsigned long eax, un= signed long ecx) #define IOBMP_BYTES 8192 #define IOBMP_INVALID_OFFSET 0x8000 =20 -struct __packed __cacheline_aligned tss_struct { +struct __packed tss_struct { uint32_t :32; uint64_t rsp0, rsp1, rsp2; uint64_t :64; @@ -425,6 +425,7 @@ struct __packed __cacheline_aligned tss_struct { /* Pads the TSS to be cacheline-aligned (total size is 0x80). */ uint8_t __cacheline_filler[24]; }; +DECLARE_PER_CPU(struct tss_struct, init_tss); =20 #define IST_NONE 0UL #define IST_DF 1UL @@ -463,7 +464,6 @@ static inline void disable_each_ist(idt_entry_t *idt) extern idt_entry_t idt_table[]; extern idt_entry_t *idt_tables[]; =20 -DECLARE_PER_CPU(struct tss_struct, init_tss); DECLARE_PER_CPU(root_pgentry_t *, root_pgt); =20 extern void write_ptbase(struct vcpu *v); --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel