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d="scan'208";a="3474414" From: Andrew Cooper To: Xen-devel Date: Fri, 26 Jul 2019 14:52:39 +0100 Message-ID: <20190726135240.21745-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190726135240.21745-1-andrew.cooper3@citrix.com> References: <20190726135240.21745-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] xen/link: Introduce .bss.percpu.page_aligned X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Wei Liu , Andrew Cooper , Julien Grall , Jan Beulich , Volodymyr Babchuk , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Future changes are going to need to page align some percpu data. This means that the percpu area needs suiably aligning in the BSS so CPU0 h= as correctly aligned data. Shuffle the exact link order of items within the B= SS to give .bss.percpu.page_aligned appropriate alignment. Additionally, introduce DEFINE_PER_CPU_PAGE_ALIGNED() Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk --- xen/arch/arm/xen.lds.S | 5 +++-- xen/arch/x86/xen.lds.S | 5 +++-- xen/include/xen/percpu.h | 2 ++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index 12c107f45d..07cbdf2543 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -201,14 +201,15 @@ SECTIONS *(.bss.stack_aligned) . =3D ALIGN(PAGE_SIZE); *(.bss.page_aligned) - *(.bss) - . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_start =3D .; + *(.bss.percpu.page_aligned) *(.bss.percpu) . =3D ALIGN(SMP_CACHE_BYTES); *(.bss.percpu.read_mostly) . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_data_end =3D .; + *(.bss) + . =3D ALIGN(SMP_CACHE_BYTES); __bss_end =3D .; } :text _end =3D . ; diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index a73139cd29..b8a2ea4259 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -293,14 +293,15 @@ SECTIONS __bss_start =3D .; *(.bss.stack_aligned) *(.bss.page_aligned*) - *(.bss) - . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_start =3D .; + *(.bss.percpu.page_aligned) *(.bss.percpu) . =3D ALIGN(SMP_CACHE_BYTES); *(.bss.percpu.read_mostly) . =3D ALIGN(SMP_CACHE_BYTES); __per_cpu_data_end =3D .; + *(.bss) + . =3D ALIGN(SMP_CACHE_BYTES); __bss_end =3D .; } :text _end =3D . ; diff --git a/xen/include/xen/percpu.h b/xen/include/xen/percpu.h index aeec5c19d6..c5291dc5e9 100644 --- a/xen/include/xen/percpu.h +++ b/xen/include/xen/percpu.h @@ -10,6 +10,8 @@ * macro expanded, while still allowing a per-architecture symbol name pre= fix. */ #define DEFINE_PER_CPU(type, name) __DEFINE_PER_CPU(type, _##name, ) +#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \ + __DEFINE_PER_CPU(type, _##name, .page_aligned) #define DEFINE_PER_CPU_READ_MOSTLY(type, name) \ __DEFINE_PER_CPU(type, _##name, .read_mostly) =20 --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 3 10:57:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of andrew.cooper3@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="andrew.cooper3@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa2.hc3370-68.iphmx.com: domain of Andrew.Cooper3@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="Andrew.Cooper3@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ~all" Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: iOSrn/nFcBTbU8HOf6X360lgT2BUMpict7o6WCYMW+9h11YmOjlWY9+M3Sa6/kBtwnoKt8j0Uk GokGiftqXeSzkp38KZe2tBssESb7kqmo0pF4tdjWg4533Fs8RxxymnrbeOd9ZAH9D3UoC03sk6 uh/j9tYuwce2hY7/MdlaLzOdQfkmJZMKL9uZBfRjakj2/iL+bA3BlWx+C1h9EKC0ogQJ6m7GGf 1qB57B3EREaUH6pcrCHj8Jfh+F0mypi07n9698pNHXTOFhMWe0L0vXuDSb1yRoE3yqgusviAHd 4eI= X-SBRS: 2.7 X-MesageID: 3474415 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.64,311,1559534400"; d="scan'208";a="3474415" From: Andrew Cooper To: Xen-devel Date: Fri, 26 Jul 2019 14:52:40 +0100 Message-ID: <20190726135240.21745-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190726135240.21745-1-andrew.cooper3@citrix.com> References: <20190726135240.21745-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/2] x86/xpti: Don't leak TSS-adjacent percpu data via Meltdown X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The XPTI work restricted the visibility of most of memory, but missed a few aspects when it came to the TSS. Given that the TSS is just an object in percpu data, the 4k mapping for it created in setup_cpu_root_pgt() maps adjacent percpu data, making it all leakable via Meltdown, even when XPTI is in use. Furthermore, no care is taken to check that the TSS doesn't cross a page boundary. As it turns out, struct tss_struct is aligned on its size which does prevent it straddling a page boundary, but this will cease to be true once CET and Shadow Stack support is added to Xen. Move the TSS into the page aligned percpu area, so no adjacent data can be leaked. Move the definition from setup.c to traps.c, which is a more appropriate place for it to live. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/setup.c | 2 -- xen/arch/x86/traps.c | 6 ++++++ xen/arch/x86/xen.lds.S | 2 ++ xen/include/asm-x86/processor.h | 4 ++-- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d2011910fa..1a2ffc4dc1 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -100,8 +100,6 @@ unsigned long __read_mostly xen_phys_start; =20 unsigned long __read_mostly xen_virt_end; =20 -DEFINE_PER_CPU(struct tss_struct, init_tss); - char __section(".bss.stack_aligned") __aligned(STACK_SIZE) cpu0_stack[STACK_SIZE]; =20 diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 38d12013db..e4b4587956 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -108,6 +108,12 @@ idt_entry_t __section(".bss.page_aligned") __aligned(P= AGE_SIZE) /* Pointer to the IDT of every CPU. */ idt_entry_t *idt_tables[NR_CPUS] __read_mostly; =20 +/* + * The TSS is smaller than a page, but we give it a full page to avoid + * adjacent per-cpu data leaking via Meltdown when XPTI is in use. + */ +DEFINE_PER_CPU_PAGE_ALIGNED(struct __aligned(PAGE_SIZE) tss_struct, init_t= ss); + bool (*ioemul_handle_quirk)( u8 opcode, char *io_emul_stub, struct cpu_user_regs *regs); =20 diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index b8a2ea4259..c82e1e504a 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -368,6 +368,8 @@ ASSERT(IS_ALIGNED(__2M_rwdata_end, SECTION_ALIGN), "_= _2M_rwdata_end misaligned =20 ASSERT(IS_ALIGNED(cpu0_stack, STACK_SIZE), "cpu0_stack misaligned") =20 +ASSERT(IS_ALIGNED(per_cpu__init_tss, PAGE_SIZE), "per_cpu(init_tss) misali= gned") + ASSERT(IS_ALIGNED(__init_begin, PAGE_SIZE), "__init_begin misaligned") ASSERT(IS_ALIGNED(__init_end, PAGE_SIZE), "__init_end misaligned") =20 diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 2862321eee..b5bee94931 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -411,7 +411,7 @@ static always_inline void __mwait(unsigned long eax, un= signed long ecx) #define IOBMP_BYTES 8192 #define IOBMP_INVALID_OFFSET 0x8000 =20 -struct __packed __cacheline_aligned tss_struct { +struct __packed tss_struct { uint32_t :32; uint64_t rsp0, rsp1, rsp2; uint64_t :64; @@ -425,6 +425,7 @@ struct __packed __cacheline_aligned tss_struct { /* Pads the TSS to be cacheline-aligned (total size is 0x80). */ uint8_t __cacheline_filler[24]; }; +DECLARE_PER_CPU(struct tss_struct, init_tss); =20 #define IST_NONE 0UL #define IST_DF 1UL @@ -463,7 +464,6 @@ static inline void disable_each_ist(idt_entry_t *idt) extern idt_entry_t idt_table[]; extern idt_entry_t *idt_tables[]; =20 -DECLARE_PER_CPU(struct tss_struct, init_tss); DECLARE_PER_CPU(root_pgentry_t *, root_pgt); =20 extern void write_ptbase(struct vcpu *v); --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel