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d="scan'208";a="3182352" From: Roger Pau Monne To: Date: Fri, 19 Jul 2019 16:07:24 +0200 Message-ID: <20190719140724.69596-7-roger.pau@citrix.com> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190719140724.69596-1-roger.pau@citrix.com> References: <20190719140724.69596-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 6/6] pci: switch pci_conf_write32 to use pci_sbdf_t X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Stefano Stabellini , Suravee Suthikulpanit , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich , Brian Woods , Roger Pau Monne Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This reduces the number of parameters of the function to two, and simplifies some of the calling sites. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich Acked-by: Brian Woods --- Cc: Jan Beulich Cc: Andrew Cooper Cc: Wei Liu Cc: George Dunlap Cc: Ian Jackson Cc: Julien Grall Cc: Konrad Rzeszutek Wilk Cc: Stefano Stabellini Cc: Tim Deegan Cc: Suravee Suthikulpanit Cc: Brian Woods Cc: Kevin Tian --- xen/arch/x86/cpu/amd.c | 4 ++-- xen/arch/x86/msi.c | 12 ++++-------- xen/arch/x86/oprofile/op_model_athlon.c | 4 +++- xen/arch/x86/x86_64/pci.c | 17 ++++------------- xen/drivers/char/ehci-dbgp.c | 5 +++-- xen/drivers/char/ns16550.c | 22 ++++++++++++---------- xen/drivers/passthrough/amd/iommu_init.c | 8 ++++---- xen/drivers/passthrough/pci.c | 8 ++++---- xen/drivers/passthrough/vtd/quirks.c | 8 ++++---- xen/drivers/vpci/header.c | 7 +++---- xen/drivers/vpci/vpci.c | 2 +- xen/include/xen/pci.h | 4 +--- 12 files changed, 45 insertions(+), 56 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index f66de362cb..a2f83c79a5 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -714,11 +714,11 @@ static void init_amd(struct cpuinfo_x86 *c) (h & 0x1) ? "clearing D18F3x5C[0]" : ""); =20 if (l & 0x1f) - pci_conf_write32(0, 0, 0x18, 0x3, 0x58, + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x58, l & ~0x1f); =20 if (h & 0x1) - pci_conf_write32(0, 0, 0x18, 0x3, 0x5c, + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x5c, h & ~0x1); } =20 diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index f3e5c5cb03..d6306005a9 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -251,21 +251,17 @@ static int write_msi_msg(struct msi_desc *entry, stru= ct msi_msg *msg) { struct pci_dev *dev =3D entry->dev; int pos =3D entry->msi_attrib.pos; - u16 seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); int nr =3D entry->msi_attrib.entry_nr; =20 ASSERT((msg->data & (entry[-nr].msi.nvec - 1)) =3D=3D nr); if ( nr ) return 0; =20 - pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), + pci_conf_write32(dev->sbdf, msi_lower_address_reg(pos), msg->address_lo); if ( entry->msi_attrib.is_64 ) { - pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(p= os), + pci_conf_write32(dev->sbdf, msi_upper_address_reg(pos), msg->address_hi); pci_conf_write16(dev->sbdf, msi_data_reg(pos, 1), msg->data); } @@ -395,7 +391,7 @@ static bool msi_set_mask_bit(struct irq_desc *desc, boo= l host, bool guest) mask_bits =3D pci_conf_read32(pdev->sbdf, entry->msi.mpos); mask_bits &=3D ~((u32)1 << entry->msi_attrib.entry_nr); mask_bits |=3D (u32)flag << entry->msi_attrib.entry_nr; - pci_conf_write32(seg, bus, slot, func, entry->msi.mpos, mask_b= its); + pci_conf_write32(pdev->sbdf, entry->msi.mpos, mask_bits); } break; case PCI_CAP_ID_MSIX: @@ -716,7 +712,7 @@ static int msi_capability_init(struct pci_dev *dev, /* All MSIs are unmasked by default, Mask them all */ maskbits =3D pci_conf_read32(dev->sbdf, mpos); maskbits |=3D ~(u32)0 >> (32 - maxvec); - pci_conf_write32(seg, bus, slot, func, mpos, maskbits); + pci_conf_write32(dev->sbdf, mpos, maskbits); } list_add_tail(&entry->list, &dev->msi_list); =20 diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index 3bf0b0214d..5c48f868ae 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -472,7 +472,9 @@ static int __init init_ibs_nmi(void) if ((vendor_id =3D=3D PCI_VENDOR_ID_AMD) && (dev_id =3D=3D PCI_DEVICE_ID_AMD_10H_NB_MISC)) { =20 - pci_conf_write32(0, bus, dev, func, IBSCTL, + pci_conf_write32( + PCI_SBDF(0, bus, dev, func), + IBSCTL, IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS); =20 value =3D pci_conf_read32(PCI_SBDF(0, bus, dev, func), diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c index f014fe0fc5..aad1c3f7cf 100644 --- a/xen/arch/x86/x86_64/pci.c +++ b/xen/arch/x86/x86_64/pci.c @@ -66,19 +66,10 @@ void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg= , uint16_t data) pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), reg & 2, 2, data); } =20 -#undef PCI_CONF_ADDRESS -#define PCI_CONF_ADDRESS(bus, dev, func, reg) \ - (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) - -void pci_conf_write32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg, uint32_t data) +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data) { - if ( seg || reg > 255 ) - pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 4, data); + if ( sbdf.seg || reg > 255 ) + pci_mmcfg_write(sbdf.seg, sbdf.bus, sbdf.devfn, reg, 4, data); else - { - BUG_ON((bus > 255) || (dev > 31) || (func > 7)); - pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4, data); - } + pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), 0, 4, data); } diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index b780334953..b6e155d17b 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -1012,7 +1012,8 @@ static void nvidia_set_debug_port(struct ehci_dbgp *d= bgp, unsigned int port) =20 dword &=3D ~(0x0f << 12); dword |=3D (port & 0x0f) << 12; - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74, dword); + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), 0x74, + dword); dbgp_printk("set debug port to %u\n", port); } =20 @@ -1436,7 +1437,7 @@ static void ehci_dbgp_resume(struct serial_port *port) if ( !dbgp->ehci_debug ) return; =20 - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, dbgp->bar, + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), dbgp-= >bar, dbgp->bar_val); pci_conf_write16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), PCI_COMMAND, dbgp->pci_cr); diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 20eaecee59..e518f2d790 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -630,7 +630,8 @@ static void pci_serial_early_init(struct ns16550 *uart) (uart->io_base & 0xF000) | ((uart->io_base & 0xF000) >> 8)); =20 - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0, uart->io_base | PCI_BASE_ADDRESS_SPACE_IO); pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], @@ -860,13 +861,14 @@ static void _ns16550_resume(struct serial_port *port) =20 if ( uart->bar ) { - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[= 2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); =20 /* If 64 bit BAR, write higher 32 bits to BAR+4 */ if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) - pci_conf_write32(0, uart->ps_bdf[0], - uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->ba= r64); =20 pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], @@ -1121,11 +1123,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_a= mt, unsigned int idx) /* MMIO based */ if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) { - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); len =3D pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx * 4= ); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, bar); =20 /* Handle 64 bit BAR if found */ @@ -1133,11 +1135,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_a= mt, unsigned int idx) { bar_64 =3D pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx + 1) *= 4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0= u); len_64 =3D pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4= ); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ba= r_64); size =3D ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_M= ASK; size &=3D ((u64)len_64 << 32) | len; @@ -1151,11 +1153,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_a= mt, unsigned int idx) /* IO based */ else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO= ) ) { - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); len =3D pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, bar); size =3D len & PCI_BASE_ADDRESS_IO_MASK; =20 diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthr= ough/amd/iommu_init.c index f60238a5b8..d970f88a27 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -844,22 +844,22 @@ static void amd_iommu_erratum_746_workaround(struct a= md_iommu *iommu) (boot_cpu_data.x86_model > 0x1f) ) return; =20 - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); value =3D pci_conf_read32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4); =20 if ( value & (1 << 2) ) return; =20 /* Select NB indirect register 0x90 and enable writing */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90 | (1 << 8)); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90 | (1 <<= 8)); =20 - pci_conf_write32(iommu->seg, bus, dev, func, 0xf4, value | (1 << 2)); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4, value | (1 <= < 2)); printk(XENLOG_INFO "AMD-Vi: Applying erratum 746 workaround for IOMMU at %04x:%02x= :%02x.%u\n", iommu->seg, bus, dev, func); =20 /* Clear the enable writing bit */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); } =20 static void enable_iommu(struct amd_iommu *iommu) diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index ee2b9cc01c..7c196ba58b 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -638,7 +638,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned= int pos, ASSERT(!((flags & PCI_BAR_VF) && (flags & PCI_BAR_ROM))); ASSERT((flags & PCI_BAR_ROM) || (bar & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_ME= MORY); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, ~0); + pci_conf_write32(sbdf, pos, ~0); if ( is64bits ) { if ( flags & PCI_BAR_LAST ) @@ -651,17 +651,17 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsign= ed int pos, return 1; } hi =3D pci_conf_read32(sbdf, pos + 4); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, ~= 0); + pci_conf_write32(sbdf, pos + 4, ~0); } size =3D pci_conf_read32(sbdf, pos) & mask; if ( is64bits ) { size |=3D (uint64_t)pci_conf_read32(sbdf, pos + 4) << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, h= i); + pci_conf_write32(sbdf, pos + 4, hi); } else if ( size ) size |=3D (uint64_t)~0 << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, bar); + pci_conf_write32(sbdf, pos, bar); size =3D -size; =20 if ( paddr ) diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough= /vtd/quirks.c index 40bc25d544..d1512b9347 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -439,7 +439,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) case 0x3728: /* Xeon C5500/C3500 (JasperForest) */ case 0x3c28: /* Sandybridge */ val =3D pci_conf_read32(pdev->sbdf, 0x1AC); - pci_conf_write32(seg, bus, dev, func, 0x1AC, val | (1 << 31)); + pci_conf_write32(pdev->sbdf, 0x1AC, val | (1 << 31)); printk(XENLOG_INFO "Masked VT-d error signaling on %04x:%02x:%02x.= %u\n", seg, bus, dev, func); break; @@ -487,9 +487,9 @@ void pci_vtd_quirk(const struct pci_dev *pdev) action =3D "Found masked"; else if ( !ff ) { - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_UNCOR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_UNCOR_MASK, val | PCI_ERR_UNC_UNSUP); - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_COR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_COR_MASK, val2 | PCI_ERR_COR_ADV_NFAT); action =3D "Masked"; } @@ -498,7 +498,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) =20 /* XPUNCERRMSK Send Completion with Unsupported Request */ val =3D pci_conf_read32(pdev->sbdf, 0x20c); - pci_conf_write32(seg, bus, dev, func, 0x20c, val | (1 << 4)); + pci_conf_write32(pdev->sbdf, 0x20c, val | (1 << 4)); =20 printk(XENLOG_INFO "%s UR signaling on %04x:%02x:%02x.%u\n", action, seg, bus, dev, func); diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index f377e6abdf..3c794f486d 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -85,7 +85,6 @@ static void modify_decoding(const struct pci_dev *pdev, u= int16_t cmd, bool rom_only) { struct vpci_header *header =3D &pdev->vpci->header; - uint8_t slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); bool map =3D cmd & PCI_COMMAND_MEMORY; unsigned int i; =20 @@ -113,7 +112,7 @@ static void modify_decoding(const struct pci_dev *pdev,= uint16_t cmd, (map ? PCI_ROM_ADDRESS_ENABLE : 0); =20 header->bars[i].enabled =3D header->rom_enabled =3D map; - pci_conf_write32(pdev->seg, pdev->bus, slot, func, rom_pos, va= l); + pci_conf_write32(pdev->sbdf, rom_pos, val); return; } =20 @@ -395,7 +394,7 @@ static void bar_write(const struct pci_dev *pdev, unsig= ned int reg, val |=3D bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0; } =20 - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } =20 static void rom_write(const struct pci_dev *pdev, unsigned int reg, @@ -426,7 +425,7 @@ static void rom_write(const struct pci_dev *pdev, unsig= ned int reg, { /* Just update the ROM BAR field. */ header->rom_enabled =3D new_enabled; - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } /* * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note th= at diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 6cef5e420a..758d9420e7 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -253,7 +253,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int= reg, unsigned int size, switch ( size ) { case 4: - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, reg, data); + pci_conf_write32(sbdf, reg, data); break; =20 case 3: diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index bfdfca057b..8148f5b2e7 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -177,9 +177,7 @@ uint16_t pci_conf_read16(pci_sbdf_t sbdf, unsigned int = reg); uint32_t pci_conf_read32(pci_sbdf_t sbdf, unsigned int reg); void pci_conf_write8(pci_sbdf_t sbdf, unsigned int reg, uint8_t data); void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data); -void pci_conf_write32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg, uint32_t data); +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data); uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes); void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t = data); int pci_mmcfg_read(unsigned int seg, unsigned int bus, --=20 2.20.1 (Apple Git-117) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel