From nobody Tue Nov 11 13:18:03 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1560900123; cv=none; d=zoho.com; s=zohoarc; b=BoKbAmYv8/jRZE3BKU7Ah1wV2BaEVmg4fJ9+lZDZqAJz+PujIqQ7ocgXfywnEkClzMq3laewQN3oU16y6bxvuUQuO4AB0HZOUyWNVbZPP5nqg/jUND5K6rVKWqVAUfDWGGPRRklzGMfbUth6O+S0dcKoFlG6PbGJrOtojveO5Wc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560900123; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=QGVm8mMUWWp291y6XixrFL9Jt/M2LZC6tonEYn1LYK8=; b=Q0RjD8XZIMNe/CJHHnNeZs0c9mDnjbg1a9L7qft9WzUoD9fN4tZteOJejUd9XXqs/sxtZXAiEOM7XpbaXG2x6V8/KqIYGuSyQR4EpJnDQ6grlpBQWiFyIcje/ucPRs1kuEEZmjQnK4miU+LnqRe78IB/Yq1g3ns6wHP4Ex+Hzuk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1560900123325235.7340180031224; Tue, 18 Jun 2019 16:22:03 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hdNOt-0004sL-Sv; Tue, 18 Jun 2019 23:20:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hdNOr-0004rb-PF for xen-devel@lists.xenproject.org; Tue, 18 Jun 2019 23:20:25 +0000 Received: from mail.kernel.org (unknown [198.145.29.99]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id a6a40978-921f-11e9-a5e4-f7cb9184a011; Tue, 18 Jun 2019 23:20:25 +0000 (UTC) Received: from sstabellini-ThinkPad-T480s.hsd1.ca.comcast.net (c-67-164-102-47.hsd1.ca.comcast.net [67.164.102.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6A4B721479; Tue, 18 Jun 2019 23:20:24 +0000 (UTC) X-Inumbo-ID: a6a40978-921f-11e9-a5e4-f7cb9184a011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560900024; bh=2DrpelDctcvXkXSvHa1gX5/UiYIw+GVWWZ3Km79MV/0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ESGcy4hAbHSqng2VDwVDoszRU8vDRorkt/bESRqeqVzbXB7Htm3JLvFlRQ3snD6Gl kAsCkwQN+kJ2PmHkFt9CRpoRKXV88Jd4jIo4EjflVqU+oIoDPAlQKTQJzjYKVV5dzK +gElHPY/nhJhw78Dw8XfevJbVXxsjUgI0luNleQQ= From: Stefano Stabellini To: xen-devel@lists.xenproject.org Date: Tue, 18 Jun 2019 16:20:16 -0700 Message-Id: <20190618232019.26425-2-sstabellini@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Subject: [Xen-devel] [PATCH v3 2/5] xen: extend XEN_DOMCTL_memory_mapping to handle memory policy X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , julien.grall@arm.com, sstabellini@kernel.org, JBeulich@suse.com, andrew.cooper3@citrix.com MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reuse the existing padding field to pass memory policy information. On Arm, the caller can specify whether the memory should be mapped as Device-nGnRE (Device Memory on Armv7) at stage-2, which is the default and the only possibility today, or cacheable memory write-back. The resulting memory attributes will be a combination of stage-2 and stage-1 memory attributes: it will actually be the strongest between the 2 stages attributes. On x86, the only option is uncachable. The current behavior becomes the default (numerically '0'). Also explicitely set the memory_policy field to 0 in libxc. On ARM, map Device-nGnRE as p2m_mmio_direct_dev (as it is already done today) and WB cacheable memory as p2m_mmio_direct_c. On x86, return error if the memory policy requested is not MEMORY_POLICY_X86_UC_MINUS. Signed-off-by: Stefano Stabellini CC: JBeulich@suse.com CC: andrew.cooper3@citrix.com --- Andrew suggested to remove MEMORY_POLICY_X86_UC_MINUS completely. If that's the consensus I am happy to respin the series removing code. Changes in v3: - error handling in default label of the switch - set memory_policy to 0 in libxc - improve commit message - improve comments - s/Device-nGRE/Device-nGnRE/g - add in-code comment - s/MEMORY_POLICY_X86_UC/MEMORY_POLICY_X86_UC_MINUS/g - #ifdef hypercall defines according to arch Changes in v2: - rebase - use p2m_mmio_direct_c - use EOPNOTSUPP - rename cache_policy to memory policy - rename MEMORY_POLICY_DEVMEM to MEMORY_POLICY_ARM_DEV_nGRE - rename MEMORY_POLICY_MEMORY to MEMORY_POLICY_ARM_MEM_WB - add MEMORY_POLICY_X86_UC - add MEMORY_POLICY_DEFAULT and use it --- tools/libxc/xc_domain.c | 1 + xen/common/domctl.c | 24 ++++++++++++++++++++++-- xen/include/public/domctl.h | 23 ++++++++++++++++++++++- 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/tools/libxc/xc_domain.c b/tools/libxc/xc_domain.c index 05d771f2ce..8531298563 100644 --- a/tools/libxc/xc_domain.c +++ b/tools/libxc/xc_domain.c @@ -2070,6 +2070,7 @@ int xc_domain_memory_mapping( domctl.cmd =3D XEN_DOMCTL_memory_mapping; domctl.domain =3D domid; domctl.u.memory_mapping.add_mapping =3D add_mapping; + domctl.u.memory_mapping.memory_policy =3D 0; max_batch_sz =3D nr_mfns; do { diff --git a/xen/common/domctl.c b/xen/common/domctl.c index c6fd88d285..f21f6957b0 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -928,6 +928,7 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_d= omctl) unsigned long mfn_end =3D mfn + nr_mfns - 1; int add =3D op->u.memory_mapping.add_mapping; p2m_type_t p2mt; + uint32_t memory_policy =3D op->u.memory_mapping.memory_policy; =20 ret =3D -EINVAL; if ( mfn_end < mfn || /* wrap? */ @@ -958,9 +959,28 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_= domctl) if ( add ) { printk(XENLOG_G_DEBUG - "memory_map:add: dom%d gfn=3D%lx mfn=3D%lx nr=3D%lx\n", - d->domain_id, gfn, mfn, nr_mfns); + "memory_map:add: dom%d gfn=3D%lx mfn=3D%lx nr=3D%lx cac= he=3D%u\n", + d->domain_id, gfn, mfn, nr_mfns, memory_policy); =20 + switch ( memory_policy ) + { +#ifdef CONFIG_ARM + case MEMORY_POLICY_ARM_MEM_WB: + p2mt =3D p2m_mmio_direct_c; + break; + case MEMORY_POLICY_ARM_DEV_nGnRE: + p2mt =3D p2m_mmio_direct_dev; + break; +#endif +#ifdef CONFIG_X86 + case MEMORY_POLICY_X86_UC_MINUS: + p2mt =3D p2m_mmio_direct; + break; +#endif + default: + domctl_lock_release(); + goto domctl_out_unlock_domonly; + } ret =3D map_mmio_regions(d, _gfn(gfn), nr_mfns, _mfn(mfn), p2m= t); if ( ret < 0 ) printk(XENLOG_G_WARNING diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 19486d5e32..e51caada35 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -571,12 +571,33 @@ struct xen_domctl_bind_pt_irq { */ #define DPCI_ADD_MAPPING 1 #define DPCI_REMOVE_MAPPING 0 +/* + * Default memory policy. Corresponds to: + * Arm: MEMORY_POLICY_ARM_DEV_nGnRE + * x86: MEMORY_POLICY_X86_UC_MINUS + */ +#define MEMORY_POLICY_DEFAULT 0 +#if defined(__i386__) || defined(__x86_64__) +/* x86 only. Memory type UNCACHABLE */ +# define MEMORY_POLICY_X86_UC_MINUS 0 +#elif defined(__arm__) || defined (__aarch64__) +/* Arm only. Outer Shareable, Device-nGnRE memory (Device Memory on Armv7)= */ +# define MEMORY_POLICY_ARM_DEV_nGnRE 0 +/* Arm only. Outer Shareable, Outer/Inner Write-Back Cacheable memory */ +# define MEMORY_POLICY_ARM_MEM_WB 1 +/* + * On ARM, MEMORY_POLICY selects the stage-2 memory attributes, but note + * that the resulting memory attributes will be a combination of stage-2 + * and stage-1 memory attributes: it will be the strongest between the 2 + * stages attributes. + */ +#endif struct xen_domctl_memory_mapping { uint64_aligned_t first_gfn; /* first page (hvm guest phys page) in ran= ge */ uint64_aligned_t first_mfn; /* first page (machine page) in range */ uint64_aligned_t nr_mfns; /* number of pages in range (>0) */ uint32_t add_mapping; /* add or remove mapping */ - uint32_t padding; /* padding for 64-bit aligned structure */ + uint32_t memory_policy; /* cacheability of the memory mapping */ }; =20 =20 --=20 2.17.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel