From nobody Sat Apr 20 14:50:24 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1557835972; cv=none; d=zoho.com; s=zohoarc; b=L9AJzjEPtMEtppc9kkOZzsnH0HXHC0wZECijmz1JH8tGRnSjf7pgdN9waLokqfPxivBKEP/pBgtyeC70XwyZ/SRuoiqaz/ulAqSnhuxIoYqUx0Lb+5g6t8t7Q4jx9gX6bUYM4Qj3Plg7Pl3fy0x69GI3ItMxwTNIXnbNOyVPAB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557835972; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=l7IMz6SmFkbIDcRqmOwsxEm6qLyqX/4jEzjnX1BC1qQ=; b=nqYikqhLMlacs70NySOsBg/rnp0gchgcJIGuLv82hyi02Gi8fW7Tvh0aU1erCb1eVrvfwqaZLiRXU0P3ek0v4G0xJSVTm4shzILhne2CKTR+Eys0hw1AzvBo1uIRusePVZrer9M5+iU/h6KCa0EZ9J0qHYhsgcXG4HV8Ph7f8hI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1557835971910975.7774186312448; Tue, 14 May 2019 05:12:51 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWHX-0006EB-Od; Tue, 14 May 2019 12:11:43 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWHV-0006DS-O4 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:11:41 +0000 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 6e6b95e8-7641-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:11:40 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A10CC15AB; Tue, 14 May 2019 05:11:40 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 905D03F71E; Tue, 14 May 2019 05:11:39 -0700 (PDT) X-Inumbo-ID: 6e6b95e8-7641-11e9-8980-bc764e045a96 From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:11:25 +0100 Message-Id: <20190514121132.26732-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514121132.26732-1-julien.grall@arm.com> References: <20190514121132.26732-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The AIVIVT is a type of instruction cache available on Armv7. This is the only cache not implementing the IVIPT extension and therefore requiring specific care. To simplify maintenance requirements, Xen will not boot on platform using AIVIVT cache. This should not be an issue because Xen Arm32 can only boot on a small number of processors (see arch/arm/arm32/proc-v7.S). All of them are not using AIVIVT cache. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v3: - Patch added --- xen/arch/arm/setup.c | 5 +++++ xen/include/asm-arm/processor.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index ccb0f181ea..faaf029b99 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, = size_t dtb_size) unsigned long boot_mfn_start, boot_mfn_end; int i; void *fdt; + const uint32_t ctr =3D READ_CP32(CTR); =20 if ( !bootinfo.mem.nr_banks ) panic("No memory bank\n"); =20 + /* We only supports instruction caches implementing the IVIPT extensio= n. */ + if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) =3D=3D CTR_L1Ip_AIVIVT ) + panic("AIVIVT instruction cache not supported\n"); + init_pdx(); =20 ram_start =3D bootinfo.mem.bank[0].start; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processo= r.h index b5f515805d..04b05b3f39 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -6,6 +6,11 @@ #endif #include =20 +/* CTR Cache Type Register */ +#define CTR_L1Ip_MASK 0x3 +#define CTR_L1Ip_SHIFT 14 +#define CTR_L1Ip_AIVIVT 0x1 + /* MIDR Main ID Register */ #define MIDR_REVISION_MASK 0xf #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) --=20 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel