From nobody Sat Apr 20 05:38:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1557504811; cv=none; d=zoho.com; s=zohoarc; b=LeyqtHnFdlgUqgJaJAEb5+pKqV+0mr53sKI4FTdwNqoVUjSbEvnOtLM9OioSlBknrfwhXItfzcF5G5+l0YKinFeQXE1C6DrcQjVgD1DLjJfhm9NLLEfxqWoozPIdCJYYxO15IhS4Vqu9oNaRP59qicMh+ERYDNp1u7Qod9DF40k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557504811; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ki1AcY1iE3JJOtiz8YZ6jMyINLbSEqKSbEZWZStidRQ=; b=YzpZQxUwd5DUZ0mUccDhywyz82HaVlmduYKJvOwL3Wptv+VfUUn3HRzaJceeu4LJyCfC+SDqwfx6ctWwdyTtIjo1XoRxoQliL8LBv6KNfNCIVqJTRLNXV9c9Jl0Q7TGB1djuDabez9OlPdn9r818FcksPmVpuuz85Om2I/lsPyU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1557504811534529.7682048008924; Fri, 10 May 2019 09:13:31 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hP87s-0004aT-3F; Fri, 10 May 2019 16:12:00 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hP87q-0004Zu-HX for xen-devel@lists.xenproject.org; Fri, 10 May 2019 16:11:58 +0000 Received: from SMTP03.CITRIX.COM (unknown [162.221.156.55]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 53189c88-733e-11e9-8980-bc764e045a96; Fri, 10 May 2019 16:11:53 +0000 (UTC) X-Inumbo-ID: 53189c88-733e-11e9-8980-bc764e045a96 X-IronPort-AV: E=Sophos;i="5.60,453,1549929600"; d="scan'208";a="85330717" From: Roger Pau Monne To: Date: Fri, 10 May 2019 18:10:54 +0200 Message-ID: <20190510161056.48648-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.17.2 (Apple Git-113) In-Reply-To: <20190510161056.48648-1-roger.pau@citrix.com> References: <20190510161056.48648-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 3/5] pci: switch pci_conf_{read/write} to use pci_sbdf_t X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Stefano Stabellini , Wei Liu , Suravee Suthikulpanit , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich , Brian Woods , Roger Pau Monne Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" pci_dev already uses pci_sbdf_t, so propagate the usage of the type to pci_conf functions in order to shorten the calls when made from a pci_dev struct. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 --- Cc: Jan Beulich Cc: Andrew Cooper Cc: Wei Liu Cc: George Dunlap Cc: Ian Jackson Cc: Julien Grall Cc: Konrad Rzeszutek Wilk Cc: Stefano Stabellini Cc: Tim Deegan Cc: Suravee Suthikulpanit Cc: Brian Woods Cc: Kevin Tian --- xen/arch/x86/cpu/amd.c | 27 ++-- xen/arch/x86/dmi_scan.c | 9 +- xen/arch/x86/mm.c | 2 +- xen/arch/x86/msi.c | 177 +++++++++------------ xen/arch/x86/oprofile/op_model_athlon.c | 12 +- xen/arch/x86/x86_64/mmconf-fam10h.c | 13 +- xen/arch/x86/x86_64/mmconfig-shared.c | 26 +-- xen/arch/x86/x86_64/pci.c | 32 ++-- xen/drivers/acpi/reboot.c | 8 +- xen/drivers/char/ehci-dbgp.c | 75 +++++---- xen/drivers/char/ns16550.c | 80 +++++----- xen/drivers/passthrough/amd/iommu_detect.c | 3 +- xen/drivers/passthrough/amd/iommu_init.c | 26 +-- xen/drivers/passthrough/ats.h | 4 +- xen/drivers/passthrough/pci.c | 106 +++++------- xen/drivers/passthrough/vtd/dmar.c | 18 ++- xen/drivers/passthrough/vtd/quirks.c | 69 ++++---- xen/drivers/passthrough/x86/ats.c | 15 +- xen/drivers/pci/pci.c | 43 +++-- xen/drivers/video/vga.c | 21 +-- xen/drivers/vpci/header.c | 53 ++---- xen/drivers/vpci/msi.c | 6 +- xen/drivers/vpci/msix.c | 12 +- xen/drivers/vpci/vpci.c | 42 ++--- xen/include/xen/pci.h | 29 ++-- 25 files changed, 444 insertions(+), 464 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index e19a5ead3e..014d88925c 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -417,15 +417,21 @@ static void disable_c1_ramping(void) int node, nr_nodes; =20 /* Read the number of nodes from the first Northbridge. */ - nr_nodes =3D ((pci_conf_read32(0, 0, 0x18, 0x0, 0x60)>>4)&0x07)+1; + nr_nodes =3D ((pci_conf_read32(PCI_SBDF_T(0, 0, 0x18, 0), + 0x60)>>4)&0x07)+1; for (node =3D 0; node < nr_nodes; node++) { + const pci_sbdf_t sbdf =3D { + .dev =3D 0x18 + node, + .func =3D 0x3 + }; + /* PMM7: bus=3D0, dev=3D0x18+node, function=3D0x3, register=3D0x87. */ - pmm7 =3D pci_conf_read8(0, 0, 0x18+node, 0x3, 0x87); + pmm7 =3D pci_conf_read8(sbdf, 0x87); /* Invalid read means we've updated every Northbridge. */ if (pmm7 =3D=3D 0xFF) break; pmm7 &=3D 0xFC; /* clear pmm7[1:0] */ - pci_conf_write8(0, 0, 0x18+node, 0x3, 0x87, pmm7); + pci_conf_write8(sbdf, 0x87, pmm7); printk ("AMD: Disabling C1 Clock Ramping Node #%x\n", node); } } @@ -696,8 +702,13 @@ static void init_amd(struct cpuinfo_x86 *c) =20 if (c->x86 =3D=3D 0x16 && c->x86_model <=3D 0xf) { if (c =3D=3D &boot_cpu_data) { - l =3D pci_conf_read32(0, 0, 0x18, 0x3, 0x58); - h =3D pci_conf_read32(0, 0, 0x18, 0x3, 0x5c); + const pci_sbdf_t sbdf =3D { + .dev =3D 0x18, + .func =3D 0x3, + }; + + l =3D pci_conf_read32(sbdf, 0x58); + h =3D pci_conf_read32(sbdf, 0x5c); if ((l & 0x1f) | (h & 0x1)) printk(KERN_WARNING "Applying workaround for erratum 792: %s%s%s\n", @@ -706,12 +717,10 @@ static void init_amd(struct cpuinfo_x86 *c) (h & 0x1) ? "clearing D18F3x5C[0]" : ""); =20 if (l & 0x1f) - pci_conf_write32(0, 0, 0x18, 0x3, 0x58, - l & ~0x1f); + pci_conf_write32(sbdf, 0x58, l & ~0x1f); =20 if (h & 0x1) - pci_conf_write32(0, 0, 0x18, 0x3, 0x5c, - h & ~0x1); + pci_conf_write32(sbdf, 0x5c, h & ~0x1); } =20 rdmsrl(MSR_AMD64_LS_CFG, value); diff --git a/xen/arch/x86/dmi_scan.c b/xen/arch/x86/dmi_scan.c index fcdf2d3952..59557fa57b 100644 --- a/xen/arch/x86/dmi_scan.c +++ b/xen/arch/x86/dmi_scan.c @@ -468,16 +468,19 @@ static __init int broken_toshiba_keyboard(struct dmi_= blacklist *d) static int __init ich10_bios_quirk(struct dmi_system_id *d) { u32 port, smictl; + const pci_sbdf_t sbdf =3D { + .dev =3D 0x1f, + }; =20 - if ( pci_conf_read16(0, 0, 0x1f, 0, PCI_VENDOR_ID) !=3D 0x8086 ) + if ( pci_conf_read16(sbdf, PCI_VENDOR_ID) !=3D 0x8086 ) return 0; =20 - switch ( pci_conf_read16(0, 0, 0x1f, 0, PCI_DEVICE_ID) ) { + switch ( pci_conf_read16(sbdf, PCI_DEVICE_ID) ) { case 0x3a14: case 0x3a16: case 0x3a18: case 0x3a1a: - port =3D (pci_conf_read16(0, 0, 0x1f, 0, 0x40) & 0xff80) + 0x30; + port =3D (pci_conf_read16(sbdf, 0x40) & 0xff80) + 0x30; smictl =3D inl(port); /* turn off LEGACY_USB{,2}_EN if enabled */ if ( smictl & 0x20008 ) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 45fadbab61..37d8141ed2 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5984,7 +5984,7 @@ const struct platform_bad_page *__init get_platform_b= adpages(unsigned int *array } =20 *array_size =3D ARRAY_SIZE(snb_bad_pages); - igd_id =3D pci_conf_read32(0, 0, 2, 0, 0); + igd_id =3D pci_conf_read32(PCI_SBDF_T(0, 0, 2, 0), 0); if ( IS_SNB_GFX(igd_id) ) return snb_bad_pages; =20 diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index f30f592ee2..ad4a72d56b 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -124,29 +124,20 @@ static void msix_put_fixmap(struct arch_msix *msix, i= nt idx) =20 static bool memory_decoded(const struct pci_dev *dev) { - uint8_t bus, slot, func; + pci_sbdf_t sbdf =3D dev->sbdf; =20 - if ( !dev->info.is_virtfn ) + if ( dev->info.is_virtfn ) { - bus =3D dev->sbdf.bus; - slot =3D dev->sbdf.dev; - func =3D dev->sbdf.func; - } - else - { - bus =3D dev->info.physfn.bus; - slot =3D PCI_SLOT(dev->info.physfn.devfn); - func =3D PCI_FUNC(dev->info.physfn.devfn); + sbdf.bus =3D dev->info.physfn.bus; + sbdf.extfunc =3D dev->info.physfn.devfn; } =20 - return !!(pci_conf_read16(dev->sbdf.seg, bus, slot, func, PCI_COMMAND)= & - PCI_COMMAND_MEMORY); + return !!(pci_conf_read16(sbdf, PCI_COMMAND) & PCI_COMMAND_MEMORY); } =20 static bool msix_memory_decoded(const struct pci_dev *dev, unsigned int po= s) { - u16 control =3D pci_conf_read16(dev->sbdf.seg, dev->sbdf.bus, dev->sbd= f.dev, - dev->sbdf.func, msix_control_reg(pos)); + u16 control =3D pci_conf_read16(dev->sbdf, msix_control_reg(pos)); =20 if ( !(control & PCI_MSIX_FLAGS_ENABLE) ) return false; @@ -200,25 +191,20 @@ static bool read_msi_msg(struct msi_desc *entry, stru= ct msi_msg *msg) { struct pci_dev *dev =3D entry->dev; int pos =3D entry->msi_attrib.pos; - uint16_t data, seg =3D dev->sbdf.seg; - uint8_t bus =3D dev->sbdf.bus; - uint8_t slot =3D dev->sbdf.dev; - uint8_t func =3D dev->sbdf.func; + uint16_t data; =20 - msg->address_lo =3D pci_conf_read32(seg, bus, slot, func, + msg->address_lo =3D pci_conf_read32(dev->sbdf, msi_lower_address_reg(pos)); if ( entry->msi_attrib.is_64 ) { - msg->address_hi =3D pci_conf_read32(seg, bus, slot, func, + msg->address_hi =3D pci_conf_read32(dev->sbdf, msi_upper_address_reg(pos)); - data =3D pci_conf_read16(seg, bus, slot, func, - msi_data_reg(pos, 1)); + data =3D pci_conf_read16(dev->sbdf, msi_data_reg(pos, 1)); } else { msg->address_hi =3D 0; - data =3D pci_conf_read16(seg, bus, slot, func, - msi_data_reg(pos, 0)); + data =3D pci_conf_read16(dev->sbdf, msi_data_reg(pos, 0)); } msg->data =3D data; break; @@ -265,28 +251,22 @@ static int write_msi_msg(struct msi_desc *entry, stru= ct msi_msg *msg) { struct pci_dev *dev =3D entry->dev; int pos =3D entry->msi_attrib.pos; - uint16_t seg =3D dev->sbdf.seg; - uint8_t bus =3D dev->sbdf.bus; - uint8_t slot =3D dev->sbdf.dev; - uint8_t func =3D dev->sbdf.func; int nr =3D entry->msi_attrib.entry_nr; =20 ASSERT((msg->data & (entry[-nr].msi.nvec - 1)) =3D=3D nr); if ( nr ) return 0; =20 - pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), - msg->address_lo); + pci_conf_write32(dev->sbdf, msi_lower_address_reg(pos), msg->addre= ss_lo); if ( entry->msi_attrib.is_64 ) { - pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(p= os), + pci_conf_write32(dev->sbdf, msi_upper_address_reg(pos), msg->address_hi); - pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 1), + pci_conf_write16(dev->sbdf, msi_data_reg(pos, 1), msg->data); } else - pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 0), - msg->data); + pci_conf_write16(dev->sbdf, msi_data_reg(pos, 0), msg->data); break; } case PCI_CAP_ID_MSIX: @@ -337,12 +317,18 @@ void set_msi_affinity(struct irq_desc *desc, const cp= umask_t *mask) =20 void __msi_set_enable(u16 seg, u8 bus, u8 slot, u8 func, int pos, int enab= le) { - u16 control =3D pci_conf_read16(seg, bus, slot, func, pos + PCI_MSI_FL= AGS); + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .dev =3D slot, + .func =3D func, + }; + uint16_t control =3D pci_conf_read16(sbdf, pos + PCI_MSI_FLAGS); =20 control &=3D ~PCI_MSI_FLAGS_ENABLE; if ( enable ) control |=3D PCI_MSI_FLAGS_ENABLE; - pci_conf_write16(seg, bus, slot, func, pos + PCI_MSI_FLAGS, control); + pci_conf_write16(sbdf, pos + PCI_MSI_FLAGS, control); } =20 static void msi_set_enable(struct pci_dev *dev, int enable) @@ -369,11 +355,11 @@ static void msix_set_enable(struct pci_dev *dev, int = enable) pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); if ( pos ) { - control =3D pci_conf_read16(seg, bus, slot, func, msix_control_reg= (pos)); + control =3D pci_conf_read16(dev->sbdf, msix_control_reg(pos)); control &=3D ~PCI_MSIX_FLAGS_ENABLE; if ( enable ) control |=3D PCI_MSIX_FLAGS_ENABLE; - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), cont= rol); + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control); } } =20 @@ -406,20 +392,20 @@ static bool msi_set_mask_bit(struct irq_desc *desc, b= ool host, bool guest) { u32 mask_bits; =20 - mask_bits =3D pci_conf_read32(seg, bus, slot, func, entry->msi= .mpos); + mask_bits =3D pci_conf_read32(pdev->sbdf, entry->msi.mpos); mask_bits &=3D ~((u32)1 << entry->msi_attrib.entry_nr); mask_bits |=3D (u32)flag << entry->msi_attrib.entry_nr; - pci_conf_write32(seg, bus, slot, func, entry->msi.mpos, mask_b= its); + pci_conf_write32(pdev->sbdf, entry->msi.mpos, mask_bits); } break; case PCI_CAP_ID_MSIX: maskall =3D pdev->msix->host_maskall; - control =3D pci_conf_read16(seg, bus, slot, func, + control =3D pci_conf_read16(pdev->sbdf, msix_control_reg(entry->msi_attrib.pos)); if ( unlikely(!(control & PCI_MSIX_FLAGS_ENABLE)) ) { pdev->msix->host_maskall =3D 1; - pci_conf_write16(seg, bus, slot, func, + pci_conf_write16(pdev->sbdf, msix_control_reg(entry->msi_attrib.pos), control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); @@ -453,7 +439,7 @@ static bool msi_set_mask_bit(struct irq_desc *desc, boo= l host, bool guest) pdev->msix->host_maskall =3D maskall; if ( maskall || pdev->msix->guest_maskall ) control |=3D PCI_MSIX_FLAGS_MASKALL; - pci_conf_write16(seg, bus, slot, func, + pci_conf_write16(pdev->sbdf, msix_control_reg(entry->msi_attrib.pos), control); return flag; default: @@ -475,9 +461,7 @@ static int msi_get_mask_bit(const struct msi_desc *entr= y) case PCI_CAP_ID_MSI: if ( !entry->msi_attrib.maskbit ) break; - return (pci_conf_read32(entry->dev->sbdf.seg, entry->dev->sbdf.bus, - entry->dev->sbdf.dev, entry->dev->sbdf.fun= c, - entry->msi.mpos) >> + return (pci_conf_read32(entry->dev->sbdf, entry->msi.mpos) >> entry->msi_attrib.entry_nr) & 1; case PCI_CAP_ID_MSIX: if ( unlikely(!msix_memory_decoded(entry->dev, @@ -593,11 +577,9 @@ int setup_msi_irq(struct irq_desc *desc, struct msi_de= sc *msidesc) =20 if ( msidesc->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX ) { - control =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, - pdev->sbdf.dev, pdev->sbdf.func, cpos); + control =3D pci_conf_read16(pdev->sbdf, cpos); if ( !(control & PCI_MSIX_FLAGS_ENABLE) ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.de= v, - pdev->sbdf.func, cpos, + pci_conf_write16(pdev->sbdf, cpos, control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); } @@ -607,8 +589,7 @@ int setup_msi_irq(struct irq_desc *desc, struct msi_des= c *msidesc) : &pci_msi_nonmaskable); =20 if ( !(control & PCI_MSIX_FLAGS_ENABLE) ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, cpos, control); + pci_conf_write16(pdev->sbdf, cpos, control); =20 return rc; } @@ -697,7 +678,7 @@ static int msi_capability_init(struct pci_dev *dev, pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; - control =3D pci_conf_read16(seg, bus, slot, func, msi_control_reg(pos)= ); + control =3D pci_conf_read16(dev->sbdf, msi_control_reg(pos)); maxvec =3D multi_msi_capable(control); if ( nvec > maxvec ) return maxvec; @@ -733,9 +714,9 @@ static int msi_capability_init(struct pci_dev *dev, u32 maskbits; =20 /* All MSIs are unmasked by default, Mask them all */ - maskbits =3D pci_conf_read32(seg, bus, slot, func, mpos); + maskbits =3D pci_conf_read32(dev->sbdf, mpos); maskbits |=3D ~(u32)0 >> (32 - maxvec); - pci_conf_write32(seg, bus, slot, func, mpos, maskbits); + pci_conf_write32(dev->sbdf, mpos, maskbits); } list_add_tail(&entry->list, &dev->msi_list); =20 @@ -751,7 +732,7 @@ static int msi_capability_init(struct pci_dev *dev, pci_intx(dev, false); control |=3D PCI_MSI_FLAGS_ENABLE; } - pci_conf_write16(seg, bus, slot, func, msi_control_reg(pos), control); + pci_conf_write16(dev->sbdf, msi_control_reg(pos), control); =20 return 0; } @@ -761,6 +742,12 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, = u8 func, u8 bir, int vf) u8 limit; u32 addr, base =3D PCI_BASE_ADDRESS_0; u64 disp =3D 0; + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .dev =3D slot, + .func =3D func, + }; =20 if ( vf >=3D 0 ) { @@ -768,13 +755,10 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot,= u8 func, u8 bir, int vf) unsigned int pos =3D pci_find_ext_capability(seg, bus, PCI_DEVFN(slot, func), PCI_EXT_CAP_ID_SRIOV); - u16 ctrl =3D pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV= _CTRL); - u16 num_vf =3D pci_conf_read16(seg, bus, slot, func, - pos + PCI_SRIOV_NUM_VF); - u16 offset =3D pci_conf_read16(seg, bus, slot, func, - pos + PCI_SRIOV_VF_OFFSET); - u16 stride =3D pci_conf_read16(seg, bus, slot, func, - pos + PCI_SRIOV_VF_STRIDE); + u16 ctrl =3D pci_conf_read16(sbdf, pos + PCI_SRIOV_CTRL); + u16 num_vf =3D pci_conf_read16(sbdf, pos + PCI_SRIOV_NUM_VF); + u16 offset =3D pci_conf_read16(sbdf, pos + PCI_SRIOV_VF_OFFSET); + u16 stride =3D pci_conf_read16(sbdf, pos + PCI_SRIOV_VF_STRIDE); =20 if ( !pdev || !pos || !(ctrl & PCI_SRIOV_CTRL_VFE) || @@ -799,8 +783,7 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u= 8 func, u8 bir, int vf) disp =3D vf * pdev->vf_rlen[bir]; limit =3D PCI_SRIOV_NUM_BARS; } - else switch ( pci_conf_read8(seg, bus, slot, func, - PCI_HEADER_TYPE) & 0x7f ) + else switch ( pci_conf_read8(sbdf, PCI_HEADER_TYPE) & 0x7f ) { case PCI_HEADER_TYPE_NORMAL: limit =3D 6; @@ -817,7 +800,7 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u= 8 func, u8 bir, int vf) =20 if ( bir >=3D limit ) return 0; - addr =3D pci_conf_read32(seg, bus, slot, func, base + bir * 4); + addr =3D pci_conf_read32(sbdf, base + bir * 4); if ( (addr & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO ) return 0; if ( (addr & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_M= EM_TYPE_64 ) @@ -826,8 +809,7 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u= 8 func, u8 bir, int vf) if ( ++bir >=3D limit ) return 0; return addr + disp + - ((u64)pci_conf_read32(seg, bus, slot, func, - base + bir * 4) << 32); + ((uint64_t)pci_conf_read32(sbdf, base + bir * 4) << 32); } return (addr & PCI_BASE_ADDRESS_MEM_MASK) + disp; } @@ -863,7 +845,7 @@ static int msix_capability_init(struct pci_dev *dev, =20 ASSERT(pcidevs_locked()); =20 - control =3D pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos= )); + control =3D pci_conf_read16(dev->sbdf, msix_control_reg(pos)); /* * Ensure MSI-X interrupts are masked during setup. Some devices requi= re * MSI-X to be enabled before we can touch the MSI-X registers. We need @@ -871,13 +853,13 @@ static int msix_capability_init(struct pci_dev *dev, * fully set up. */ msix->host_maskall =3D 1; - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); =20 if ( unlikely(!memory_decoded(dev)) ) { - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); return -ENXIO; } @@ -887,7 +869,7 @@ static int msix_capability_init(struct pci_dev *dev, entry =3D alloc_msi_entry(1); if ( !entry ) { - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); return -ENOMEM; } @@ -895,8 +877,7 @@ static int msix_capability_init(struct pci_dev *dev, } =20 /* Locate MSI-X table region */ - table_offset =3D pci_conf_read32(seg, bus, slot, func, - msix_table_offset_reg(pos)); + table_offset =3D pci_conf_read32(dev->sbdf, msix_table_offset_reg(pos)= ); bir =3D (u8)(table_offset & PCI_MSIX_BIRMASK); table_offset &=3D ~PCI_MSIX_BIRMASK; =20 @@ -921,7 +902,7 @@ static int msix_capability_init(struct pci_dev *dev, { if ( !msi || !msi->table_base ) { - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); xfree(entry); return -ENXIO; @@ -942,8 +923,7 @@ static int msix_capability_init(struct pci_dev *dev, WARN_ON(rangeset_overlaps_range(mmio_ro_ranges, msix->table.first, msix->table.last)); =20 - pba_offset =3D pci_conf_read32(seg, bus, slot, func, - msix_pba_offset_reg(pos)); + pba_offset =3D pci_conf_read32(dev->sbdf, msix_pba_offset_reg(pos)= ); bir =3D (u8)(pba_offset & PCI_MSIX_BIRMASK); pba_paddr =3D read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf); WARN_ON(!pba_paddr); @@ -965,7 +945,7 @@ static int msix_capability_init(struct pci_dev *dev, =20 if ( idx < 0 ) { - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); xfree(entry); return idx; @@ -1041,7 +1021,7 @@ static int msix_capability_init(struct pci_dev *dev, maskall =3D 0; } msix->host_maskall =3D maskall; - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control); =20 return 0; } @@ -1130,8 +1110,7 @@ static int __pci_enable_msix(struct msi_info *msi, st= ruct msi_desc **desc) if ( !pdev || !pos ) return -ENODEV; =20 - control =3D pci_conf_read16(msi->seg, msi->bus, slot, func, - msix_control_reg(pos)); + control =3D pci_conf_read16(pdev->sbdf, msix_control_reg(pos)); nr_entries =3D multi_msix_capable(control); if ( msi->entry_nr >=3D nr_entries ) return -EINVAL; @@ -1177,14 +1156,14 @@ static void __pci_disable_msix(struct msi_desc *ent= ry) uint8_t func =3D dev->sbdf.func; unsigned int pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); - u16 control =3D pci_conf_read16(seg, bus, slot, func, - msix_control_reg(entry->msi_attrib.pos)); + uint16_t control =3D pci_conf_read16(dev->sbdf, + msix_control_reg(entry->msi_attrib.= pos)); bool maskall =3D dev->msix->host_maskall; =20 if ( unlikely(!(control & PCI_MSIX_FLAGS_ENABLE)) ) { dev->msix->host_maskall =3D 1; - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); } @@ -1203,7 +1182,7 @@ static void __pci_disable_msix(struct msi_desc *entry) dev->msix->host_maskall =3D maskall; if ( maskall || dev->msix->guest_maskall ) control |=3D PCI_MSIX_FLAGS_MASKALL; - pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); + pci_conf_write16(dev->sbdf, msix_control_reg(pos), control); =20 _pci_cleanup_msix(dev->msix); } @@ -1235,8 +1214,7 @@ int pci_prepare_msix(u16 seg, u8 bus, u8 devfn, bool = off) } else { - u16 control =3D pci_conf_read16(seg, bus, slot, func, - msix_control_reg(pos)); + uint16_t control =3D pci_conf_read16(pdev->sbdf, msix_control_reg(= pos)); =20 rc =3D msix_capability_init(pdev, pos, NULL, NULL, multi_msix_capable(control)); @@ -1337,7 +1315,7 @@ int pci_msi_conf_write_intercept(struct pci_dev *pdev= , unsigned int reg, if ( reg < entry->msi.mpos || reg >=3D entry->msi.mpos + 4 || size= !=3D 4 ) return -EACCES; =20 - cntl =3D pci_conf_read16(seg, bus, slot, func, msi_control_reg(pos= )); + cntl =3D pci_conf_read16(pdev->sbdf, msi_control_reg(pos)); unused =3D ~(uint32_t)0 >> (32 - multi_msi_capable(cntl)); for ( pos =3D 0; pos < entry->msi.nvec; ++pos, ++entry ) { @@ -1396,8 +1374,7 @@ int pci_restore_msi_state(struct pci_dev *pdev) pdev->sbdf.seg, pdev->sbdf.bus, slot, func, i); spin_unlock_irqrestore(&desc->lock, flags); if ( type =3D=3D PCI_CAP_ID_MSIX ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, slot, fun= c, - msix_control_reg(pos), + pci_conf_write16(pdev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); return -EINVAL; } @@ -1411,17 +1388,14 @@ int pci_restore_msi_state(struct pci_dev *pdev) } else if ( !type && entry->msi_attrib.type =3D=3D PCI_CAP_ID_MSIX ) { - control =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, sl= ot, - func, msix_control_reg(pos)); - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, slot, func, - msix_control_reg(pos), + control =3D pci_conf_read16(pdev->sbdf, msix_control_reg(pos)); + pci_conf_write16(pdev->sbdf, msix_control_reg(pos), control | (PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL)); if ( unlikely(!memory_decoded(pdev)) ) { spin_unlock_irqrestore(&desc->lock, flags); - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, slot, fun= c, - msix_control_reg(pos), + pci_conf_write16(pdev->sbdf, msix_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE); return -ENXIO; } @@ -1454,19 +1428,16 @@ int pci_restore_msi_state(struct pci_dev *pdev) { unsigned int cpos =3D msi_control_reg(pos); =20 - control =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, sl= ot, - func, cpos) & ~PCI_MSI_FLAGS_QSIZE; + control =3D pci_conf_read16(pdev->sbdf, cpos) & ~PCI_MSI_FLAGS= _QSIZE; multi_msi_enable(control, entry->msi.nvec); - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, slot, func, c= pos, - control); + pci_conf_write16(pdev->sbdf, cpos, control); =20 msi_set_enable(pdev, 1); } } =20 if ( type =3D=3D PCI_CAP_ID_MSIX ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, slot, func, - msix_control_reg(pos), + pci_conf_write16(pdev->sbdf, msix_control_reg(pos), control | PCI_MSIX_FLAGS_ENABLE); =20 return 0; diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index 3d6e26f636..33f7394979 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -463,7 +463,13 @@ static int __init init_ibs_nmi(void) for (bus =3D 0; bus < 256; bus++) { for (dev =3D 0; dev < 32; dev++) { for (func =3D 0; func < 8; func++) { - id =3D pci_conf_read32(0, bus, dev, func, PCI_VENDOR_ID); + const pci_sbdf_t sbdf =3D { + .bus =3D bus, + .dev =3D dev, + .func =3D func, + }; + =20 + id =3D pci_conf_read32(sbdf, PCI_VENDOR_ID); =20 vendor_id =3D id & 0xffff; dev_id =3D (id >> 16) & 0xffff; @@ -471,10 +477,10 @@ static int __init init_ibs_nmi(void) if ((vendor_id =3D=3D PCI_VENDOR_ID_AMD) && (dev_id =3D=3D PCI_DEVICE_ID_AMD_10H_NB_MISC)) { =20 - pci_conf_write32(0, bus, dev, func, IBSCTL, + pci_conf_write32(sbdf, IBSCTL, IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS); =20 - value =3D pci_conf_read32(0, bus, dev, func, IBSCTL); + value =3D pci_conf_read32(sbdf, IBSCTL); =20 if (value !=3D (IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS)) { diff --git a/xen/arch/x86/x86_64/mmconf-fam10h.c b/xen/arch/x86/x86_64/mmco= nf-fam10h.c index ed0acb9968..e7f02de894 100644 --- a/xen/arch/x86/x86_64/mmconf-fam10h.c +++ b/xen/arch/x86/x86_64/mmconf-fam10h.c @@ -38,21 +38,22 @@ static struct pci_hostbridge_probe pci_probes[] =3D { #define BASE_VALID(b) ((b) + SIZE <=3D (0xfdULL<<32) || (b) >=3D (1ULL<<40= )) static void __init get_fam10h_pci_mmconf_base(void) { - unsigned int i, j, bus, slot, hi_mmio_num; + unsigned int i, j, hi_mmio_num; u32 address; u64 val, tom2, start, end; struct range { u64 start, end; } range[8]; + pci_sbdf_t sbdf =3D { }; =20 for (i =3D 0; i < ARRAY_SIZE(pci_probes); i++) { u32 id; u16 device; u16 vendor; =20 - bus =3D pci_probes[i].bus; - slot =3D pci_probes[i].slot; - id =3D pci_conf_read32(0, bus, slot, 0, PCI_VENDOR_ID); + sbdf.bus =3D pci_probes[i].bus; + sbdf.dev =3D pci_probes[i].slot; + id =3D pci_conf_read32(sbdf, PCI_VENDOR_ID); =20 vendor =3D id & 0xffff; device =3D (id>>16) & 0xffff; @@ -83,12 +84,12 @@ static void __init get_fam10h_pci_mmconf_base(void) * above 4G */ for (hi_mmio_num =3D i =3D 0; i < 8; i++) { - val =3D pci_conf_read32(0, bus, slot, 1, 0x80 + (i << 3)); + val =3D pci_conf_read32(sbdf, 0x80 + (i << 3)); if (!(val & 3)) continue; =20 start =3D (val & 0xffffff00) << 8; /* 39:16 on 31:8*/ - val =3D pci_conf_read32(0, bus, slot, 1, 0x84 + (i << 3)); + val =3D pci_conf_read32(sbdf, 0x84 + (i << 3)); end =3D ((val & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/ =20 if (end < tom2) diff --git a/xen/arch/x86/x86_64/mmconfig-shared.c b/xen/arch/x86/x86_64/mm= config-shared.c index 9e1c81dcd2..284a788fcd 100644 --- a/xen/arch/x86/x86_64/mmconfig-shared.c +++ b/xen/arch/x86/x86_64/mmconfig-shared.c @@ -63,10 +63,8 @@ custom_param("mmcfg", parse_mmcfg); =20 static const char __init *pci_mmcfg_e7520(void) { - u32 win; - win =3D pci_conf_read16(0, 0, 0, 0, 0xce); + uint32_t win =3D pci_conf_read16(PCI_SBDF_T(0, 0, 0, 0), 0xce) & 0xf00= 0; =20 - win =3D win & 0xf000; if(win =3D=3D 0x0000 || win =3D=3D 0xf000) pci_mmcfg_config_num =3D 0; else { @@ -89,7 +87,7 @@ static const char __init *pci_mmcfg_intel_945(void) =20 pci_mmcfg_config_num =3D 1; =20 - pciexbar =3D pci_conf_read32(0, 0, 0, 0, 0x48); + pciexbar =3D pci_conf_read32(PCI_SBDF_T(0, 0, 0, 0), 0x48); =20 /* Enable bit */ if (!(pciexbar & 1)) @@ -212,15 +210,18 @@ static const char __init *pci_mmcfg_nvidia_mcp55(void) for (i =3D bus =3D 0; bus < 256; bus++) { u32 l, extcfg; u16 vendor, device; + const pci_sbdf_t sbdf =3D { + .bus =3D bus, + }; =20 - l =3D pci_conf_read32(0, bus, 0, 0, 0); + l =3D pci_conf_read32(sbdf, 0); vendor =3D l & 0xffff; device =3D (l >> 16) & 0xffff; =20 if (PCI_VENDOR_ID_NVIDIA !=3D vendor || 0x0369 !=3D device) continue; =20 - extcfg =3D pci_conf_read32(0, bus, 0, 0, extcfg_regnum); + extcfg =3D pci_conf_read32(sbdf, extcfg_regnum); =20 if (extcfg & extcfg_enable_mask) i++; @@ -238,15 +239,18 @@ static const char __init *pci_mmcfg_nvidia_mcp55(void) u32 l, extcfg; u16 vendor, device; int size_index; + const pci_sbdf_t sbdf =3D { + .bus =3D bus, + }; =20 - l =3D pci_conf_read32(0, bus, 0, 0, 0); + l =3D pci_conf_read32(sbdf, 0); vendor =3D l & 0xffff; device =3D (l >> 16) & 0xffff; =20 if (PCI_VENDOR_ID_NVIDIA !=3D vendor || 0x0369 !=3D device) continue; =20 - extcfg =3D pci_conf_read32(0, bus, 0, 0, extcfg_regnum); + extcfg =3D pci_conf_read32(sbdf, extcfg_regnum); =20 if (!(extcfg & extcfg_enable_mask)) continue; @@ -300,7 +304,6 @@ static struct pci_mmcfg_hostbridge_probe pci_mmcfg_prob= es[] __initdata =3D { static int __init pci_mmcfg_check_hostbridge(void) { u32 l; - u32 bus, devfn; u16 vendor, device; int i; const char *name; @@ -310,9 +313,8 @@ static int __init pci_mmcfg_check_hostbridge(void) name =3D NULL; =20 for (i =3D 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { - bus =3D pci_mmcfg_probes[i].bus; - devfn =3D pci_mmcfg_probes[i].devfn; - l =3D pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); + l =3D pci_conf_read32(PCI_SBDF3_T(0, pci_mmcfg_probes[i].bus, + pci_mmcfg_probes[i].devfn), 0); vendor =3D l & 0xffff; device =3D (l >> 16) & 0xffff; =20 diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c index 4f77beb119..342c2aa8e6 100644 --- a/xen/arch/x86/x86_64/pci.c +++ b/xen/arch/x86/x86_64/pci.c @@ -8,25 +8,20 @@ #include #include =20 -#define PCI_CONF_ADDRESS(bus, dev, func, reg) \ - (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) +#define PCI_CONF_ADDRESS(bdf, reg) (0x80000000 | (bdf << 8) | (reg & ~3)) =20 #define GEN_PCI_CONF_READ(s) = \ - uint ## s ## _t pci_conf_read ## s (unsigned int seg, unsigned int bus= , \ - unsigned int dev, unsigned int fun= c, \ - unsigned int reg) = \ + uint ## s ## _t pci_conf_read ## s (pci_sbdf_t sbdf, unsigned int reg= ) \ { = \ uint32_t value; = \ = \ BUILD_BUG_ON(s !=3D 8 && s !=3D 16 && s !=3D 32); = \ - if ( seg || reg > 255 ) = \ - pci_mmcfg_read(seg, bus, PCI_DEVFN(dev, func), reg, s / 8, &va= lue);\ + if ( sbdf.seg || reg > 255 ) = \ + pci_mmcfg_read(sbdf.seg, sbdf.bus, sbdf.extfunc, reg, s / 8, = \ + &value); = \ else = \ - { = \ - BUG_ON((bus > 255) || (dev > 31) || (func > 7)); = \ - value =3D pci_conf_read(PCI_CONF_ADDRESS(bus, dev, func, reg),= \ + value =3D pci_conf_read(PCI_CONF_ADDRESS(sbdf.bdf, reg), = \ reg & (4 - s / 8), s / 8); = \ - } = \ = \ return value; = \ } @@ -47,19 +42,16 @@ GEN_PCI_CONF_READ(32) #undef GEN_PCI_CONF_READ =20 #define GEN_PCI_CONF_WRITE(s) = \ - void pci_conf_write ## s (unsigned int seg, unsigned int bus, = \ - unsigned int dev, unsigned int func, = \ - unsigned int reg, uint ## s ## _t data) = \ + void pci_conf_write ## s (pci_sbdf_t sbdf, unsigned int reg, = \ + uint ## s ## _t data) = \ { = \ BUILD_BUG_ON(s !=3D 8 && s !=3D 16 && s !=3D 32); = \ - if ( seg || reg > 255 ) = \ - pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, s / 8, da= ta); \ + if ( sbdf.seg || reg > 255 ) = \ + pci_mmcfg_write(sbdf.seg, sbdf.bus, sbdf.extfunc, reg, s / 8, = \ + data); = \ else = \ - { = \ - BUG_ON((bus > 255) || (dev > 31) || (func > 7)); = \ - pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), = \ + pci_conf_write(PCI_CONF_ADDRESS(sbdf.bdf, reg), = \ reg & (4 - s / 8), s / 8, data); = \ - } = \ } =20 /* Grep fodder */ diff --git a/xen/drivers/acpi/reboot.c b/xen/drivers/acpi/reboot.c index 72d06fd8e5..919239faa1 100644 --- a/xen/drivers/acpi/reboot.c +++ b/xen/drivers/acpi/reboot.c @@ -23,11 +23,9 @@ void acpi_reboot(void) case ACPI_ADR_SPACE_PCI_CONFIG: printk("Resetting with ACPI PCI RESET_REG.\n"); /* Write the value that resets us. */ - pci_conf_write8(0, 0, - (rr->address >> 32) & 31, - (rr->address >> 16) & 7, - (rr->address & 255), - reset_value); + pci_conf_write8(PCI_SBDF_T(0, 0, (rr->address >> 32) & 31, + (rr->address >> 16) & 7), + (rr->address & 255), reset_value); break; case ACPI_ADR_SPACE_SYSTEM_MEMORY: case ACPI_ADR_SPACE_SYSTEM_IO: diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index 475dc41767..4cd4157353 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -682,7 +682,8 @@ static int dbgp_control_msg(struct ehci_dbgp *dbgp, uns= igned int devnum, =20 static unsigned int __init __find_dbgp(u8 bus, u8 slot, u8 func) { - u32 class =3D pci_conf_read32(0, bus, slot, func, PCI_CLASS_REVISION); + uint32_t class =3D pci_conf_read32(PCI_SBDF_T(0, bus, slot, func), + PCI_CLASS_REVISION); =20 if ( (class >> 8) !=3D PCI_CLASS_SERIAL_USB_EHCI ) return 0; @@ -713,8 +714,9 @@ static unsigned int __init find_dbgp(struct ehci_dbgp *= dbgp, cap =3D __find_dbgp(bus, slot, func); if ( !cap || ehci_num-- ) { - if ( !func && !(pci_conf_read8(0, bus, slot, func, - PCI_HEADER_TYPE) & 0x80= ) ) + if ( !func && + !(pci_conf_read8(PCI_SBDF_T(0, bus, slot, func), + PCI_HEADER_TYPE) & 0x80) ) break; continue; } @@ -1006,17 +1008,22 @@ static set_debug_port_t __read_mostly set_debug_por= t =3D default_set_debug_port; =20 static void nvidia_set_debug_port(struct ehci_dbgp *dbgp, unsigned int por= t) { - u32 dword =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x= 74); + const pci_sbdf_t sbdf =3D { + .bus =3D dbgp->bus, + .dev =3D dbgp->slot, + .func =3D dbgp->func, + }; + uint32_t dword =3D pci_conf_read32(sbdf, 0x74); =20 dword &=3D ~(0x0f << 12); dword |=3D (port & 0x0f) << 12; - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74, dword); + pci_conf_write32(sbdf, 0x74, dword); dbgp_printk("set debug port to %u\n", port); } =20 static void __init detect_set_debug_port(struct ehci_dbgp *dbgp) { - if ( pci_conf_read16(0, dbgp->bus, dbgp->slot, dbgp->func, + if ( pci_conf_read16(PCI_SBDF_T(0, dbgp->bus, dbgp->slot, dbgp->func), PCI_VENDOR_ID) =3D=3D 0x10de ) { dbgp_printk("using nvidia set_debug_port\n"); @@ -1035,17 +1042,22 @@ static void ehci_dbgp_bios_handoff(struct ehci_dbgp= *dbgp, u32 hcc_params) u32 cap; unsigned int offset =3D HCC_EXT_CAPS(hcc_params); int msec; + const pci_sbdf_t sbdf =3D { + .bus =3D dbgp->bus, + .dev =3D dbgp->slot, + .func =3D dbgp->func, + }; =20 if ( !offset ) return; =20 - cap =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offset); + cap =3D pci_conf_read32(sbdf, offset); dbgp_printk("dbgp: EHCI BIOS state %08x\n", cap); =20 if ( (cap & 0xff) =3D=3D 1 && (cap & EHCI_USBLEGSUP_BIOS) ) { dbgp_printk("dbgp: BIOS handoff\n"); - pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func, offset + 3, = 1); + pci_conf_write8(sbdf, offset + 3, 1); } =20 /* if boot firmware now owns EHCI, spin till it hands it over. */ @@ -1054,7 +1066,7 @@ static void ehci_dbgp_bios_handoff(struct ehci_dbgp *= dbgp, u32 hcc_params) { mdelay(10); msec -=3D 10; - cap =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offs= et); + cap =3D pci_conf_read32(sbdf, offset); } =20 if ( cap & EHCI_USBLEGSUP_BIOS ) @@ -1062,12 +1074,11 @@ static void ehci_dbgp_bios_handoff(struct ehci_dbgp= *dbgp, u32 hcc_params) /* well, possibly buggy BIOS... try to shut it down, * and hope nothing goes too wrong */ dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap); - pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func, offset + 2, = 0); + pci_conf_write8(sbdf, offset + 2, 0); } =20 /* just in case, always disable EHCI SMIs */ - pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func, - offset + EHCI_USBLEGCTLSTS, 0); + pci_conf_write8(sbdf, offset + EHCI_USBLEGCTLSTS, 0); } =20 static int ehci_dbgp_setup(struct ehci_dbgp *dbgp) @@ -1306,19 +1317,21 @@ static void __init ehci_dbgp_init_preirq(struct ser= ial_port *port) struct ehci_dbgp *dbgp =3D port->uart; u32 debug_port, offset; void __iomem *ehci_bar; + const pci_sbdf_t sbdf =3D { + .bus =3D dbgp->bus, + .dev =3D dbgp->slot, + .func =3D dbgp->func, + }; =20 - debug_port =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, - dbgp->cap); + debug_port =3D pci_conf_read32(sbdf, dbgp->cap); offset =3D (debug_port >> 16) & 0xfff; =20 /* double check if the mem space is enabled */ - dbgp->pci_cr =3D pci_conf_read8(0, dbgp->bus, dbgp->slot, dbgp->func, - PCI_COMMAND); + dbgp->pci_cr =3D pci_conf_read8(sbdf, PCI_COMMAND); if ( !(dbgp->pci_cr & PCI_COMMAND_MEMORY) ) { dbgp->pci_cr |=3D PCI_COMMAND_MEMORY; - pci_conf_write16(0, dbgp->bus, dbgp->slot, dbgp->func, PCI_COMMAND, - dbgp->pci_cr); + pci_conf_write16(sbdf, PCI_COMMAND, dbgp->pci_cr); dbgp_printk("MMIO for EHCI enabled\n"); } =20 @@ -1415,8 +1428,8 @@ static void ehci_dbgp_suspend(struct serial_port *por= t) stop_timer(&dbgp->timer); dbgp->timer.expires =3D 0; =20 - dbgp->pci_cr =3D pci_conf_read16(0, dbgp->bus, dbgp->slot, dbgp->func, - PCI_COMMAND); + dbgp->pci_cr =3D pci_conf_read16(PCI_SBDF_T(0, dbgp->bus, dbgp->slot, + dbgp->func), PCI_COMMAND); =20 dbgp->state =3D dbgp_unsafe; } @@ -1424,14 +1437,17 @@ static void ehci_dbgp_suspend(struct serial_port *p= ort) static void ehci_dbgp_resume(struct serial_port *port) { struct ehci_dbgp *dbgp =3D port->uart; + const pci_sbdf_t sbdf =3D { + .bus =3D dbgp->bus, + .dev =3D dbgp->slot, + .func =3D dbgp->func, + }; =20 if ( !dbgp->ehci_debug ) return; =20 - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, dbgp->bar, - dbgp->bar_val); - pci_conf_write16(0, dbgp->bus, dbgp->slot, dbgp->func, - PCI_COMMAND, dbgp->pci_cr); + pci_conf_write32(sbdf, dbgp->bar, dbgp->bar_val); + pci_conf_write16(sbdf, PCI_COMMAND, dbgp->pci_cr); =20 ehci_dbgp_setup_preirq(dbgp); ehci_dbgp_setup_postirq(dbgp); @@ -1459,6 +1475,11 @@ void __init ehci_dbgp_init(void) struct ehci_dbgp *dbgp =3D &ehci_dbgp; u32 debug_port, offset, bar_val; const char *e; + const pci_sbdf_t sbdf =3D { + .bus =3D dbgp->bus, + .dev =3D dbgp->slot, + .func =3D dbgp->func, + }; =20 if ( strncmp(opt_dbgp, "ehci", 4) ) return; @@ -1502,8 +1523,7 @@ void __init ehci_dbgp_init(void) else return; =20 - debug_port =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, - dbgp->cap); + debug_port =3D pci_conf_read32(sbdf, dbgp->cap); dbgp->bar =3D (debug_port >> 29) & 0x7; dbgp->bar =3D ((dbgp->bar - 1) * 4) + PCI_BASE_ADDRESS_0; offset =3D (debug_port >> 16) & 0xfff; @@ -1514,8 +1534,7 @@ void __init ehci_dbgp_init(void) return; } =20 - dbgp->bar_val =3D bar_val =3D pci_conf_read32(0, dbgp->bus, dbgp->slot, - dbgp->func, dbgp->bar); + dbgp->bar_val =3D bar_val =3D pci_conf_read32(sbdf, dbgp->bar); dbgp_printk("bar_val: %08x\n", bar_val); if ( bar_val & ~PCI_BASE_ADDRESS_MEM_MASK ) { diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 189e121b7e..698984d879 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -620,20 +620,23 @@ static int ns16550_getc(struct serial_port *port, cha= r *pc) static void pci_serial_early_init(struct ns16550 *uart) { #ifdef CONFIG_HAS_PCI + const pci_sbdf_t sbdf =3D { + .bus =3D uart->pb_bdf[0], + .dev =3D uart->pb_bdf[1], + .func =3D uart->pb_bdf[2], + }; + if ( !uart->ps_bdf_enable || uart->io_base >=3D 0x10000 ) return; =20 if ( uart->pb_bdf_enable ) - pci_conf_write16(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf= [2], - PCI_IO_BASE, + pci_conf_write16(sbdf, PCI_IO_BASE, (uart->io_base & 0xF000) | ((uart->io_base & 0xF000) >> 8)); =20 - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], - PCI_BASE_ADDRESS_0, + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0, uart->io_base | PCI_BASE_ADDRESS_SPACE_IO); - pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], - PCI_COMMAND, PCI_COMMAND_IO); + pci_conf_write16(sbdf, PCI_COMMAND, PCI_COMMAND_IO); #endif } =20 @@ -846,8 +849,9 @@ static void ns16550_suspend(struct serial_port *port) =20 #ifdef CONFIG_HAS_PCI if ( uart->bar ) - uart->cr =3D pci_conf_read16(0, uart->ps_bdf[0], uart->ps_bdf[1], - uart->ps_bdf[2], PCI_COMMAND); + uart->cr =3D pci_conf_read16(PCI_SBDF_T(0, uart->ps_bdf[0], + uart->ps_bdf[1], uart->ps_bd= f[2]), + PCI_COMMAND); #endif } =20 @@ -855,20 +859,22 @@ static void _ns16550_resume(struct serial_port *port) { #ifdef CONFIG_HAS_PCI struct ns16550 *uart =3D port->uart; + const pci_sbdf_t sbdf =3D { + .bus =3D uart->ps_bdf[0], + .dev =3D uart->ps_bdf[1], + .func =3D uart->ps_bdf[2], + }; =20 if ( uart->bar ) { - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[= 2], - PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->= bar); =20 /* If 64 bit BAR, write higher 32 bits to BAR+4 */ if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) - pci_conf_write32(0, uart->ps_bdf[0], - uart->ps_bdf[1], uart->ps_bdf[2], - PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->ba= r64); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*= 4, + uart->bar64); =20 - pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[= 2], - PCI_COMMAND, uart->cr); + pci_conf_write16(sbdf, PCI_COMMAND, uart->cr); } #endif =20 @@ -1063,11 +1069,16 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_a= mt, unsigned int idx) uint32_t bar, bar_64 =3D 0, len, len_64; u64 size =3D 0; const struct ns16550_config_param *param =3D uart_param; + const pci_sbdf_t sbdf =3D { + .bus =3D b, + .dev =3D d, + .func =3D f, + }; =20 - nextf =3D (f || (pci_conf_read16(0, b, d, f, PCI_HEADER_TY= PE) & + nextf =3D (f || (pci_conf_read16(sbdf, PCI_HEADER_TYPE) & 0x80)) ? f + 1 : 8; =20 - switch ( pci_conf_read16(0, b, d, f, PCI_CLASS_DEVICE) ) + switch ( pci_conf_read16(sbdf, PCI_CLASS_DEVICE) ) { case 0x0700: /* single port serial */ case 0x0702: /* multi port serial */ @@ -1084,8 +1095,8 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt= , unsigned int idx) /* Check for params in uart_config lookup table */ for ( i =3D 0; i < ARRAY_SIZE(uart_config); i++ ) { - u16 vendor =3D pci_conf_read16(0, b, d, f, PCI_VENDOR_= ID); - u16 device =3D pci_conf_read16(0, b, d, f, PCI_DEVICE_= ID); + uint16_t vendor =3D pci_conf_read16(sbdf, PCI_VENDOR_I= D); + uint16_t device =3D pci_conf_read16(sbdf, PCI_DEVICE_I= D); =20 if ( uart_config[i].vendor_id =3D=3D vendor && uart_config[i].dev_id =3D=3D device ) @@ -1108,28 +1119,25 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_a= mt, unsigned int idx) } =20 uart->io_base =3D 0; - bar =3D pci_conf_read32(0, b, d, f, - PCI_BASE_ADDRESS_0 + bar_idx*4); + bar =3D pci_conf_read32(sbdf, PCI_BASE_ADDRESS_0 + bar_idx= *4); =20 /* MMIO based */ if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) { - pci_conf_write32(0, b, d, f, - PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); - len =3D pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0= + bar_idx*4); - pci_conf_write32(0, b, d, f, - PCI_BASE_ADDRESS_0 + bar_idx*4, bar); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + bar_idx*4,= ~0u); + len =3D pci_conf_read32(sbdf, PCI_BASE_ADDRESS_0 + bar= _idx*4); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + bar_idx*4,= bar); =20 /* Handle 64 bit BAR if found */ if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) { - bar_64 =3D pci_conf_read32(0, b, d, f, + bar_64 =3D pci_conf_read32(sbdf, PCI_BASE_ADDRESS_0 + (bar_idx+1)*4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0= u); - len_64 =3D pci_conf_read32(0, b, d, f, + len_64 =3D pci_conf_read32(sbdf, PCI_BASE_ADDRESS_0 + (bar_idx+1)*4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ba= r_64); size =3D ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_M= ASK; size &=3D ((u64)len_64 << 32) | len; @@ -1143,11 +1151,9 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_am= t, unsigned int idx) /* IO based */ else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO= ) ) { - pci_conf_write32(0, b, d, f, - PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); - len =3D pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0= ); - pci_conf_write32(0, b, d, f, - PCI_BASE_ADDRESS_0 + bar_idx*4, bar); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + bar_idx*4,= ~0u); + len =3D pci_conf_read32(sbdf, PCI_BASE_ADDRESS_0); + pci_conf_write32(sbdf, PCI_BASE_ADDRESS_0 + bar_idx*4,= bar); size =3D len & PCI_BASE_ADDRESS_IO_MASK; =20 uart->io_base =3D bar & ~PCI_BASE_ADDRESS_SPACE_IO; @@ -1188,8 +1194,8 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt= , unsigned int idx) uart->bar64 =3D bar_64; uart->io_size =3D max(8U << param->reg_shift, param->uart_offset); - uart->irq =3D pci_conf_read8(0, b, d, f, PCI_INTERRUPT_PIN= ) ? - pci_conf_read8(0, b, d, f, PCI_INTERRUPT_LINE) : 0; + uart->irq =3D pci_conf_read8(sbdf, PCI_INTERRUPT_PIN) ? + pci_conf_read8(sbdf, PCI_INTERRUPT_LINE) : 0; =20 return 0; } diff --git a/xen/drivers/passthrough/amd/iommu_detect.c b/xen/drivers/passt= hrough/amd/iommu_detect.c index 3c5d4de1a3..e8d8ec59bd 100644 --- a/xen/drivers/passthrough/amd/iommu_detect.c +++ b/xen/drivers/passthrough/amd/iommu_detect.c @@ -48,7 +48,8 @@ static int __init get_iommu_capabilities( { u8 type; =20 - iommu->cap.header =3D pci_conf_read32(seg, bus, dev, func, cap_ptr); + iommu->cap.header =3D pci_conf_read32(PCI_SBDF_T(seg, bus, dev, func), + cap_ptr); type =3D get_field_from_reg_u32(iommu->cap.header, PCI_CAP_TYPE_MASK, PCI_CAP_TYPE_SHIFT); =20 diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthr= ough/amd/iommu_init.c index 17f39552a9..fe0516f788 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -798,8 +798,7 @@ static bool_t __init set_iommu_interrupt_handler(struct= amd_iommu *iommu) PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf)); return 0; } - control =3D pci_conf_read16(iommu->seg, PCI_BUS(iommu->bdf), - PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf), + control =3D pci_conf_read16(iommu->msi.dev->sbdf, iommu->msi.msi_attrib.pos + PCI_MSI_FLAGS); iommu->msi.msi.nvec =3D 1; if ( is_mask_bit_support(control) ) @@ -835,6 +834,10 @@ static bool_t __init set_iommu_interrupt_handler(struc= t amd_iommu *iommu) static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) { u32 value; + const pci_sbdf_t sbdf =3D { + .seg =3D iommu->seg, + .bdf =3D iommu->bdf, + }; u8 bus =3D PCI_BUS(iommu->bdf); u8 dev =3D PCI_SLOT(iommu->bdf); u8 func =3D PCI_FUNC(iommu->bdf); @@ -844,22 +847,22 @@ static void amd_iommu_erratum_746_workaround(struct a= md_iommu *iommu) (boot_cpu_data.x86_model > 0x1f) ) return; =20 - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); - value =3D pci_conf_read32(iommu->seg, bus, dev, func, 0xf4); + pci_conf_write32(sbdf, 0xf0, 0x90); + value =3D pci_conf_read32(sbdf, 0xf4); =20 if ( value & (1 << 2) ) return; =20 /* Select NB indirect register 0x90 and enable writing */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90 | (1 << 8)); + pci_conf_write32(sbdf, 0xf0, 0x90 | (1 << 8)); =20 - pci_conf_write32(iommu->seg, bus, dev, func, 0xf4, value | (1 << 2)); + pci_conf_write32(sbdf, 0xf4, value | (1 << 2)); printk(XENLOG_INFO "AMD-Vi: Applying erratum 746 workaround for IOMMU at %04x:%02x= :%02x.%u\n", iommu->seg, bus, dev, func); =20 /* Clear the enable writing bit */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); + pci_conf_write32(sbdf, 0xf0, 0x90); } =20 static void enable_iommu(struct amd_iommu *iommu) @@ -1203,7 +1206,12 @@ static bool_t __init amd_sp5100_erratum28(void) =20 for (bus =3D 0; bus < 256; bus++) { - id =3D pci_conf_read32(0, bus, 0x14, 0, PCI_VENDOR_ID); + const pci_sbdf_t sbdf =3D { + .bus =3D bus, + .dev =3D 0x14, + }; + + id =3D pci_conf_read32(sbdf, PCI_VENDOR_ID); =20 vendor_id =3D id & 0xffff; dev_id =3D (id >> 16) & 0xffff; @@ -1212,7 +1220,7 @@ static bool_t __init amd_sp5100_erratum28(void) if (vendor_id !=3D 0x1002 || dev_id !=3D 0x4385) continue; =20 - byte =3D pci_conf_read8(0, bus, 0x14, 0, 0xad); + byte =3D pci_conf_read8(sbdf, 0xad); if ( (byte >> 3) & 1 ) { printk(XENLOG_WARNING "AMD-Vi: SP5100 erratum 28 detected, dis= abling IOMMU.\n" diff --git a/xen/drivers/passthrough/ats.h b/xen/drivers/passthrough/ats.h index bee13911c0..e83a45d16e 100644 --- a/xen/drivers/passthrough/ats.h +++ b/xen/drivers/passthrough/ats.h @@ -35,8 +35,8 @@ static inline int pci_ats_enabled(int seg, int bus, int d= evfn) pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); =20 - value =3D pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), - pos + ATS_REG_CTL); + value =3D pci_conf_read16(PCI_SBDF3_T(seg, bus, devfn), pos + ATS_REG_= CTL); + return value & ATS_ENABLE; } =20 diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 8de8d8e110..94fb3a183d 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -246,36 +246,34 @@ static void check_pdev(const struct pci_dev *pdev) =20 if ( command_mask ) { - val =3D pci_conf_read16(seg, bus, dev, func, PCI_COMMAND); + val =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); if ( val & command_mask ) - pci_conf_write16(seg, bus, dev, func, PCI_COMMAND, - val & ~command_mask); - val =3D pci_conf_read16(seg, bus, dev, func, PCI_STATUS); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, val & ~command_mask); + val =3D pci_conf_read16(pdev->sbdf, PCI_STATUS); if ( val & PCI_STATUS_CHECK ) { printk(XENLOG_INFO "%04x:%02x:%02x.%u status %04x -> %04x\n", seg, bus, dev, func, val, val & ~PCI_STATUS_CHECK); - pci_conf_write16(seg, bus, dev, func, PCI_STATUS, - val & PCI_STATUS_CHECK); + pci_conf_write16(pdev->sbdf, PCI_STATUS, val & PCI_STATUS_CHEC= K); } } =20 - switch ( pci_conf_read8(seg, bus, dev, func, PCI_HEADER_TYPE) & 0x7f ) + switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f ) { case PCI_HEADER_TYPE_BRIDGE: if ( !bridge_ctl_mask ) break; - val =3D pci_conf_read16(seg, bus, dev, func, PCI_BRIDGE_CONTROL); + val =3D pci_conf_read16(pdev->sbdf, PCI_BRIDGE_CONTROL); if ( val & bridge_ctl_mask ) - pci_conf_write16(seg, bus, dev, func, PCI_BRIDGE_CONTROL, + pci_conf_write16(pdev->sbdf, PCI_BRIDGE_CONTROL, val & ~bridge_ctl_mask); - val =3D pci_conf_read16(seg, bus, dev, func, PCI_SEC_STATUS); + val =3D pci_conf_read16(pdev->sbdf, PCI_SEC_STATUS); if ( val & PCI_STATUS_CHECK ) { printk(XENLOG_INFO "%04x:%02x:%02x.%u secondary status %04x -> %04x\n", seg, bus, dev, func, val, val & ~PCI_STATUS_CHECK); - pci_conf_write16(seg, bus, dev, func, PCI_SEC_STATUS, + pci_conf_write16(pdev->sbdf, PCI_SEC_STATUS, val & PCI_STATUS_CHECK); } break; @@ -289,12 +287,8 @@ static void check_pdev(const struct pci_dev *pdev) =20 static void apply_quirks(struct pci_dev *pdev) { - uint16_t vendor =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, - pdev->sbdf.dev, pdev->sbdf.func, - PCI_VENDOR_ID); - uint16_t device =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, - pdev->sbdf.dev, pdev->sbdf.func, - PCI_DEVICE_ID); + uint16_t vendor =3D pci_conf_read16(pdev->sbdf, PCI_VENDOR_ID); + uint16_t device =3D pci_conf_read16(pdev->sbdf, PCI_DEVICE_ID); static const struct { uint16_t vendor, device; } ignore_bars[] =3D { @@ -368,10 +362,8 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg= , u8 bus, u8 devfn) =20 case DEV_TYPE_PCIe2PCI_BRIDGE: case DEV_TYPE_LEGACY_PCI_BRIDGE: - sec_bus =3D pci_conf_read8(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_SECONDARY_BUS); - sub_bus =3D pci_conf_read8(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_SUBORDINATE_BUS); + sec_bus =3D pci_conf_read8(pdev->sbdf, PCI_SECONDARY_BUS); + sub_bus =3D pci_conf_read8(pdev->sbdf, PCI_SUBORDINATE_BUS); =20 spin_lock(&pseg->bus2bridge_lock); for ( ; sec_bus <=3D sub_bus; sec_bus++ ) @@ -387,8 +379,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg,= u8 bus, u8 devfn) pos =3D pci_find_cap_offset(pseg->nr, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), PCI_CAP_ID_EXP); BUG_ON(!pos); - cap =3D pci_conf_read16(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), pos + PCI_EXP_DEVCAP); + cap =3D pci_conf_read16(pdev->sbdf, pos + PCI_EXP_DEVCAP); if ( cap & PCI_EXP_DEVCAP_PHANTOM ) { pdev->phantom_stride =3D 8 >> MASK_EXTR(cap, @@ -438,10 +429,8 @@ static void free_pdev(struct pci_seg *pseg, struct pci= _dev *pdev) =20 case DEV_TYPE_PCIe2PCI_BRIDGE: case DEV_TYPE_LEGACY_PCI_BRIDGE: - sec_bus =3D pci_conf_read8(pseg->nr, pdev->sbdf.bus, pdev->sbd= f.dev, - pdev->sbdf.func, PCI_SECONDARY_BUS); - sub_bus =3D pci_conf_read8(pseg->nr, pdev->sbdf.bus, pdev->sbd= f.dev, - pdev->sbdf.func, PCI_SUBORDINATE_BUS); + sec_bus =3D pci_conf_read8(pdev->sbdf, PCI_SECONDARY_BUS); + sub_bus =3D pci_conf_read8(pdev->sbdf, PCI_SUBORDINATE_BUS); =20 spin_lock(&pseg->bus2bridge_lock); for ( ; sec_bus <=3D sub_bus; sec_bus++ ) @@ -603,8 +592,6 @@ static void pci_enable_acs(struct pci_dev *pdev) int pos; uint16_t cap, ctrl, seg =3D pdev->sbdf.seg; uint8_t bus =3D pdev->sbdf.bus; - uint8_t dev =3D pdev->sbdf.dev; - uint8_t func =3D pdev->sbdf.func; =20 if ( !iommu_enabled ) return; @@ -613,8 +600,8 @@ static void pci_enable_acs(struct pci_dev *pdev) if (!pos) return; =20 - cap =3D pci_conf_read16(seg, bus, dev, func, pos + PCI_ACS_CAP); - ctrl =3D pci_conf_read16(seg, bus, dev, func, pos + PCI_ACS_CTRL); + cap =3D pci_conf_read16(pdev->sbdf, pos + PCI_ACS_CAP); + ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_ACS_CTRL); =20 /* Source Validation */ ctrl |=3D (cap & PCI_ACS_SV); @@ -628,7 +615,7 @@ static void pci_enable_acs(struct pci_dev *pdev) /* Upstream Forwarding */ ctrl |=3D (cap & PCI_ACS_UF); =20 - pci_conf_write16(seg, bus, dev, func, pos + PCI_ACS_CTRL, ctrl); + pci_conf_write16(pdev->sbdf, pos + PCI_ACS_CTRL, ctrl); } =20 static int iommu_add_device(struct pci_dev *pdev); @@ -639,8 +626,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned= int pos, uint64_t *paddr, uint64_t *psize, unsigned int flags) { - uint32_t hi =3D 0, bar =3D pci_conf_read32(sbdf.seg, sbdf.bus, sbdf.de= v, - sbdf.func, pos); + uint32_t hi =3D 0, bar =3D pci_conf_read32(sbdf, pos); uint64_t size; bool is64bits =3D !(flags & PCI_BAR_ROM) && (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_MEM= _TYPE_64; @@ -650,7 +636,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned= int pos, ASSERT(!((flags & PCI_BAR_VF) && (flags & PCI_BAR_ROM))); ASSERT((flags & PCI_BAR_ROM) || (bar & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_ME= MORY); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, pos, ~0); + pci_conf_write32(sbdf, pos, ~0); if ( is64bits ) { if ( flags & PCI_BAR_LAST ) @@ -662,20 +648,18 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsign= ed int pos, *psize =3D 0; return 1; } - hi =3D pci_conf_read32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, po= s + 4); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, pos + 4,= ~0); + hi =3D pci_conf_read32(sbdf, pos + 4); + pci_conf_write32(sbdf, pos + 4, ~0); } - size =3D pci_conf_read32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, - pos) & mask; + size =3D pci_conf_read32(sbdf, pos) & mask; if ( is64bits ) { - size |=3D (uint64_t)pci_conf_read32(sbdf.seg, sbdf.bus, sbdf.dev, - sbdf.func, pos + 4) << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, pos + 4,= hi); + size |=3D (uint64_t)pci_conf_read32(sbdf, pos + 4) << 32; + pci_conf_write32(sbdf, pos + 4, hi); } else if ( size ) size |=3D (uint64_t)~0 << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, pos, bar); + pci_conf_write32(sbdf, pos, bar); size =3D -size; =20 if ( paddr ) @@ -745,7 +729,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, { unsigned int pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_SRIOV); - u16 ctrl =3D pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV= _CTRL); + u16 ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL); =20 if ( !pos ) /* Nothing */; @@ -757,10 +741,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, for ( i =3D 0; i < PCI_SRIOV_NUM_BARS; ) { unsigned int idx =3D pos + PCI_SRIOV_BAR + i * 4; - u32 bar =3D pci_conf_read32(seg, bus, slot, func, idx); - pci_sbdf_t sbdf =3D { - .sbdf =3D PCI_SBDF3(seg, bus, devfn), - }; + uint32_t bar =3D pci_conf_read32(pdev->sbdf, idx); =20 if ( (bar & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO ) @@ -771,7 +752,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, seg, bus, slot, func, i); continue; } - ret =3D pci_size_mem_bar(sbdf, idx, NULL, &pdev->vf_rlen[i= ], + ret =3D pci_size_mem_bar(pdev->sbdf, idx, NULL, &pdev->vf_= rlen[i], PCI_BAR_VF | ((i =3D=3D PCI_SRIOV_NUM_BARS - 1) ? PCI_BAR_LAST : 0)); @@ -940,14 +921,20 @@ enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn) u16 class_device, creg; u8 d =3D PCI_SLOT(devfn), f =3D PCI_FUNC(devfn); int pos =3D pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP); + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .dev =3D d, + .func =3D f, + }; =20 - class_device =3D pci_conf_read16(seg, bus, d, f, PCI_CLASS_DEVICE); + class_device =3D pci_conf_read16(sbdf, PCI_CLASS_DEVICE); switch ( class_device ) { case PCI_CLASS_BRIDGE_PCI: if ( !pos ) return DEV_TYPE_LEGACY_PCI_BRIDGE; - creg =3D pci_conf_read16(seg, bus, d, f, pos + PCI_EXP_FLAGS); + creg =3D pci_conf_read16(sbdf, pos + PCI_EXP_FLAGS); switch ( (creg & PCI_EXP_FLAGS_TYPE) >> 4 ) { case PCI_EXP_TYPE_PCI_BRIDGE: @@ -1011,7 +998,7 @@ bool_t __init pci_device_detect(u16 seg, u8 bus, u8 de= v, u8 func) { u32 vendor; =20 - vendor =3D pci_conf_read32(seg, bus, dev, func, PCI_VENDOR_ID); + vendor =3D pci_conf_read32(PCI_SBDF_T(seg, bus, dev, func), PCI_VENDOR= _ID); /* some broken boards return 0 or ~0 if a slot is empty: */ if ( (vendor =3D=3D 0xffffffff) || (vendor =3D=3D 0x00000000) || (vendor =3D=3D 0x0000ffff) || (vendor =3D=3D 0xffff0000) ) @@ -1043,10 +1030,8 @@ void pci_check_disable_device(u16 seg, u8 bus, u8 de= vfn) =20 /* Tell the device to stop DMAing; we can't rely on the guest to * control it for us. */ - cword =3D pci_conf_read16(seg, bus, pdev->sbdf.dev, pdev->sbdf.func, - PCI_COMMAND); - pci_conf_write16(seg, bus, pdev->sbdf.dev, pdev->sbdf.func, - PCI_COMMAND, cword & ~PCI_COMMAND_MASTER); + cword =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cword & ~PCI_COMMAND_MASTER); } =20 /* @@ -1079,7 +1064,7 @@ static int __init _scan_pci_devices(struct pci_seg *p= seg, void *arg) return -ENOMEM; } =20 - if ( !func && !(pci_conf_read8(pseg->nr, bus, dev, func, + if ( !func && !(pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x80) ) break; } @@ -1210,9 +1195,7 @@ static bool_t hest_match_type(const struct acpi_hest_= header *hest_hdr, unsigned int pos =3D pci_find_cap_offset(pdev->sbdf.seg, pdev->sbdf.bu= s, pdev->sbdf.dev, pdev->sbdf.func, PCI_CAP_ID_EXP); - uint8_t pcie =3D MASK_EXTR(pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.= bus, - pdev->sbdf.dev, pdev->sbdf.fu= nc, - pos + PCI_EXP_FLAGS), + uint8_t pcie =3D MASK_EXTR(pci_conf_read16(pdev->sbdf, pos + PCI_EXP_F= LAGS), PCI_EXP_FLAGS_TYPE); =20 switch ( hest_hdr->type ) @@ -1222,8 +1205,7 @@ static bool_t hest_match_type(const struct acpi_hest_= header *hest_hdr, case ACPI_HEST_TYPE_AER_ENDPOINT: return pcie =3D=3D PCI_EXP_TYPE_ENDPOINT; case ACPI_HEST_TYPE_AER_BRIDGE: - return pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.= dev, - pdev->sbdf.func, PCI_CLASS_DEVICE) =3D=3D + return pci_conf_read16(pdev->sbdf, PCI_CLASS_DEVICE) =3D=3D PCI_CLASS_BRIDGE_PCI; } =20 diff --git a/xen/drivers/passthrough/vtd/dmar.c b/xen/drivers/passthrough/v= td/dmar.c index effaf93222..9d30188ab9 100644 --- a/xen/drivers/passthrough/vtd/dmar.c +++ b/xen/drivers/passthrough/vtd/dmar.c @@ -348,7 +348,7 @@ static int __init acpi_parse_dev_scope( =20 while ( --depth > 0 ) { - bus =3D pci_conf_read8(seg, bus, path->dev, path->fn, + bus =3D pci_conf_read8(PCI_SBDF_T(seg, bus, path->dev, path->f= n), PCI_SECONDARY_BUS); path++; } @@ -356,10 +356,16 @@ static int __init acpi_parse_dev_scope( switch ( acpi_scope->entry_type ) { case ACPI_DMAR_SCOPE_TYPE_BRIDGE: - sec_bus =3D pci_conf_read8(seg, bus, path->dev, path->fn, - PCI_SECONDARY_BUS); - sub_bus =3D pci_conf_read8(seg, bus, path->dev, path->fn, - PCI_SUBORDINATE_BUS); + { + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .dev =3D path->dev, + .func =3D path->fn, + }; + + sec_bus =3D pci_conf_read8(sbdf, PCI_SECONDARY_BUS); + sub_bus =3D pci_conf_read8(sbdf, PCI_SUBORDINATE_BUS); if ( iommu_verbose ) printk(VTDPREFIX " bridge: %04x:%02x:%02x.%u start=3D%x sec=3D%x sub= =3D%x\n", @@ -368,7 +374,7 @@ static int __init acpi_parse_dev_scope( =20 dmar_scope_add_buses(scope, sec_bus, sub_bus); break; - + } case ACPI_DMAR_SCOPE_TYPE_HPET: if ( iommu_verbose ) printk(VTDPREFIX " MSI HPET: %04x:%02x:%02x.%u\n", diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough= /vtd/quirks.c index fa811605ee..48c7384b82 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -61,6 +61,14 @@ static bool_t __read_mostly is_snb_gfx; static u8 *__read_mostly igd_reg_va; static spinlock_t igd_lock; =20 +static const pci_sbdf_t igd_sbdf =3D { + .dev =3D IGD_DEV, +}; + +static const pci_sbdf_t ioh_sbdf =3D { + .dev =3D IOH_DEV, +}; + /* * QUIRK to workaround Xen boot issue on Calpella/Ironlake OEM BIOS * not enabling VT-d properly in IGD. The workaround is to not enabling @@ -74,7 +82,7 @@ int is_igd_vt_enabled_quirk(void) return 1; =20 /* integrated graphics on Intel platforms is located at 0:2.0 */ - ggc =3D pci_conf_read16(0, 0, IGD_DEV, 0, GGC); + ggc =3D pci_conf_read16(igd_sbdf, GGC); return ( ggc & GGC_MEMORY_VT_ENABLED ? 1 : 0 ); } =20 @@ -88,12 +96,12 @@ static void __init cantiga_b3_errata_init(void) u16 vid; u8 did_hi, rid; =20 - vid =3D pci_conf_read16(0, 0, IGD_DEV, 0, 0); + vid =3D pci_conf_read16(igd_sbdf, 0); if ( vid !=3D 0x8086 ) return; =20 - did_hi =3D pci_conf_read8(0, 0, IGD_DEV, 0, 3); - rid =3D pci_conf_read8(0, 0, IGD_DEV, 0, 8); + did_hi =3D pci_conf_read8(igd_sbdf, 3); + rid =3D pci_conf_read8(igd_sbdf, 8); =20 if ( (did_hi =3D=3D 0x2A) && (rid =3D=3D 0x7) ) is_cantiga_b3 =3D 1; @@ -128,9 +136,9 @@ static void __init map_igd_reg(void) if ( igd_reg_va ) return; =20 - igd_mmio =3D pci_conf_read32(0, 0, IGD_DEV, 0, PCI_BASE_ADDRESS_1); + igd_mmio =3D pci_conf_read32(igd_sbdf, PCI_BASE_ADDRESS_1); igd_mmio <<=3D 32; - igd_mmio +=3D pci_conf_read32(0, 0, IGD_DEV, 0, PCI_BASE_ADDRESS_0); + igd_mmio +=3D pci_conf_read32(igd_sbdf, PCI_BASE_ADDRESS_0); igd_reg_va =3D ioremap(igd_mmio & IGD_BAR_MASK, 0x3000); } =20 @@ -279,9 +287,14 @@ static void __init tylersburg_intremap_quirk(void) =20 for ( bus =3D 0; bus < 0x100; bus++ ) { + const pci_sbdf_t sbdf =3D { + .bus =3D bus, + .dev =3D 20, + }; + /* Match on System Management Registers on Device 20 Function 0 */ - device =3D pci_conf_read32(0, bus, 20, 0, PCI_VENDOR_ID); - rev =3D pci_conf_read8(0, bus, 20, 0, PCI_REVISION_ID); + device =3D pci_conf_read32(sbdf, PCI_VENDOR_ID); + rev =3D pci_conf_read8(sbdf, PCI_REVISION_ID); =20 if ( rev =3D=3D 0x13 && device =3D=3D 0x342e8086 ) { @@ -296,8 +309,8 @@ static void __init tylersburg_intremap_quirk(void) /* initialize platform identification flags */ void __init platform_quirks_init(void) { - ioh_id =3D pci_conf_read32(0, 0, IOH_DEV, 0, 0); - igd_id =3D pci_conf_read32(0, 0, IGD_DEV, 0, 0); + ioh_id =3D pci_conf_read32(ioh_sbdf, 0); + igd_id =3D pci_conf_read32(igd_sbdf, 0); =20 /* Mobile 4 Series Chipset neglects to set RWBF capability. */ if ( ioh_id =3D=3D 0x2a408086 ) @@ -356,15 +369,15 @@ int me_wifi_quirk(struct domain *domain, u8 bus, u8 d= evfn, int map) u32 id; int rc =3D 0; =20 - id =3D pci_conf_read32(0, 0, 0, 0, 0); + id =3D pci_conf_read32(PCI_SBDF_T(0, 0, 0, 0), 0); if ( IS_CTG(id) ) { /* quit if ME does not exist */ - if ( pci_conf_read32(0, 0, 3, 0, 0) =3D=3D 0xffffffff ) + if ( pci_conf_read32(PCI_SBDF_T(0, 0, 3, 0), 0) =3D=3D 0xffffffff ) return 0; =20 /* if device is WLAN device, map ME phantom device 0:3.7 */ - id =3D pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0= ); + id =3D pci_conf_read32(PCI_SBDF3_T(0, bus, devfn), 0); switch (id) { case 0x42328086: @@ -384,11 +397,11 @@ int me_wifi_quirk(struct domain *domain, u8 bus, u8 d= evfn, int map) else if ( IS_ILK(id) || IS_CPT(id) ) { /* quit if ME does not exist */ - if ( pci_conf_read32(0, 0, 22, 0, 0) =3D=3D 0xffffffff ) + if ( pci_conf_read32(PCI_SBDF_T(0, 0, 22, 0), 0) =3D=3D 0xffffffff= ) return 0; =20 /* if device is WLAN device, map ME phantom device 0:22.7 */ - id =3D pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0= ); + id =3D pci_conf_read32(PCI_SBDF3_T(0, bus, devfn), 0); switch (id) { case 0x00878086: /* Kilmer Peak */ @@ -424,11 +437,11 @@ void pci_vtd_quirk(const struct pci_dev *pdev) paddr_t pa; const char *action; =20 - if ( pci_conf_read16(seg, bus, dev, func, PCI_VENDOR_ID) !=3D + if ( pci_conf_read16(pdev->sbdf, PCI_VENDOR_ID) !=3D PCI_VENDOR_ID_INTEL ) return; =20 - switch ( pci_conf_read16(seg, bus, dev, func, PCI_DEVICE_ID) ) + switch ( pci_conf_read16(pdev->sbdf, PCI_DEVICE_ID) ) { /* * Mask reporting Intel VT-d faults to IOH core logic: @@ -439,8 +452,8 @@ void pci_vtd_quirk(const struct pci_dev *pdev) case 0x342e: /* Tylersburg chipset (Nehalem / Westmere systems) */ case 0x3728: /* Xeon C5500/C3500 (JasperForest) */ case 0x3c28: /* Sandybridge */ - val =3D pci_conf_read32(seg, bus, dev, func, 0x1AC); - pci_conf_write32(seg, bus, dev, func, 0x1AC, val | (1 << 31)); + val =3D pci_conf_read32(pdev->sbdf, 0x1AC); + pci_conf_write32(pdev->sbdf, 0x1AC, val | (1 << 31)); printk(XENLOG_INFO "Masked VT-d error signaling on %04x:%02x:%02x.= %u\n", seg, bus, dev, func); break; @@ -462,7 +475,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) PCI_EXT_CAP_ID_VNDR); while ( pos ) { - val =3D pci_conf_read32(seg, bus, dev, func, pos + PCI_VND= R_HEADER); + val =3D pci_conf_read32(pdev->sbdf, pos + PCI_VNDR_HEADER); if ( PCI_VNDR_HEADER_ID(val) =3D=3D 4 && PCI_VNDR_HEADER_R= EV(val) =3D=3D 1 ) { pos +=3D PCI_VNDR_HEADER; @@ -482,15 +495,15 @@ void pci_vtd_quirk(const struct pci_dev *pdev) break; } =20 - val =3D pci_conf_read32(seg, bus, dev, func, pos + PCI_ERR_UNCOR_M= ASK); - val2 =3D pci_conf_read32(seg, bus, dev, func, pos + PCI_ERR_COR_MA= SK); + val =3D pci_conf_read32(pdev->sbdf, pos + PCI_ERR_UNCOR_MASK); + val2 =3D pci_conf_read32(pdev->sbdf, pos + PCI_ERR_COR_MASK); if ( (val & PCI_ERR_UNC_UNSUP) && (val2 & PCI_ERR_COR_ADV_NFAT) ) action =3D "Found masked"; else if ( !ff ) { - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_UNCOR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_UNCOR_MASK, val | PCI_ERR_UNC_UNSUP); - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_COR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_COR_MASK, val2 | PCI_ERR_COR_ADV_NFAT); action =3D "Masked"; } @@ -498,8 +511,8 @@ void pci_vtd_quirk(const struct pci_dev *pdev) action =3D "Must not mask"; =20 /* XPUNCERRMSK Send Completion with Unsupported Request */ - val =3D pci_conf_read32(seg, bus, dev, func, 0x20c); - pci_conf_write32(seg, bus, dev, func, 0x20c, val | (1 << 4)); + val =3D pci_conf_read32(pdev->sbdf, 0x20c); + pci_conf_write32(pdev->sbdf, 0x20c, val | (1 << 4)); =20 printk(XENLOG_INFO "%s UR signaling on %04x:%02x:%02x.%u\n", action, seg, bus, dev, func); @@ -515,8 +528,8 @@ void pci_vtd_quirk(const struct pci_dev *pdev) case 0x1610: case 0x1614: case 0x1618: /* Broadwell */ case 0x1900: case 0x1904: case 0x1908: case 0x190c: case 0x190f: /* Sk= ylake */ case 0x1910: case 0x1918: case 0x191f: /* Skylake */ - bar =3D pci_conf_read32(seg, bus, dev, func, 0x6c); - bar =3D (bar << 32) | pci_conf_read32(seg, bus, dev, func, 0x68); + bar =3D pci_conf_read32(pdev->sbdf, 0x6c); + bar =3D (bar << 32) | pci_conf_read32(pdev->sbdf, 0x68); pa =3D bar & 0x7ffffff000UL; /* bits 12...38 */ if ( (bar & 1) && pa && page_is_ram_type(paddr_to_pfn(pa), RAM_TYPE_RESERVED) ) diff --git a/xen/drivers/passthrough/x86/ats.c b/xen/drivers/passthrough/x8= 6/ats.c index ddaec72d19..c3203793a6 100644 --- a/xen/drivers/passthrough/x86/ats.c +++ b/xen/drivers/passthrough/x86/ats.c @@ -34,8 +34,7 @@ int enable_ats_device(struct pci_dev *pdev, struct list_h= ead *ats_list) dprintk(XENLOG_INFO, "%04x:%02x:%02x.%u: ATS capability found\n", seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); =20 - value =3D pci_conf_read16(seg, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), pos + ATS_REG_CTL); + value =3D pci_conf_read16(pdev->sbdf, pos + ATS_REG_CTL); if ( value & ATS_ENABLE ) { struct pci_dev *other; @@ -51,15 +50,13 @@ int enable_ats_device(struct pci_dev *pdev, struct list= _head *ats_list) if ( !(value & ATS_ENABLE) ) { value |=3D ATS_ENABLE; - pci_conf_write16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), - pos + ATS_REG_CTL, value); + pci_conf_write16(pdev->sbdf, pos + ATS_REG_CTL, value); } =20 if ( pos ) { pdev->ats.cap_pos =3D pos; - value =3D pci_conf_read16(seg, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), pos + ATS_REG_CAP); + value =3D pci_conf_read16(pdev->sbdf, pos + ATS_REG_CAP); pdev->ats.queue_depth =3D value & ATS_QUEUE_DEPTH_MASK ?: ATS_QUEUE_DEPTH_MASK + 1; list_add(&pdev->ats.list, ats_list); @@ -81,11 +78,9 @@ void disable_ats_device(struct pci_dev *pdev) =20 BUG_ON(!pdev->ats.cap_pos); =20 - value =3D pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), - pdev->ats.cap_pos + ATS_REG_CTL); + value =3D pci_conf_read16(pdev->sbdf, pdev->ats.cap_pos + ATS_REG_CTL); value &=3D ~ATS_ENABLE; - pci_conf_write16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), - pdev->ats.cap_pos + ATS_REG_CTL, value); + pci_conf_write16(pdev->sbdf, pdev->ats.cap_pos + ATS_REG_CTL, value); =20 list_del(&pdev->ats.list); =20 diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index a3223a2b29..3d2acf6f77 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -14,19 +14,25 @@ int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 fun= c, u8 cap) int max_cap =3D 48; u8 pos =3D PCI_CAPABILITY_LIST; u16 status; - - status =3D pci_conf_read16(seg, bus, dev, func, PCI_STATUS); + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .dev =3D dev, + .func =3D func, + }; + + status =3D pci_conf_read16(sbdf, PCI_STATUS); if ( (status & PCI_STATUS_CAP_LIST) =3D=3D 0 ) return 0; =20 while ( max_cap-- ) { - pos =3D pci_conf_read8(seg, bus, dev, func, pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(seg, bus, dev, func, pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -43,16 +49,20 @@ int pci_find_next_cap(u16 seg, u8 bus, unsigned int dev= fn, u8 pos, int cap) { u8 id; int ttl =3D 48; + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .extfunc =3D devfn, + }; =20 while ( ttl-- ) { - pos =3D pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn),= pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), - pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -90,11 +100,14 @@ int pci_find_ext_capability(int seg, int bus, int devf= n, int cap) */ int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, i= nt cap) { - u32 header; int ttl =3D 480; /* 3840 bytes, minimum 8 bytes per capability */ int pos =3D max(start, 0x100); - - header =3D pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn),= pos); + const pci_sbdf_t sbdf =3D { + .seg =3D seg, + .bus =3D bus, + .extfunc =3D devfn, + }; + uint32_t header =3D pci_conf_read32(sbdf, pos); =20 /* * If we have no capabilities, this is indicated by cap ID, @@ -110,24 +123,20 @@ int pci_find_next_ext_capability(int seg, int bus, in= t devfn, int start, int cap pos =3D PCI_EXT_CAP_NEXT(header); if ( pos < 0x100 ) break; - header =3D pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(dev= fn), pos); + header =3D pci_conf_read32(sbdf, pos); } return 0; } =20 void pci_intx(const struct pci_dev *pdev, bool enable) { - uint16_t seg =3D pdev->sbdf.seg; - uint8_t bus =3D pdev->sbdf.bus; - uint8_t slot =3D pdev->sbdf.dev; - uint8_t func =3D pdev->sbdf.func; - uint16_t cmd =3D pci_conf_read16(seg, bus, slot, func, PCI_COMMAND); + uint16_t cmd =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); =20 if ( enable ) cmd &=3D ~PCI_COMMAND_INTX_DISABLE; else cmd |=3D PCI_COMMAND_INTX_DISABLE; - pci_conf_write16(seg, bus, slot, func, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); } =20 const char *__init parse_pci(const char *s, unsigned int *seg_p, diff --git a/xen/drivers/video/vga.c b/xen/drivers/video/vga.c index 6a64fd9013..59f9c9de6f 100644 --- a/xen/drivers/video/vga.c +++ b/xen/drivers/video/vga.c @@ -121,10 +121,8 @@ void __init video_endboot(void) pcidevs_unlock(); =20 if ( !pdev || - pci_conf_read16(0, bus, PCI_SLOT(devfn), PCI_FUNC(dev= fn), - PCI_CLASS_DEVICE) !=3D 0x0300 || - !(pci_conf_read16(0, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_COMMAND) & + pci_conf_read16(pdev->sbdf, PCI_CLASS_DEVICE) !=3D 0x= 0300 || + !(pci_conf_read16(pdev->sbdf, PCI_COMMAND) & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) ) continue; =20 @@ -136,21 +134,24 @@ void __init video_endboot(void) b =3D 0; break; case 1: - switch ( pci_conf_read8(0, b, PCI_SLOT(df), - PCI_FUNC(df), - PCI_HEADER_TYPE) ) + { + const pci_sbdf_t sbdf =3D { + .bus =3D b, + .extfunc =3D df, + }; + + switch ( pci_conf_read8(sbdf, PCI_HEADER_TYPE) ) { case PCI_HEADER_TYPE_BRIDGE: case PCI_HEADER_TYPE_CARDBUS: - if ( pci_conf_read16(0, b, PCI_SLOT(df), - PCI_FUNC(df), - PCI_BRIDGE_CONTROL) & + if ( pci_conf_read16(sbdf, PCI_BRIDGE_CONTROL)= & PCI_BRIDGE_CTL_VGA ) continue; break; } break; } + } break; } if ( !b ) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 74d70a4278..d693b1376c 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -112,8 +112,7 @@ static void modify_decoding(const struct pci_dev *pdev,= uint16_t cmd, (map ? PCI_ROM_ADDRESS_ENABLE : 0); =20 header->bars[i].enabled =3D header->rom_enabled =3D map; - pci_conf_write32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.de= v, - pdev->sbdf.func, rom_pos, val); + pci_conf_write32(pdev->sbdf, rom_pos, val); return; } =20 @@ -123,8 +122,7 @@ static void modify_decoding(const struct pci_dev *pdev,= uint16_t cmd, } =20 if ( !rom_only ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); else ASSERT_UNREACHABLE(); } @@ -335,9 +333,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) static void cmd_write(const struct pci_dev *pdev, unsigned int reg, uint32_t cmd, void *data) { - uint16_t current_cmd =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bu= s, - pdev->sbdf.dev, pdev->sbdf.func, - reg); + uint16_t current_cmd =3D pci_conf_read16(pdev->sbdf, reg); =20 /* * Let Dom0 play with all the bits directly except for the memory @@ -352,8 +348,7 @@ static void cmd_write(const struct pci_dev *pdev, unsig= ned int reg, */ modify_bars(pdev, cmd, false); else - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg, cmd); + pci_conf_write16(pdev->sbdf, reg, cmd); } =20 static void bar_write(const struct pci_dev *pdev, unsigned int reg, @@ -371,8 +366,7 @@ static void bar_write(const struct pci_dev *pdev, unsig= ned int reg, else val &=3D PCI_BASE_ADDRESS_MEM_MASK; =20 - if ( pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, PCI_COMMAND) & PCI_COMMAND_MEMOR= Y ) + if ( pci_conf_read16(pdev->sbdf, PCI_COMMAND) & PCI_COMMAND_MEMORY ) { /* If the value written is the current one avoid printing a warnin= g. */ if ( val !=3D (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) @@ -399,8 +393,7 @@ static void bar_write(const struct pci_dev *pdev, unsig= ned int reg, val |=3D bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0; } =20 - pci_conf_write32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } =20 static void rom_write(const struct pci_dev *pdev, unsigned int reg, @@ -408,9 +401,7 @@ static void rom_write(const struct pci_dev *pdev, unsig= ned int reg, { struct vpci_header *header =3D &pdev->vpci->header; struct vpci_bar *rom =3D data; - uint16_t cmd =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, - pdev->sbdf.dev, pdev->sbdf.func, - PCI_COMMAND); + uint16_t cmd =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); bool new_enabled =3D val & PCI_ROM_ADDRESS_ENABLE; =20 if ( (cmd & PCI_COMMAND_MEMORY) && header->rom_enabled && new_enabled ) @@ -433,8 +424,7 @@ static void rom_write(const struct pci_dev *pdev, unsig= ned int reg, { /* Just update the ROM BAR field. */ header->rom_enabled =3D new_enabled; - pci_conf_write32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } /* * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note th= at @@ -464,8 +454,7 @@ static int init_bars(struct pci_dev *pdev) struct vpci_bar *bars =3D header->bars; int rc; =20 - switch ( pci_conf_read8(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, PCI_HEADER_TYPE) & 0x7f ) + switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f ) { case PCI_HEADER_TYPE_NORMAL: num_bars =3D PCI_HEADER_NORMAL_NR_BARS; @@ -491,12 +480,9 @@ static int init_bars(struct pci_dev *pdev) return 0; =20 /* Disable memory decoding before sizing. */ - cmd =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, PCI_COMMAND); + cmd =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); if ( cmd & PCI_COMMAND_MEMORY ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, PCI_COMMAND, - cmd & ~PCI_COMMAND_MEMORY); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMOR= Y); =20 for ( i =3D 0; i < num_bars; i++ ) { @@ -510,16 +496,14 @@ static int init_bars(struct pci_dev *pdev) 4, &bars[i]); if ( rc ) { - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbd= f.dev, - pdev->sbdf.func, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); return rc; } =20 continue; } =20 - val =3D pci_conf_read32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf= .dev, - pdev->sbdf.func, reg); + val =3D pci_conf_read32(pdev->sbdf, reg); if ( (val & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_= IO ) { bars[i].type =3D VPCI_BAR_IO; @@ -535,8 +519,7 @@ static int init_bars(struct pci_dev *pdev) (i =3D=3D num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) { - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.de= v, - pdev->sbdf.func, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); return rc; } =20 @@ -554,8 +537,7 @@ static int init_bars(struct pci_dev *pdev) &bars[i]); if ( rc ) { - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.de= v, - pdev->sbdf.func, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); return rc; } } @@ -569,9 +551,8 @@ static int init_bars(struct pci_dev *pdev) rom->type =3D VPCI_BAR_ROM; rom->size =3D size; rom->addr =3D addr; - header->rom_enabled =3D pci_conf_read32(pdev->sbdf.seg, pdev->sbdf= .bus, - pdev->sbdf.dev, pdev->sbdf.f= unc, - rom_reg) & PCI_ROM_ADDRESS_E= NABLE; + header->rom_enabled =3D pci_conf_read32(pdev->sbdf, rom_reg) & + PCI_ROM_ADDRESS_ENABLE; =20 rc =3D vpci_add_register(pdev->vpci, vpci_hw_read32, rom_write, ro= m_reg, 4, rom); diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index dfc894dcc6..4f2e55f3fd 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -77,8 +77,7 @@ static void control_write(const struct pci_dev *pdev, uns= igned int reg, msi->vectors =3D vectors; msi->enabled =3D new_enabled; =20 - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg, control_read(pdev, reg, data)); + pci_conf_write16(pdev->sbdf, reg, control_read(pdev, reg, data)); } =20 static void update_msi(const struct pci_dev *pdev, struct vpci_msi *msi) @@ -210,8 +209,7 @@ static int init_msi(struct pci_dev *pdev) return ret; =20 /* Get the maximum number of vectors the device supports. */ - control =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf= .dev, - pdev->sbdf.func, msi_control_reg(pos)); + control =3D pci_conf_read16(pdev->sbdf, msi_control_reg(pos)); =20 /* * FIXME: I've only been able to test this code with devices using a s= ingle diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 04431715f5..47d569121f 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -147,8 +147,7 @@ static void control_write(const struct pci_dev *pdev, u= nsigned int reg, =20 val =3D control_read(pdev, reg, data); if ( pci_msi_conf_write_intercept(msix->pdev, reg, 2, &val) >=3D 0 ) - pci_conf_write16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg, val); + pci_conf_write16(pdev->sbdf, reg, val); } =20 static struct vpci_msix *msix_find(const struct domain *d, unsigned long a= ddr) @@ -459,8 +458,7 @@ static int init_msix(struct pci_dev *pdev) if ( !msix_offset ) return 0; =20 - control =3D pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf= .dev, - pdev->sbdf.func, msix_control_reg(msix_offse= t)); + control =3D pci_conf_read16(pdev->sbdf, msix_control_reg(msix_offset)); =20 max_entries =3D msix_table_size(control); =20 @@ -472,11 +470,9 @@ static int init_msix(struct pci_dev *pdev) pdev->vpci->msix->pdev =3D pdev; =20 pdev->vpci->msix->tables[VPCI_MSIX_TABLE] =3D - pci_conf_read32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, msix_table_offset_reg(msix_offset= )); + pci_conf_read32(pdev->sbdf, msix_table_offset_reg(msix_offset)); pdev->vpci->msix->tables[VPCI_MSIX_PBA] =3D - pci_conf_read32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, msix_pba_offset_reg(msix_offset)); + pci_conf_read32(pdev->sbdf, msix_pba_offset_reg(msix_offset)); =20 for ( i =3D 0; i < pdev->vpci->msix->max_entries; i++) { diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 9a060c108e..afe0c38396 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -114,15 +114,13 @@ static void vpci_ignored_write(const struct pci_dev *= pdev, unsigned int reg, uint32_t vpci_hw_read16(const struct pci_dev *pdev, unsigned int reg, void *data) { - return pci_conf_read16(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg); + return pci_conf_read16(pdev->sbdf, reg); } =20 uint32_t vpci_hw_read32(const struct pci_dev *pdev, unsigned int reg, void *data) { - return pci_conf_read32(pdev->sbdf.seg, pdev->sbdf.bus, pdev->sbdf.dev, - pdev->sbdf.func, reg); + return pci_conf_read32(pdev->sbdf, reg); } =20 int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, @@ -212,7 +210,7 @@ static uint32_t vpci_read_hw(pci_sbdf_t sbdf, unsigned = int reg, switch ( size ) { case 4: - data =3D pci_conf_read32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, = reg); + data =3D pci_conf_read32(sbdf, reg); break; =20 case 3: @@ -222,26 +220,22 @@ static uint32_t vpci_read_hw(pci_sbdf_t sbdf, unsigne= d int reg, */ if ( reg & 1 ) { - data =3D pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fun= c, - reg); - data |=3D pci_conf_read16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.f= unc, - reg + 1) << 8; + data =3D pci_conf_read8(sbdf, reg); + data |=3D pci_conf_read16(sbdf, reg + 1) << 8; } else { - data =3D pci_conf_read16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fu= nc, - reg); - data |=3D pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fu= nc, - reg + 2) << 16; + data =3D pci_conf_read16(sbdf, reg); + data |=3D pci_conf_read8(sbdf, reg + 2) << 16; } break; =20 case 2: - data =3D pci_conf_read16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, = reg); + data =3D pci_conf_read16(sbdf, reg); break; =20 case 1: - data =3D pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, r= eg); + data =3D pci_conf_read8(sbdf, reg); break; =20 default: @@ -259,7 +253,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int= reg, unsigned int size, switch ( size ) { case 4: - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg, dat= a); + pci_conf_write32(sbdf, reg, data); break; =20 case 3: @@ -269,26 +263,22 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned i= nt reg, unsigned int size, */ if ( reg & 1 ) { - pci_conf_write8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg, - data); - pci_conf_write16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg = + 1, - data >> 8); + pci_conf_write8(sbdf, reg, data); + pci_conf_write16(sbdf, reg + 1, data >> 8); } else { - pci_conf_write16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg, - data); - pci_conf_write8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg += 2, - data >> 16); + pci_conf_write16(sbdf, reg, data); + pci_conf_write8(sbdf, reg + 2, data >> 16); } break; =20 case 2: - pci_conf_write16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg, dat= a); + pci_conf_write16(sbdf, reg, data); break; =20 case 1: - pci_conf_write8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.func, reg, data= ); + pci_conf_write8(sbdf, reg, data); break; =20 default: diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 1cf54eb466..9908d0fe5d 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -58,6 +58,11 @@ typedef union { }; } pci_sbdf_t; =20 +#define PCI_SBDF_T(s, b, d, f) \ + ((pci_sbdf_t) { .seg =3D (s), .bus =3D (b), .dev =3D (d), .func =3D (f= ) }) +#define PCI_SBDF3_T(s, b, e) \ + ((pci_sbdf_t) { .seg =3D (s), .bus =3D (b), .extfunc =3D (e) }) + struct pci_dev_info { /* * VF's 'is_extfn' field is used to indicate whether its PF is an exte= nded @@ -159,24 +164,12 @@ struct pci_dev *pci_get_pdev_by_domain(const struct d= omain *, int seg, int bus, int devfn); void pci_check_disable_device(u16 seg, u8 bus, u8 devfn); =20 -uint8_t pci_conf_read8( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg); -uint16_t pci_conf_read16( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg); -uint32_t pci_conf_read32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg); -void pci_conf_write8( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg, uint8_t data); -void pci_conf_write16( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg, uint16_t data); -void pci_conf_write32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int fun= c, - unsigned int reg, uint32_t data); +uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg); +uint16_t pci_conf_read16(pci_sbdf_t sbdf, unsigned int reg); +uint32_t pci_conf_read32(pci_sbdf_t sbdf, unsigned int reg); +void pci_conf_write8(pci_sbdf_t sbdf, unsigned int reg, uint8_t data); +void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data); +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data); uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes); void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t = data); int pci_mmcfg_read(unsigned int seg, unsigned int bus, --=20 2.17.2 (Apple Git-113) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel