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Wed, 25 Oct 2023 12:29:58 -0700 (PDT) From: =?UTF-8?q?Edwin=20T=C3=B6r=C3=B6k?= To: xen-devel@lists.xenproject.org Cc: =?UTF-8?q?Edwin=20T=C3=B6r=C3=B6k?= , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 01/22] x86/msr: MSR_PLATFORM_INFO shouldn't claim that turbo is programmable Date: Wed, 25 Oct 2023 20:29:31 +0100 Message-Id: <17a99e1da838a2edeeffa5a988e22c6fcb31406b.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1698262237313100003 From: Edwin T=C3=B6r=C3=B6k Xen forbids writes to the various turbo control MSRs, however MSR_PLATFORM_= INFO claims that these MSRs are writable. Override MSR_PLATFORM_INFO bits to indicate lack of support. See Intel SDM Volume 4, 2.17.6 "MSRs Introduced in the Intel Xeon Scaslable= Processor Family", which describes that MSR_PLATFORM_INFO.[28] =3D 1 implies that MSR_TURBO_RA= TIO_LIMIT is R/W, and similarly bit 29 for TDP control, and bit 30 for MSR_TEMPERATURE_TARGET. These bits were not all present on earlier processors, however where missin= g the bits were reserved, and when present they are always present in the same bits. (Curiously bit 31 that Xen uses is not documented anywhere in this manual b= ut a separate one). Backport: 4.0+ Signed-off-by: Edwin T=C3=B6r=C3=B6k --- xen/arch/x86/cpu-policy.c | 8 ++++++++ xen/include/xen/lib/x86/cpu-policy.h | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 81e574390f..64c8857a61 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -407,6 +407,14 @@ static void __init calculate_host_policy(void) /* 0x000000ce MSR_INTEL_PLATFORM_INFO */ /* probe_cpuid_faulting() sanity checks presence of MISC_FEATURES_ENAB= LES */ p->platform_info.cpuid_faulting =3D cpu_has_cpuid_faulting; + + /* Xen denies write access to turbo control MSRs, however natively the= CPU may support them + and advertise those MSRs as writable by having bits 28 to 30 set to= 1 in MSR_PLATFORM_INFO. + Set these bits to 0 to avoid confusing guests on the availability o= f turbo controls. + */ + p->platform_info.programmable_ratio_turbo =3D 0; + p->platform_info.programmable_tdp_turbo =3D 0; + p->platform_info.programmable_tj_offset =3D 0; } =20 static void __init guest_common_max_feature_adjustments(uint32_t *fs) diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index bab3eecda6..70479689f2 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -339,7 +339,10 @@ struct cpu_policy union { uint32_t raw; struct { - uint32_t :31; + uint32_t :28; + bool programmable_ratio_turbo:1; + bool programmable_tdp_turbo:1; + bool programmable_tj_offset:1; bool cpuid_faulting:1; }; } platform_info; --=20 2.41.0