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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1792164601; l=1244; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=+LzNSE69Zr30dJkU84NarchViXCqICrw6WmtSLXks6Q=; b=bNTzxbYvv9vey4JFgGuBmc1YSyU9HYVbIGJ/y6Ya5nH8owyjvbOZWlcI2n85Ep+5dFkXXT1fb 3vu3h6/sCqkCBDtGMzVZ9LLo0asg3B9sL6/G+5QlnaOTe5ypgAq6fkg X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1792164865623 X-purgate-ID: tlsNG-bad1c0/1792164870-3A6DA034-00595ABD/10/73395122804 X-purgate-type: spam X-purgate-size: 1246 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1792164886731158500 Use pte_is_valid() instead of open-coding the PTE_VALID check. No functional change. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v6: - no changes, already reviewed and waiting to be merged. --- Changes since v5: - no changes, already reviewed and waiting to be merged. --- Changes since v4: - rebase on top of staging. --- Changes since v3: - no changes. - add trailers. --- Changes since v2: - new patch. --- xen/arch/riscv/include/asm/page.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index b465a90325..c8bb334b85 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -187,7 +187,7 @@ static inline bool pte_is_mapping(pte_t p) /* See pte_is_table() */ ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); =20 - return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); + return pte_is_valid(p) && (p.pte & PTE_ACCESS_MASK); } =20 static inline bool pte_is_superpage(pte_t p, unsigned int level) --=20 2.55.0 From nobody Fri Oct 23 16:20:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 16 Oct 2026 17:34:25 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=kd8hyu2pwxdWJMMk+8+bs2OtvVOlWK795twG5YZLGjQ=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=FBDfl7LnyHgbZE7QBnWIaZWnqfLu6PilyYRA1H+ll9lb4jvuGZ4n2Qpa04H8MxfM86Lb2vap4 pkngcrlJ6Gcsj2vxWjCvSNnp5XBvl5U5hcIBdu41/VFgQ45m1zzwEw05QRxlcScZqSuOkGsHS93 1h6ujJrAc61q8m/MzOR+JL6jCJJM4BcR9dyY9OUIIZEXtITp4i00Ww5sSibUmZK96XJ1xDMIgex ByQY43g1uA8CRPkoP+8zLkmnzK1sjP1sUNl7FJ1g9BhOW6bfJukhHC8xn3QN5MlbjBa6gvXzEgO +P1eYNR2c5r5Z0IPOjkptsUZvydfVeI9VbB2HK5ZqAuQ== X-Zone-Loop: 3524b98995af21cdc3e15cf19697b182d256875d8686 x-campaign-type: default x-transaction-id: fc82399a-4f1d-4a27-93e0-74ae26b0175e x-swg-uid: 01-faa53deb-8804-4052-9cd5-cde350502cd8 X-Mailer: Sweego Message-ID: <1792164866.8631fc262581453bbf619ec5b2062170.1a14559aa020008425@vates.tech> x-swg-bid: 1792164866.8631fc262581453bbf619ec5b2062170.1a14559aa020008425 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko , Zheng Zhang Subject: [PATCH v7 2/4] xen/riscv: fix A/D bits in Xen's page-table mappings Date: Fri, 16 Oct 2026 17:34:18 +0200 In-Reply-To: <1792164706.8631fc262581453bbf619ec5b2062170.1a14557373c0008425@vates.tech> References: <1792164706.8631fc262581453bbf619ec5b2062170.1a14557373c0008425@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1792164601; l=7908; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=X3nR2IyT1QGAA88KY+QhGva03mGk51wIsZ54wFGrE0M=; b=Zf6myBrnbaP6fH0g1Vp30SbVVH/7sFrfgi4Ng3APtX75mzf91GuiRdZJydihc3DrVAGvDHWBB gFj/7EfNcCrA3INnaq2OWhm0Ahd3tmoJviFcXzHwNvDo2TWFNGNK8U6 X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1792164866122 X-purgate-ID: tlsNG-c1860d/1792164874-CCD7087B-21287097/10/73395122804 X-purgate-type: spam X-purgate-size: 7910 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1792164888945158500 Xen does not handle page faults caused by clear A/D bits, so it presets them when creating PTEs. pt_update_entry() does so, but three places build leaf PTEs directly without going through it: setup_initial_mapping() (the boot page tables), check_pgtbl_mode_support() (the temporary root entry used to probe SATP mode support) and arch_pmap_map() (the fixmap). On implementations that fault on clear A/D bits (Svade), all three fault on first access. For check_pgtbl_mode_support(), the fault is raised by the instruction fetch right after the SATP write, before any trap handler is set. Add PTE_ACCESSED and PTE_DIRTY to PAGE_HYPERVISOR_RO, and build PAGE_HYPERVISOR_RW and PAGE_HYPERVISOR_RX on top of it. PTE_DIRTY is set in all cases for consistency with pt_update_entry() which sets it at runtime. This fixes arch_pmap_map() for free, since it already builds its PTE from PAGE_HYPERVISOR_RW. Switch setup_initial_mapping() to use these macros for its default, text and rodata permissions, and check_pgtbl_mode_support() to use PAGE_HYPERVISOR_RX for its temporary root entry. The latter drops PTE_WRITABLE, going from RWX to RX, but this is harmless, as that entry only has to make the current instruction stream fetchable between the two CSR_SATP writes, and nothing writes through it. Drop the now-redundant PTE_LEAF_DEFAULT, since converting the last open-coded site above leaves it with no user outside page.h itself. pte_is_table() and pte_is_mapping() both assert that a PTE doesn't use one of the two reserved encodings, (V=3D1, W=3D1, R=3D0) and (V=3D1, X=3D1, W= =3D1, R=3D0), by masking it with PAGE_HYPERVISOR_RW. Now that PAGE_HYPERVISOR_RW also carries A and D, a reserved PTE with A or D set would no longer be caught. Mask with the V, R and W bits explicitly instead, and factor the check out into pte_has_reserved_rwx(). Fixes: e66003e7be19 ("xen/riscv: introduce setup_initial_pages") Fixes: f89e1a170299 ("xen/riscv: introduce asm/pmap.h header") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko Tested-by: Zhang Zheng --- Changes since v6: - add a 2nd Fixes tag, as arch_pmap_map() was introduced by a later commit. --- Changes since v5: - no changes, already reviewed and waiting to be merged. --- Changes since v4: - rebase on top of staging. - add a missing changes line in "Changes since v3". --- Changes since v3: - rebase patch 2/6 which modified wrong indentation. - change commit message to address review comments. - rename pte_is_reserved() to pte_has_reserved_rwx() --- Changes since v2: - add fixes commit ref. - add A/D bits to PAGE_HYPERVISOR_RO and derive PAGE_HYPERVISOR_RW/RX from it for consistency with runtime. - introduce pte_is_reserved() to factor out the reserved-encoding assert shared by pte_is_table() and pte_is_mapping(). - reword commit title --- Changes since v1: - change commit title - mention in patch message that arch_pmap_map() is fixed too, via the PAGE_HYPERVISOR_RW change, not just setup_initial_mapping(). - convert check_pgtbl_mode_support()'s temporary root entry to PAGE_HYPERVISOR_RX, as it's harmless. - drop PTE_LEAF_DEFAULT entirely instead of keeping it, now that no site open-codes it anymore. - drop the pte_is_table() comment line that referenced PAGE_HYPERVISOR_RW, now stale. --- xen/arch/riscv/include/asm/page.h | 33 +++++++++++++++++---------------- xen/arch/riscv/mm.c | 11 +++++------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index c8bb334b85..f9e59e61de 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -46,12 +46,12 @@ #define PTE_PBMT_NOCACHE BIT(61, UL) #define PTE_PBMT_IO BIT(62, UL) =20 -#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 -#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) -#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) -#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE | \ + PTE_ACCESSED | PTE_DIRTY) +#define PAGE_HYPERVISOR_RW (PAGE_HYPERVISOR_RO | PTE_WRITABLE) +#define PAGE_HYPERVISOR_RX (PAGE_HYPERVISOR_RO | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW /* @@ -161,31 +161,32 @@ static inline bool pte_is_valid(pte_t p) * X W R Meaning * 0 0 0 Pointer to next level of page table. * 0 0 1 Read-only page. - * 0 1 0 Reserved for future use. + * 0 1 0 Reserved for future use. [1] * 0 1 1 Read-write page. * 1 0 0 Execute-only page. * 1 0 1 Read-execute page. - * 1 1 0 Reserved for future use. + * 1 1 0 Reserved for future use. [2] * 1 1 1 Read-write-execute page. + * + * So if V=3D1 and W=3D1 then R also needs to be 1 as R =3D 0 is reserve= d for + * future use ([1], [2]). */ +static inline bool pte_has_reserved_rwx(pte_t p) +{ + return (p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) =3D=3D + (PTE_VALID | PTE_WRITABLE); +} + static inline bool pte_is_table(pte_t p) { - /* - * According to the spec if V=3D1 and W=3D1 then R also needs to be 1 = as - * R =3D 0 is reserved for future use ( look at the Table 4.5 ) so che= ck - * in ASSERT that if (V=3D=3D1 && W=3D=3D1) then R isn't 0. - * - * PAGE_HYPERVISOR_RW contains PTE_VALID too. - */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) =3D=3D PTE_VALID); } =20 static inline bool pte_is_mapping(pte_t p) { - /* See pte_is_table() */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return pte_is_valid(p) && (p.pte & PTE_ACCESS_MASK); } diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 06f0406781..6f7dcd10b2 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,19 +140,18 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int pte_flags =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PAGE_HYPERVISOR_RW; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; =20 index =3D pt_index(0, page_addr); =20 - if ( is_kernel_text(addr) || - is_kernel_inittext(addr) ) - pte_flags =3D PTE_EXECUTABLE | PTE_READABLE | PTE_VALI= D; + if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) + pte_flags =3D PAGE_HYPERVISOR_RX; =20 if ( is_kernel_rodata(addr) ) - pte_flags =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PAGE_HYPERVISOR_RO; =20 pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 @@ -197,7 +196,7 @@ static bool __init check_pgtbl_mode_support(struct mmu_= desc *mmu_desc, =20 index =3D pt_index(page_table_level, aligned_load_start); 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1792164601; l=4855; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=eN2ifjmoqFQ0XZBkxcJg+hlp7/mIynrnz6gDFALyBmA=; b=MkRMsAyOMvDjiwpAZycWz+p6eskCQYqqDFtDc/HEJViX5gG1h2bncKqvUspeiIUAOLudnrWln AyaXVKlJ1//DZnq8UdRy7RLVoHUTGadT3ot8xkgQb/tS69QlmHji6Zm X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1792164866439 X-purgate-ID: tlsNG-ebf023/1792164879-C38C1B50-C3DB94E6/10/78276251493 X-purgate-type: spam X-purgate-size: 4857 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1792164899021158500 p2m_set_pte_flags() presets the A/D bits of G-stage PTEs only when RISCV_ISA_EXT_svade is set, which is correct only if the device tree is. The privileged spec allows exactly two schemes for updating the PTE A and D bits: hardware sets them on access and on write, or accessing a page whose A and/or D bit is clear raises a page fault so that software can set them (ratified as Svade). Every implementation uses one of them, but platforms designed before Svade and Svadu were ratified, such as the HiFive Premier P550, may advertise neither. Xen then cannot tell which scheme is in effect, so rather than guess, panic in riscv_fill_hwcap() when the device tree advertises neither Svade nor Svadu, so that the device tree gets fixed. Add Svadu to the known ISA extensions so it can be told apart from Svade. The comment above the enum asks for new extensions to go at the bottom to avoid shuffling, a leftover from Linux where the IDs were macros with explicit values. Nothing depends on the enum values, so have the comment say that multi-letter extensions follow the order of riscv_isa_ext[]. Suggested-by: Jan Beulich Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko Tested-by: Zhang Zheng --- Changes since v6: - drop the probe and trust the device tree, only panic when it advertises neither Svade nor Svadu. - update the patch's title/body accordingly. - put svadu between svade and svpbmt in riscv_isa_ext_id. - rewrite the enum riscv_isa_ext_id comment. --- Changes since v5: - new patch, probe the A/D bits update scheme instead of trusting the device tree alone. --- xen/arch/riscv/cpufeature.c | 17 +++++++++++++++++ xen/arch/riscv/include/asm/cpufeature.h | 13 +++++++------ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 3d5bbd2228..5406fad59b 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -200,6 +200,7 @@ static const struct riscv_isa_ext_entry __initconstrel = riscv_isa_ext[] =3D { RISCV_ISA_EXT_ENTRY(ssaia, ANY), RISCV_ISA_EXT_ENTRY(sstc, NONE), RISCV_ISA_EXT_ENTRY(svade, NONE), + RISCV_ISA_EXT_ENTRY(svadu, NONE), RISCV_ISA_EXT_ENTRY(svpbmt, NONE), }; =20 @@ -674,6 +675,22 @@ void __init riscv_fill_hwcap(void) "Zihintpause unavailable: cpu_relax() gives the CPU no hint= ; " "wire up this platform's pause equivalent in cpu_relax()\n"= ); =20 + /* + * The privileged spec allows exactly two schemes for updating the PTE= A + * and D bits: + * 1) hardware sets them on access and on write; + * 2) accessing a page whose A and/or D bit is clear raises a page fa= ult, + * so that software can set them (ratified as Svade). + * + * Every implementation uses one of them, but may predate the extensio= ns + * and advertise neither. The device tree is then ambiguous: Xen cannot + * tell which scheme is in effect, so panic and have the device tree + * fixed. + */ + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) && + !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svadu) ) + panic("Device tree advertises neither Svade nor Svadu, A/D bits up= date scheme unknown\n"); + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index 2973eb13a5..b0a23be18e 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -8,13 +8,13 @@ #include =20 /* - * These macros represent the logical IDs of each multi-letter RISC-V ISA - * extension and are used in the ISA bitmap. The logical IDs start from - * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for sing= le - * letter extensions and are used in enum riscv_isa_ext_id. + * Logical IDs of RISC-V ISA extensions, used as bit positions in the ISA + * bitmap. * - * New extensions should just be added to the bottom, rather than added - * alphabetically, in order to avoid unnecessary shuffling. + * Single-letter extensions use IDs below RISCV_ISA_EXT_BASE and are sorted + * alphabetically. Multi-letter extensions start from RISCV_ISA_EXT_BASE a= nd + * follow the same order as riscv_isa_ext[] (see the ordering rules descri= bed + * above it). */ #define RISCV_ISA_EXT_BASE 26 =20 @@ -41,6 +41,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ssaia, RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, + RISCV_ISA_EXT_svadu, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX }; --=20 2.55.0 From nobody Fri Oct 23 16:20:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1792164897; cv=none; d=zohomail.com; s=zohoarc; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=h04Hzox3zgjbpcf+0P2EnIWZow6bWEDIHK8/hqyjTPQ=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=RIiC+bGKoUxLYNDzQpWVyDrkkK6+9GMCXws+UuhLKgqfv/S36/sCfEbzwK539hYs8WTBmq7t5 AmkZmx6LmIM107wR8ETFOnQTuNYapP0wpornJh9DEskQrhxGYRnPCf1RAEk5oSOt/4HmzIE53Nb bkTRdB1rk0sEjMiQyRp/WSp8MT+NGpUNNRkh470z/DL494YCzmmPgs19Sh0JRHcJi0Ej2cnRIfN S2qMThBeJZ2ilQ+/hxJ//VYzraGqHr3eaKAD2VSWyvMOCiwEfMP1rgJZ1dlFLf3x3EXzo+MYOhG UAPZE4qZaC6AedElNLlvUYwUafRMuGdojC7qpv7JJ9UQ== X-Zone-Loop: ea2f99a36fef2c199ece06ad51bb652b55a3a11495b7 x-campaign-type: default x-transaction-id: 72999b38-07ea-49ed-906f-d3ed2be33771 x-swg-uid: 01-6a4943de-9800-4414-9e3c-321f373fd043 X-Mailer: Sweego Message-ID: <1792164867.8631fc262581453bbf619ec5b2062170.1a14559acd50008425@vates.tech> x-swg-bid: 1792164867.8631fc262581453bbf619ec5b2062170.1a14559acd50008425 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko , Zheng Zhang Subject: [PATCH v7 4/4] xen/riscv: rework the A/D bits comment in p2m_set_pte_flags() Date: Fri, 16 Oct 2026 17:34:20 +0200 In-Reply-To: <1792164706.8631fc262581453bbf619ec5b2062170.1a14557373c0008425@vates.tech> References: <1792164706.8631fc262581453bbf619ec5b2062170.1a14557373c0008425@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1792164601; l=4824; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=Mv+v4M/J3Q6LeDzmM1l8D/JPCMBtrswouZq8wEXvjUM=; b=dB2J+ksp8OeIPnH8RGrKdlHUqguCXe/dcIi1lrJJAdqjb0IP3u21G+LDV3hlta811pHQFJUpO TB5Uuc3hsU1Bw11DcRmcoXekV/cVVKib4oMX5upC22joaEvtuw1TLCS X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1792164866841 X-purgate-ID: tlsNG-ebf023/1792164883-C0CDFB50-A8D8C7A8/0/0 X-purgate-type: clean X-purgate-size: 4826 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1792164899047158500 The comment in p2m_set_pte_flags() quotes the spec at length to describe the two A/D bits schemes, and its TODO mixes two things: why A/D are preset today (OpenSBI delegates the resulting page faults to a lower privilege mode, so Xen would take them with no handler) and what remains to be done. Summarize the two schemes as a short list. The reason for presetting A/D is not future work, so move it out of the TODO, next to the schemes. The TODO now keeps only the later work, handling these page faults instead of presetting A/D, which only concerns Svade as A/D page faults cannot happen otherwise. Also note that presetting the A/D bits is harmless when the device tree advertises both Svade and Svadu and the platform uses hardware A/D updating. No functional change. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Baptiste Le Duc --- Changes since v6: - drop the change to preset A/D unless only Svadu is advertised, as riscv_fill_hwcap() now panics if the device tree advertises neither Svade nor Svadu. The patch only reworks the comment. - update the patch's title accordingly. --- Changes since v5: - new patch, split out of "xen/riscv: always preset A/D bits in G-stage PTEs". --- xen/arch/riscv/p2m.c | 45 +++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 3d195294d5..a2d81a9c8a 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -591,35 +591,28 @@ static void p2m_set_pte_flags(pte_t *e, p2m_type_t t) e->pte |=3D PTE_USER; =20 /* - * Two schemes to manage the A and D bits are defined: - * =E2=80=A2 The Svade extension: when a virtual page is accessed an= d the A bit - * is clear, or is written and the D bit is clear, a page-fault - * exception is raised. - * =E2=80=A2 When the Svade extension is not implemented, the follow= ing scheme - * applies. - * When a virtual page is accessed and the A bit is clear, the PTE= is - * updated to set the A bit. When the virtual page is written and = the - * D bit is clear, the PTE is updated to set the D bit. When G-sta= ge - * address translation is in use and is not Bare, the G-stage virt= ual - * pages may be accessed or written by implicit accesses to VS-lev= el - * memory management data structures, such as page tables. - * Thereby to avoid a page-fault in case of Svade is available, it is - * necessary to set A and D bits. + * A RISC-V implementation can either: + * 1) Update the 'A' and 'D' PTE bits in hardware. + * 2) Generate a page fault when 'A' and/or 'D' is clear, so that + * software can set them. * - * TODO: For now, it=E2=80=99s fine to simply set the A/D bits, since = OpenSBI - * delegates page faults to a lower privilege mode and so OpenSBI - * isn't expect to handle page-faults occured in lower modes. - * By setting the A/D bits here, page faults that would otherwise - * be generated due to unset A/D bits will not occur in Xen. + * (1) needs nothing more as it is handled by hardware. For (2), set '= A' + * and 'D' up front: OpenSBI delegates such page faults to a lower + * privilege mode, so they would be raised in Xen, which has no handler + * for them. * - * Currently, Xen on RISC-V does not make use of the information - * that could be obtained from handling such page faults, which - * could otherwise be useful for several use cases such as demand - * paging, cache-flushing optimizations, memory access tracking,= etc. + * If both Svade and Svadu are advertised and the CPU updates A/D in + * hardware, presetting them is harmless. * - * To support the more general case and the optimizations mentio= ned - * above, it would be better to stop setting the A/D bits here a= nd - * instead handle page faults that occur due to unset A/D bits. + * TODO: Xen on RISC-V currently makes no use of the information that + * handling such page faults could provide, which would be useful + * for several use cases such as demand paging, cache-flushing + * optimizations, memory access tracking, etc. + * + * To support the more general case and the optimizations + * mentioned above, it would be better to stop setting the A/D + * bits here and instead handle the page faults that occur due to + * unset A/D bits. */ if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) ) e->pte |=3D PTE_ACCESSED | PTE_DIRTY; --=20 2.55.0