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Mon, 05 Oct 2026 16:00:17 +0000 Received: from leducb.home (areims-651-1-80-194.w90-18.abo.wanadoo.fr [90.18.187.194]) (Authenticated sender: baptiste.le-duc) by mail2.vates.fr (Postfix) with ESMTPSA id 20D948280B; Mon, 5 Oct 2026 18:00:16 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=43pCL2Pcw0Ag1BgM2PoJ0XDwKsUsxAQ7FbkpNgPFfic=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=ZI6C75HUSSRnTF9uf2Ats45SPpXvsi9FaVgamtmTIJNSiR2+iVFbxL7I8NzSneP5ueFPkkA9B sUc7XBytAOLS/gS6BBYzspMo2S9ZVvp4j1vNWSr3V4W7F9G5eibOpmcWq4s49uRTPSNcGwvFWtV Bp7iadkBRPZwXn00dCiNohee6t261Yrc9tmOo/3P1ZQx3KeXhxDLTu0zDgDPSJplLXqlPPXgoxp 6yZQvGClcDWc9DBS9j4xJ6R/zMbnYpqZgeSP+HGot+4L4CIeCHt/1ium+tYwL4J0nQ3ZATzD3LY sD18gkji6YNdEvOaw4v4H0/ZL1HmZXXj0t4LD2aJM1PA== X-Zone-Loop: b6c0c72d052383083a30c635c4d132fdd0fd1d8f279c x-campaign-type: default x-transaction-id: 2fa68973-88e9-4adc-bd3b-e53ad72b4158 x-swg-uid: 01-f1eee119-2f8d-4f27-8568-14b990a7b00c X-Mailer: Sweego Message-ID: <1791216017.8631fc262581453bbf619ec5b2062170.1a10ccb5ec20003f66@vates.tech> x-swg-bid: 1791216017.8631fc262581453bbf619ec5b2062170.1a10ccb5ec20003f66 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko , Zheng Zhang Subject: [PATCH v5 1/3] xen/riscv: always preset A/D bits in G-stage PTEs Date: Mon, 5 Oct 2026 18:00:14 +0200 In-Reply-To: <1791215925.8631fc262581453bbf619ec5b2062170.1a10cc9f7c20003f66@vates.tech> References: <1791215925.8631fc262581453bbf619ec5b2062170.1a10cc9f7c20003f66@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1791215868; l=5258; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=+7RuCsiQXUwfROF9vIBU6i/pk2whnmvYv855VhRuUz8=; b=DmXvMoAw7Td79BJHKaVHegoLOBhKrRziema3PB5qGxeEpCHjdbr0lnJHftMAL2Lk5sh0GeSkm poHiQBofggUBrjmdZJ+TAbGfXOxVQ0S73zKn7sdYmgO1lDgkNQZ8ODs X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1791216016324 X-purgate-ID: tlsNG-720697/1791216021-F06A72AC-D89A7C4B/0/0 X-purgate-type: clean X-purgate-size: 5260 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1791216043246158500 A RISC-V implementation can manage the PTE A/D bits in one of two ways: 1) Update the 'A' and 'D' PTE bits in hardware (ratified as Svadu). 2) Generate a page fault when 'A' and/or 'D' is clear, so that software can set them (ratified as Svade). p2m_set_pte_flags() presets A/D in G-stage PTEs only when the device tree advertises Svade. Platforms that use scheme (2) without advertising Svade, such as the HiFive Premier P550, then hit guest-page faults that Xen does not handle. Always preset A/D in G-stage PTEs so scheme (2) never faults. This is harmless with (1): software just does what hardware would have done on first access. Drop the TODO suggesting to handle A/D faults: only Svade raises them, so it would not work on Svadu. Dirty/access tracking can restrict the RWX permissions of p2m entries, as x86 and Arm do. Fixes: ff14053983b0 ("xen/riscv: Implement p2m_pte_from_mfn() and support P= BMT configuration") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- Changes since v4: - restore svade and update the commit message accordingly. - rebase on top of staging. --- Changes since v3: - always preset A/D bits in G-stage mappings instead of keying off the DT: it may not reflect what the hardware actually does. - change commit title/message. - drop svade as it is now-unused. --- Changes since v2: - change commit title. - preset A/D bits in p2m_set_pte_flags() if (!svadu || svade), instead of setting RISCV_ISA_EXT_svade in the riscv_isa bitmap for cases 1, 2 and 4. - riscv_resolve_ad_scheme() now only warns when both Svade and Svadu are present and SBI FWFT is missing; drop the dead 'svadu && svade' operand. - repeat XENLOG_WARNING on each line of the warning. - drop ASSERT(svade !=3D svadu) from p2m_set_pte_flags(). - only add the sbi_probe_extension() declaration to sbi.h. - rework the comment in p2m_set_pte_flags(). --- Changes since v1: - change commit title - expose RISCV_ISA_EXT_svadu so the two extensions can be told apart. - move the Svade/Svadu resolution to a new riscv_resolve_ad_scheme(), called once from riscv_fill_hwcap(). - expose sbi_probe_extension() (was static) to probe for SBI FWFT. - stop presetting A/D bits unconditionally in p2m_set_permission(), do it only when Svade is present. --- xen/arch/riscv/p2m.c | 38 ++++++++------------------------------ 1 file changed, 8 insertions(+), 30 deletions(-) diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index f7b380b90a..14cae7dcd7 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -591,38 +591,16 @@ static void p2m_set_pte_flags(pte_t *e, p2m_type_t t) e->pte |=3D PTE_USER; =20 /* - * Two schemes to manage the A and D bits are defined: - * =E2=80=A2 The Svade extension: when a virtual page is accessed an= d the A bit - * is clear, or is written and the D bit is clear, a page-fault - * exception is raised. - * =E2=80=A2 When the Svade extension is not implemented, the follow= ing scheme - * applies. - * When a virtual page is accessed and the A bit is clear, the PTE= is - * updated to set the A bit. When the virtual page is written and = the - * D bit is clear, the PTE is updated to set the D bit. When G-sta= ge - * address translation is in use and is not Bare, the G-stage virt= ual - * pages may be accessed or written by implicit accesses to VS-lev= el - * memory management data structures, such as page tables. - * Thereby to avoid a page-fault in case of Svade is available, it is - * necessary to set A and D bits. + * A RISC-V implementation can either: + * 1) Update the 'A' and 'D' PTE bits in hardware. + * 2) Generate a page fault when 'A' and/or 'D' is clear, so that + * software can set them. * - * TODO: For now, it=E2=80=99s fine to simply set the A/D bits, since = OpenSBI - * delegates page faults to a lower privilege mode and so OpenSBI - * isn't expect to handle page-faults occured in lower modes. - * By setting the A/D bits here, page faults that would otherwise - * be generated due to unset A/D bits will not occur in Xen. - * - * Currently, Xen on RISC-V does not make use of the information - * that could be obtained from handling such page faults, which - * could otherwise be useful for several use cases such as demand - * paging, cache-flushing optimizations, memory access tracking,= etc. - * - * To support the more general case and the optimizations mentio= ned - * above, it would be better to stop setting the A/D bits here a= nd - * instead handle page faults that occur due to unset A/D bits. + * Xen supports both, so set 'A' and 'D' up front to avoid the faults + * of (2). This is harmless with (1): software just does what hardware + * would have done on first access. */ - if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) ) - e->pte |=3D PTE_ACCESSED | PTE_DIRTY; + e->pte |=3D PTE_ACCESSED | PTE_DIRTY; =20 switch ( t ) { --=20 2.55.0 From nobody Fri Oct 23 15:33:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1791216043; cv=none; d=zohomail.com; s=zohoarc; b=CDhxc0pszGO3S2vbMwg3JVqnCKYmb7sJOsDXDVtXJSxHjWf9zZ5UD8EuKFjPbyEu1BnyirMe32RGSO4ByDcSMKERhYG7oeMTCDfJu09+hsahM3BV30CIISdUvZvgaAzfo+ALBXDX4aMvi8szy0YyCKqUyMjoJiNJd7PCl8B7oOw= ARC-Message-Signature: i=1; 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1791215868; l=7619; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=VSEkK1zF5QeYTsfWAsxXKEDM+CtdWZX+AIJltvq6cZQ=; b=OCZmAm5JzG5Jw2QiJq9kiRIcGvZff6kKULX0zY/lm2yDhtdBg55ilO24dUh0Nc3Rxo3M8HM3B 2xLWlTf6J1AA4qULsBHw2VLchGAuL8+TTX3ksjsr/N0G9A8thOUj5rR X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1791216016960 X-purgate-ID: tlsNG-720697/1791216024-305C52AC-254B5BD6/10/73395122804 X-purgate-type: spam X-purgate-size: 7621 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1791216046505158500 Xen does not handle page faults caused by clear A/D bits, so it presets them when creating PTEs. pt_update_entry() does so, but three places build leaf PTEs directly without going through it: setup_initial_mapping() (the boot page tables), check_pgtbl_mode_support() (the temporary root entry used to probe SATP mode support) and arch_pmap_map() (the fixmap). Without Svadu, all three fault on first access. For check_pgtbl_mode_support(), the fault is raised by the instruction fetch right after the SATP write, before any trap handler is set. Add PTE_ACCESSED and PTE_DIRTY to PAGE_HYPERVISOR_RO, and build PAGE_HYPERVISOR_RW and PAGE_HYPERVISOR_RX on top of it. PTE_DIRTY is set in all cases for consistency with pt_update_entry() which sets it at runtime. This fixes arch_pmap_map() for free, since it already builds its PTE from PAGE_HYPERVISOR_RW. Switch setup_initial_mapping() to use these macros for its default, text and rodata permissions, and check_pgtbl_mode_support() to use PAGE_HYPERVISOR_RX for its temporary root entry. The latter drops PTE_WRITABLE, going from RWX to RX, but this is harmless, as that entry only has to make the current instruction stream fetchable between the two CSR_SATP writes, and nothing writes through it. Drop the now-redundant PTE_LEAF_DEFAULT, since converting the last open-coded site above leaves it with no user outside page.h itself. pte_is_table() and pte_is_mapping() both assert that a PTE doesn't use one of the two reserved encodings, (V=3D1, W=3D1, R=3D0) and (V=3D1, X=3D1, W= =3D1, R=3D0), by masking it with PAGE_HYPERVISOR_RW. Now that PAGE_HYPERVISOR_RW also carries A and D, a reserved PTE with A or D set would no longer be caught. Mask with the V, R and W bits explicitly instead, and factor the check out into pte_has_reserved_rwx(). Fixes: e66003e7be19 ("xen/riscv: introduce setup_initial_pages") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v4: - rebase on top of staging. - add a missing changes line in "Changes since v3". --- Changes since v3: - rebase patch 2/6 which modified wrong indentation. - change commit message to address review comments. - rename pte_is_reserved() to pte_has_reserved_rwx() --- Changes since v2: - add fixes commit ref. - add A/D bits to PAGE_HYPERVISOR_RO and derive PAGE_HYPERVISOR_RW/RX from it for consistency with runtime. - introduce pte_is_reserved() to factor out the reserved-encoding assert shared by pte_is_table() and pte_is_mapping(). - reword commit title --- Changes since v1: - change commit title - mention in patch message that arch_pmap_map() is fixed too, via the PAGE_HYPERVISOR_RW change, not just setup_initial_mapping(). - convert check_pgtbl_mode_support()'s temporary root entry to PAGE_HYPERVISOR_RX, as it's harmless. - drop PTE_LEAF_DEFAULT entirely instead of keeping it, now that no site open-codes it anymore. - drop the pte_is_table() comment line that referenced PAGE_HYPERVISOR_RW, now stale. --- xen/arch/riscv/include/asm/page.h | 33 +++++++++++++++++---------------- xen/arch/riscv/mm.c | 11 +++++------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index b465a90325..8a3e3e1e66 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -46,12 +46,12 @@ #define PTE_PBMT_NOCACHE BIT(61, UL) #define PTE_PBMT_IO BIT(62, UL) =20 -#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 -#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) -#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) -#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE | \ + PTE_ACCESSED | PTE_DIRTY) +#define PAGE_HYPERVISOR_RW (PAGE_HYPERVISOR_RO | PTE_WRITABLE) +#define PAGE_HYPERVISOR_RX (PAGE_HYPERVISOR_RO | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW /* @@ -161,31 +161,32 @@ static inline bool pte_is_valid(pte_t p) * X W R Meaning * 0 0 0 Pointer to next level of page table. * 0 0 1 Read-only page. - * 0 1 0 Reserved for future use. + * 0 1 0 Reserved for future use. [1] * 0 1 1 Read-write page. * 1 0 0 Execute-only page. * 1 0 1 Read-execute page. - * 1 1 0 Reserved for future use. + * 1 1 0 Reserved for future use. [2] * 1 1 1 Read-write-execute page. + * + * So if V=3D1 and W=3D1 then R also needs to be 1 as R =3D 0 is reserve= d for + * future use ([1], [2]). */ +static inline bool pte_has_reserved_rwx(pte_t p) +{ + return (p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) =3D=3D + (PTE_VALID | PTE_WRITABLE); +} + static inline bool pte_is_table(pte_t p) { - /* - * According to the spec if V=3D1 and W=3D1 then R also needs to be 1 = as - * R =3D 0 is reserved for future use ( look at the Table 4.5 ) so che= ck - * in ASSERT that if (V=3D=3D1 && W=3D=3D1) then R isn't 0. - * - * PAGE_HYPERVISOR_RW contains PTE_VALID too. - */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) =3D=3D PTE_VALID); } =20 static inline bool pte_is_mapping(pte_t p) { - /* See pte_is_table() */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); } diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 06f0406781..6f7dcd10b2 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,19 +140,18 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int pte_flags =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PAGE_HYPERVISOR_RW; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; =20 index =3D pt_index(0, page_addr); =20 - if ( is_kernel_text(addr) || - is_kernel_inittext(addr) ) - pte_flags =3D PTE_EXECUTABLE | PTE_READABLE | PTE_VALI= D; + if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) + pte_flags =3D PAGE_HYPERVISOR_RX; =20 if ( is_kernel_rodata(addr) ) - pte_flags =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PAGE_HYPERVISOR_RO; =20 pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 @@ -197,7 +196,7 @@ static bool __init check_pgtbl_mode_support(struct mmu_= desc *mmu_desc, =20 index =3D pt_index(page_table_level, aligned_load_start); stage1_pgtbl_root[index] =3D paddr_to_pte(aligned_load_start, - PTE_LEAF_DEFAULT | PTE_EXECUTA= BLE); + PAGE_HYPERVISOR_RX); =20 sfence_vma(); csr_write(CSR_SATP, --=20 2.55.0 From nobody Fri Oct 23 15:33:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1791216054; cv=none; d=zohomail.com; s=zohoarc; b=AN1CT5tftApHC5bzP77NTwmEUJSZwyjqakTxHbfx5XE7XxC7hEhvTCBdxX0PmA2roVnl7kxvQE4ir29mmVnUvrD6/xEYD8+oXm5k0+cvPDfbqP7GkcEcVG1vCGc64mQ54Ev8C9Bhb8dRLqO6Nm4pBJvUzaKikKv7J2jrv/cTesE= ARC-Message-Signature: i=1; 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1791215868; l=1017; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=mfATwIkml8XPxYLNKsPDuCuta+Y9echIFDKTb+/YvRE=; b=udBmv3YNcYm7Alk+b+2JN7o8WJ/iGv3UZs0K728bPBE4ntdExZntIv/uxnHRjuJgd0CAA2sNM 8DDrkaCdP4bCUnhuiAIKkMKCuVtTHFywlS2tyBJN05AZajuxcotYjpq X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1791216017415 X-purgate-ID: tlsNG-42698a/1791216031-A9EC69EA-B54B7DDF/10/73395122804 X-purgate-type: spam X-purgate-size: 1019 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1791216056700158500 Use pte_is_valid() instead of open-coding the PTE_VALID check. No functional change. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v4: - rebase on top of staging. --- Changes since v3: - no changes. - add trailers. --- Changes since v2: - new patch. --- xen/arch/riscv/include/asm/page.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 8a3e3e1e66..f9e59e61de 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -188,7 +188,7 @@ static inline bool pte_is_mapping(pte_t p) { ASSERT(!pte_has_reserved_rwx(p)); =20 - return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); + return pte_is_valid(p) && (p.pte & PTE_ACCESS_MASK); } =20 static inline bool pte_is_superpage(pte_t p, unsigned int level) --=20 2.55.0