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Wed, 30 Sep 2026 19:30:43 +0000 Received: from Skynet-1 (lfbn-gre-1-317-75.w90-112.abo.wanadoo.fr [90.112.38.75]) (Authenticated sender: olivier.lambert@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id 2689581CA2; Wed, 30 Sep 2026 21:30:42 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=Kpd2jV7S7d6YBx5ym+oeKqua+T/Z4Y5AJYZSAtyvwqQ=; h=from:subject:date:message-id:to:cc:mime-version:content-type:feedback-id; b=Fse6S334g6hpF5jAhWMa33vHJGuWpp+xYWi2xLCSntjTM85/P6/PbYLi1T8vYTrsfFlZXjGIz 7W4ATnQjJFk0w1N/b3W4nOcbTHKp0yztH/9oXYcLjthJf+7/2zyLABijSuJAtd2XRtfm6fAh5ip FPktmF68sLYJTAYtFJzldbmEzmZ8SxxEEgsY7ge0hKDwzrP/W9eomApeskY7W9xq+KhAbp/JksK etk2mogDPtiAQ7FqOeJWQcR6tQdYwNEHqXUg558IWrW7bivWs6FTe2KnWrIq/HnP1HcWuxE4ZGS CJQzVF/DiCIKUs4CU8/OEtzonXqD/zEGrtvQbthzFwPw== X-Zone-Loop: becaa3a908a3e42b53f2b6bcd66239d0eff7406fcb2b x-campaign-type: default x-transaction-id: 14f70a98-d2c0-4e22-aef1-6670ab5187b5 x-swg-uid: 01-8dac6ee2-e6cc-46f5-ae7a-e5ac200a2744 X-Mailer: Sweego Message-ID: <1790796643.8631fc262581453bbf619ec5b2062170.1a0f3cc3da00003f66@vates.tech> x-swg-bid: 1790796643.8631fc262581453bbf619ec5b2062170.1a0f3cc3da00003f66 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Olivier Lambert To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Jason Andryuk Subject: [RFC PATCH v2] x86/ACPI: optimise C3 entry on AMD CPUs Date: Wed, 30 Sep 2026 19:30:27 +0000 MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.55b.68ab02269abdac5e.1a0f3cc37d7.8965732be61e6872=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790796642263 X-purgate-ID: tlsNG-d25034/1790796645-5093EA5B-4D8B2ADE/0/0 X-purgate-type: clean X-purgate-size: 3965 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790796678309158500 ---=Part.55b.68ab02269abdac5e.1a0f3cc37d7.8965732be61e6872=- Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All Zen or newer CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause drop in performance for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly. Signed-off-by: Deepak Sharma Acked-by: Thomas Gleixner Signed-off-by: Rafael J. Wysocki Origin: https://git.kernel.org/torvalds/p/a8fb40966f19 [Port to Xen. Include Hygon.] Assisted-by: Claude-Code:claude-opus-5-5 Signed-off-by: Olivier Lambert Reviewed-by: Jason Andryuk Acked-by: Jan Beulich Reviewed-by: Teddy Astie --- Notes: Changes in v2: - Resend with git send-email: my mail client stripped the whitespace f= rom v1, so its diff could not be applied. No code change. - Picked up Jason's Reviewed-by. =20 Found on XCP-ng 8.3 (Xen 4.17.6) on a Ryzen 5 7600 (Zen 4, family 0x19) whose _CST lists C1 (HLT) plus C2 and C3 as SYSIO states (C3 exit latency 350us). With bm_check =3D=3D 0, every C3 entry executes WBINVD. =20 Measured under a VM-to-VM network load, in 25s windows: - ~140 WBINVD/s, 65-69us each on average, 300us at worst. - Spinning on each CPU in turn with IRQs off and reading the TSC shows gaps of up to 222us; none with this change. The SMI count (PMC event 0x2b, validated by counting cycles on the same counter) stayed at 0, and NMIs didn't line up with the gaps. - credit1's do_schedule() occasionally took up to 262us, with IRQs off; at most 4.4us with this change. - xenpm set-max-cstate 1 removes the stalls too, which points at C3 entry. =20 This change was booted and measured as a backport on 4.17.6 only. On staging it is build-tested. It also covers Hygon, as Linux does today through X86_FEATURE_ZEN; the original Linux commit was AMD-only. =20 This will conflict trivially with Alejandro's pending "x86/acpi: Migrate vendor checks to cpu_vendor()"; happy to rebase on top of it. =20 Possibly a backport candidate. xen/arch/x86/acpi/cpu_idle.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 56b22a2..b2bca4d 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -1065,6 +1065,24 @@ static void acpi_processor_power_init_bm_check(struc= t acpi_processor_flags *flag */ if ( c->vendor =3D=3D X86_VENDOR_INTEL ) flags->bm_control =3D 0; + + if ( (c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + c->family >=3D 0x17 ) + { + /* + * For all AMD Zen or newer CPUs that support C3, caches + * should not be flushed by software while entering C3 + * type state. Set bm_check to 1 so that Xen doesn't + * need to execute cache flush operation. + */ + flags->bm_check =3D 1; + /* + * In current AMD C state implementation ARB_DIS is no longer + * used. So set bm_control to zero to indicate ARB_DIS is not + * required while entering C3 type state. + */ + flags->bm_control =3D 0; + } } =20 #define VENDOR_INTEL (1) --=20 2.53.0 --=20 Olivier Lambert | Vates CEO XCP-ng & Xen Orchestra - Vates solutions Book a meeting with me: https://calrs.vates.tech/u/olivier-lambert web: https://vates.tech ---=Part.55b.68ab02269abdac5e.1a0f3cc37d7.8965732be61e6872=---