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Tue, 29 Sep 2026 16:33:04 +0000 Received: from leducb.home (areims-651-1-80-194.w90-18.abo.wanadoo.fr [90.18.187.194]) (Authenticated sender: baptiste.le-duc) by mail2.vates.fr (Postfix) with ESMTPSA id F133C81FC1; Tue, 29 Sep 2026 18:33:03 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=12mKu7El4VkzxXu5EH/5PCbGFN8X+TVJYBMrRAMDRcI=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=OCgb2ehJC+ErXCa/V5Lrg/Zj5iyAHQoGWpAnytHXvVg0XBd6xh05F/vCwnuzsLDaNwqZ/nW2r LOKIQ2oQei7gVmXQ0/5SuMfKXb5x8DcQqPQaaOSA2sCCP73IVNiu6K7NMSMI3BKff6GxWtvkmei lHbEfXSUthiphkywZnckudWYojurt1Xbfr/ttWBwOBt+OmB1pCCgqDesNBIORkUVXufr7+KUnJs cRrE6lAis2hqKlWumbiA6qVOAxnoyn9yLwWKz6p/u7OPiRwhS3qsdEwyNUn3WaEhllfNpQv14kg vak0+FqHGo3ieKY1GWJZNNl6Bsdi40LXY4ykqo5uJHig== X-Zone-Loop: fe2842a351f855fece7b6f0f02f0ba1a2a638fe53afe x-campaign-type: default x-transaction-id: 2f8fe3ca-19cd-402f-b3e9-f6964f43810a x-swg-uid: 01-db512d60-8cc1-4f86-9a85-f5ebc72efa51 X-Mailer: Sweego Message-ID: <1790699584.8631fc262581453bbf619ec5b2062170.1a0ee033d8d000b504@vates.tech> x-swg-bid: 1790699584.8631fc262581453bbf619ec5b2062170.1a0ee033d8d000b504 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: [PATCH v3 1/6] docs/riscv: sync required ISA extensions with required_extensions[] Date: Tue, 29 Sep 2026 18:32:42 +0200 In-Reply-To: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> References: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=3168; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=nLzeT75EaLv5u/dZAvUywqbxINvFTyoxgtWKF0QIu8g=; b=+i19NMXJr6ygjWucFQtYsFMobjm/VjhNLEN844atyhnp5pAFWOnWBfqFON+D0vDztsLBMRd9m Odcr+6jygBNDQA9ZnXaDU+9DE2UJkQq8A7unDlMwUVihcSrdvXQmMBO X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699584176 X-purgate-ID: tlsNG-4011c0/1790699589-58BC8CFC-06502D6B/10/73395122804 X-purgate-type: spam X-purgate-size: 3225 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699615491158500 From: Oleksii Kurochko booting.txt listed only H, Zbb, Zihintpause and Svpbmt as required, while required_extensions[] in cpufeature.c also checks for I, M, A, Zicsr, Zifencei and, with CONFIG_RISCV_ISA_C=3Dy, C. As the panic message printed for a missing extension points to booting.txt, document the missing ones. Also add a section pointing to riscv_isa_ext[] for the optional extensions Xen recognises, and a comment above required_extensions[] to keep it in sync with the document. No functional change. Suggested-by: Baptiste Le Duc Signed-off-by: Oleksii Kurochko Signed-off-by: Baptiste Le Duc Acked-by: Jan Beulich Reviewed-by: Oleksii Kurochko --- Changes since v2: - new patch --- docs/misc/riscv/booting.txt | 24 ++++++++++++++++++++---- xen/arch/riscv/cpufeature.c | 1 + 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt index e100bde575..c99ccafa74 100644 --- a/docs/misc/riscv/booting.txt +++ b/docs/misc/riscv/booting.txt @@ -1,8 +1,12 @@ System requirements =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -The following extensions are expected to be supported by a system on which -Xen is run: +The following extensions are required by Xen. Xen panics at boot if any of +them is missing from the riscv,isa property of the CPU nodes: +- I, M, A, Zicsr, Zifencei: + Base ISA Xen is compiled for. +- C: + Required only when Xen is built with CONFIG_RISCV_ISA_C=3Dy. - H: Provides additional instructions and CSRs that control the new stage of address translation and support hosting a guest OS in virtual S-mode @@ -18,7 +22,19 @@ Xen is run: - Zihintpause: On a system that doesn't have this extension, cpu_relax() should be implemented properly. -- SVPBMT is mandatory to enable changing the memory attributes of a page. - For platforms that do not support SVPBMT, it is necessary to introduce a +- Svpbmt: + Mandatory to enable changing the memory attributes of a page. + For platforms that do not support Svpbmt, it is necessary to introduce a similar mechanism as described in: https://lore.kernel.org/all/20241102000843.1301099-1-samuel.holland@sifi= ve.com/ + +Note: this list must be kept in sync with required_extensions[] in + xen/arch/riscv/cpufeature.c. + +Optional extensions +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Other extensions recognised by Xen are listed in riscv_isa_ext[] in +xen/arch/riscv/cpufeature.c. Xen uses them when present, but they are not +needed to boot. The second column of that table says whether the extension +is also exposed to guests. diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index aaf544d13f..2d12dffae7 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -203,6 +203,7 @@ static const struct riscv_isa_ext_entry __initconstrel = riscv_isa_ext[] =3D { RISCV_ISA_EXT_ENTRY(svpbmt, NONE), }; =20 +/* Keep in sync with docs/misc/riscv/booting.txt. */ static const struct riscv_isa_ext_data __initconst required_extensions[] = =3D { RISCV_ISA_EXT_DATA(i), RISCV_ISA_EXT_DATA(m), --=20 2.55.0 From nobody Fri Oct 23 15:34:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=3zPdImH7iv8y5g60t32jUOCpFkVJaZ5SSHVr8/w4ycA=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=DIyRb6X+yo4JsYKBTuLxvF7JWhM1OTtkRjy/NcvAyzA+2uFg3xssMlI7KgmvZ7d00zvibNMDt YddoF+8OIMl6mJWX8tOiUR2jQ/Fcfo8mab6ni4ydoi6c7+wNpagVrXmtDWmvBuqvp4TmGoK2fvZ zPSBSXvKiTgCbP4aXNPXQ0qEfJjHE9cYxd5s97+3ZHgI6/oWlI+MEzP8MRf8RIvF3CVJcxQlPD/ D713voIoDfKET0GO9wK+y5gDh1NgiQMGuNAwZ/V0fEiTe6IA32gpA7jXANDZxagzFZoDhSAqQZx +nUl7BulRP6YtxRJt2x4ljYIWvIZHqc0ItutTUJbhduA== X-Zone-Loop: 123d37f5383964c31833018aef8ada642b2335e4c98d x-campaign-type: default x-transaction-id: ad4ede69-0294-42d7-ab40-3ad1cd9fc3f7 x-swg-uid: 01-5b7b0f5a-df1f-46bc-bcdf-2f2480a58410 X-Mailer: Sweego Message-ID: <1790699585.8631fc262581453bbf619ec5b2062170.1a0ee033eb9000b504@vates.tech> x-swg-bid: 1790699585.8631fc262581453bbf619ec5b2062170.1a0ee033eb9000b504 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: [PATCH v3 2/6] xen/riscv: rename PTE "permissions" to "pte_flags" Date: Tue, 29 Sep 2026 18:32:43 +0200 In-Reply-To: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> References: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=3566; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=E3egDkZK6boHg/W2zoFtBVdv7bpvzgoKLJiNsjxQQqM=; b=aR9MHvLXVP0bYgr0h5s1p0ZHi/v+npJaP+TrU9tTxJO97TK7/LJUyoRwM8duZSPRIeVVCaun5 SGEfakJJ+sSAD3txdvDyAr/oXJ4BzNDTdzm8KlW/+6LZb9TsIUImI0Z X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699584706 X-purgate-ID: tlsNG-4011c0/1790699592-538D5CFC-FB0F10A6/10/78276251493 X-purgate-type: spam X-purgate-size: 3902 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699609396158500 paddr_to_pte()'s "permissions" parameter, the matching local in setup_initial_mapping() and p2m_set_permission() don't only deal with permission bits: they also handle PTE_VALID, PTE_USER, PTE_ACCESSED and PTE_DIRTY. Rename them to "pte_flags" and p2m_set_pte_flags() respectively. No functional change. Requested-by: Jan Beulich Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Acked-by: Jan Beulich --- Changes since v2: - new patch --- xen/arch/riscv/include/asm/mm.h | 5 +++-- xen/arch/riscv/mm.c | 8 ++++---- xen/arch/riscv/p2m.c | 4 ++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 9e28c24954..1ac66283ec 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -22,9 +22,10 @@ extern vaddr_t directmap_virt_start; #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) =20 static inline pte_t paddr_to_pte(paddr_t paddr, - unsigned int permissions) + unsigned int pte_flags) { - return (pte_t) { .pte =3D (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | per= missions }; + return (pte_t) { .pte =3D (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | + pte_flags }; } =20 static inline paddr_t pte_to_paddr(pte_t pte) diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 610d111945..0e26c5751f 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,7 +140,7 @@ static void __init setup_initial_mapping(struct mmu_des= c *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int permissions =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PTE_LEAF_DEFAULT; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; @@ -149,13 +149,13 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, =20 if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) - permissions =3D + pte_flags =3D PTE_EXECUTABLE | PTE_READABLE | PTE_VALID; =20 if ( is_kernel_rodata(addr) ) - permissions =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PTE_READABLE | PTE_VALID; =20 - pte_to_be_written =3D paddr_to_pte(paddr, permissions); + pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 if ( !pte_is_valid(pgtbl[index]) ) pgtbl[index] =3D pte_to_be_written; diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 1cea86512c..f7b380b90a 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -584,7 +584,7 @@ static inline void p2m_clean_pte(pte_t *p, bool clean_c= ache) p2m_write_pte(p, pte, clean_cache); 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=10414; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=Mk8xGybs2kVRu6/g1isOlfwZyZJ4XtFG3h9cBFjFKtg=; b=8oJMCfkQP58xS7GtTJYIzHNMGGc5HhAcr1L1GPm5/i3fTUh+lKZh78DytTq4r0LHkrGp45QVd oMobD2lzEWgCJ45nC7pz8RIC8OBQThwniC4/sO1AW8K8EZagjYS0IRz X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699585075 X-purgate-ID: tlsNG-4011c0/1790699595-53AD4CFC-CA8090B2/0/0 X-purgate-type: clean X-purgate-size: 10416 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699619177158500 There are two schemes for managing the PTE A/D bits: either a page fault is raised when an access requires A or D to be set (ratified as Svade), or hardware updates the bits itself (ratified as Svadu). p2m_set_pte_flags() presets the A/D bits in G-stage PTEs only when Svade is present in the device tree. When neither Svade nor Svadu is present, this causes an unhandled page fault. The four possible Svade/Svadu combinations in the device tree mean (see [1]): - neither present: the scheme is unknown, so the A/D bits have to be preset. This is harmless if hardware actually updates them itself. - only Svade present: page faults, so the A/D bits have to be preset. - only Svadu present: hardware updates the A/D bits. - both present: hardware updating is off at boot and has to be enabled through the SBI FWFT extension, which Xen doesn't support yet, so the A/D bits have to be preset. Hence preset the A/D bits in p2m_set_pte_flags() unless only Svadu is present, i.e. when (!svadu || svade). Add riscv_resolve_ad_scheme(), called once from riscv_fill_hwcap(), to warn when both are present but SBI FWFT is missing, as dropping 'svade' from the DT is then the only way to get Svadu. [1] https://lwn.net/Articles/980016/ Fixes: ff14053983b0 ("xen/riscv: Implement p2m_pte_from_mfn() and support P= BMT configuration") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- Changes since v2: - change commit title. - preset A/D bits in p2m_set_pte_flags() if (!svadu || svade), instead of setting RISCV_ISA_EXT_svade in the riscv_isa bitmap for cases 1, 2 and 4. - riscv_resolve_ad_scheme() now only warns when both Svade and Svadu are present and SBI FWFT is missing; drop the dead 'svadu && svade' operand. - repeat XENLOG_WARNING on each line of the warning. - drop ASSERT(svade !=3D svadu) from p2m_set_pte_flags(). - only add the sbi_probe_extension() declaration to sbi.h. - rework the comment in p2m_set_pte_flags(). --- Changes since v1: - change commit title - expose RISCV_ISA_EXT_svadu so the two extensions can be told apart. - move the Svade/Svadu resolution to a new riscv_resolve_ad_scheme(), called once from riscv_fill_hwcap(). - expose sbi_probe_extension() (was static) to probe for SBI FWFT. - stop presetting A/D bits unconditionally in p2m_set_permission(), do it only when Svade is present. --- xen/arch/riscv/cpufeature.c | 43 +++++++++++++++++++++++++++++= ++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/sbi.h | 8 ++++++ xen/arch/riscv/p2m.c | 40 +++++++++--------------------- 4 files changed, 63 insertions(+), 29 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 2d12dffae7..ee35c7a17c 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -20,6 +20,7 @@ =20 #include #include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -200,6 +201,7 @@ static const struct riscv_isa_ext_entry __initconstrel = riscv_isa_ext[] =3D { RISCV_ISA_EXT_ENTRY(ssaia, ANY), RISCV_ISA_EXT_ENTRY(sstc, NONE), RISCV_ISA_EXT_ENTRY(svade, NONE), + RISCV_ISA_EXT_ENTRY(svadu, NONE), RISCV_ISA_EXT_ENTRY(svpbmt, NONE), }; =20 @@ -500,6 +502,45 @@ static void __init riscv_fill_hwcap_from_isa_string(vo= id) } } =20 +/* + * Svade and Svadu extensions represent two schemes for managing the PTE A= /D + * bits. When the PTE A/D bits need to be set, the Svade extension indicat= es + * that a page fault will be raised. In contrast, the Svadu extension supp= orts + * hardware updating of the PTE A/D bits. + * + * There are 4 possible combinations of these extensions in the device tre= e. + * The default hardware behavior for each is: + * + * 1) Neither Svade nor Svadu present in DT =3D> It is technically unknown + * whether the platform uses Svade or Svadu. Xen should be prepared to + * handle either hardware updating of the PTE A/D bits or page faults w= hen + * they need updating. + * + * 2) Only Svade present in DT =3D> Xen must assume Svade to be always ena= bled. + * + * 3) Only Svadu present in DT =3D> Xen must assume Svadu to be always ena= bled. + * + * 4) Both Svade and Svadu present in DT =3D> Xen must assume Svadu is tur= ned off + * at boot time, so it presets the A/D bits. To use Svadu, the supervis= or + * must explicitly enable it using the SBI FWFT extension. + * + * The Svade extension is mandatory and the Svadu extension is optional in= the + * RVA23 profile. Platforms wanting to take advantage of Svadu can choose + * option 3. Platforms aware of the profile can choose option 4, and Xen w= on't + * get the benefit of Svadu until the SBI FWFT extension is available. + */ +static void __init riscv_resolve_ad_scheme(void) +{ + bool svade =3D riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade= ); + bool svadu =3D riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svadu= ); + + if ( svadu && svade ) + if ( sbi_probe_extension(SBI_EXT_FWFT) <=3D 0 ) + printk(XENLOG_WARNING "RISC-V: Both Svade and Svadu detected, = but SBI FWFT is missing.\n" + XENLOG_WARNING "RISC-V: Defaulting to software A/D updates= (Svade).\n" + XENLOG_WARNING "RISC-V: To force hardware A/D updates (Sva= du), remove 'svade' from DT.\n"); +} + static bool __init has_isa_extensions_property(void) { const struct dt_device_node *cpus =3D dt_find_node_by_path("/cpus"); @@ -664,6 +705,8 @@ void __init riscv_fill_hwcap(void) __set_bit(RISCV_ISA_EXT_sstc, riscv_isa); } =20 + riscv_resolve_ad_scheme(); + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index 2973eb13a5..7a448d6111 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -41,6 +41,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ssaia, RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, + RISCV_ISA_EXT_svadu, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX }; diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 1952868e96..4efa166603 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_FWFT 0x46574654 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -138,6 +139,13 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Check if an SBI extension ID is supported or not. + * + * @return: > 0 if supported, 0 if not, negative errno on SBI error. + */ +int sbi_probe_extension(long extid); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index f7b380b90a..5c8e480050 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -586,42 +586,24 @@ static inline void p2m_clean_pte(pte_t *p, bool clean= _cache) =20 static void p2m_set_pte_flags(pte_t *e, p2m_type_t t) { + bool svade =3D riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade= ); + bool svadu =3D riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svadu= ); + e->pte &=3D ~PTE_ACCESS_MASK; =20 e->pte |=3D PTE_USER; =20 /* - * Two schemes to manage the A and D bits are defined: - * =E2=80=A2 The Svade extension: when a virtual page is accessed an= d the A bit - * is clear, or is written and the D bit is clear, a page-fault - * exception is raised. - * =E2=80=A2 When the Svade extension is not implemented, the follow= ing scheme - * applies. - * When a virtual page is accessed and the A bit is clear, the PTE= is - * updated to set the A bit. When the virtual page is written and = the - * D bit is clear, the PTE is updated to set the D bit. When G-sta= ge - * address translation is in use and is not Bare, the G-stage virt= ual - * pages may be accessed or written by implicit accesses to VS-lev= el - * memory management data structures, such as page tables. - * Thereby to avoid a page-fault in case of Svade is available, it is - * necessary to set A and D bits. - * - * TODO: For now, it=E2=80=99s fine to simply set the A/D bits, since = OpenSBI - * delegates page faults to a lower privilege mode and so OpenSBI - * isn't expect to handle page-faults occured in lower modes. - * By setting the A/D bits here, page faults that would otherwise - * be generated due to unset A/D bits will not occur in Xen. - * - * Currently, Xen on RISC-V does not make use of the information - * that could be obtained from handling such page faults, which - * could otherwise be useful for several use cases such as demand - * paging, cache-flushing optimizations, memory access tracking,= etc. + * A RISC-V implementation can choose to either: + * 1) Update 'A' and 'D' PTE bits in hardware. + * 2) Generate page fault when 'A' and/or 'D' PTE bits are not set so = that + * software can update these bits. * - * To support the more general case and the optimizations mentio= ned - * above, it would be better to stop setting the A/D bits here a= nd - * instead handle page faults that occur due to unset A/D bits. + * Xen supports both options mentioned above: unless the platform guar= antees + * (1), i.e. only Svadu is present, set 'A' and 'D' so that (2) never + * faults. */ - if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) ) + if ( !svadu || svade ) e->pte |=3D PTE_ACCESSED | PTE_DIRTY; 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Tue, 29 Sep 2026 16:33:06 +0000 Received: from leducb.home (areims-651-1-80-194.w90-18.abo.wanadoo.fr [90.18.187.194]) (Authenticated sender: baptiste.le-duc) by mail2.vates.fr (Postfix) with ESMTPSA id 75F5981FC1; Tue, 29 Sep 2026 18:33:05 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=kKPNIhp+A4+dr7qNXhZlECXliG/Lv9mfBHv0bnTfetM=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=O5u4BE/4QmFNOJjDs+p0mIYl3LXmhh58qjvXUVafiBLUGeQEEPCtqKNTBaHydCMQw2dswO+mf appecEDDpEtG/2IyKPytugYW9Z/9fRqLfy37/PoTsLcFPcQgcol9pKk38EV24L3z5YbF3x2/9gu iGs72RriktHwAyN9ucA76uBbFWQRmqWKQGSC0YqC5lWAaLMrBncimgStdDvpxrxnxxTN8EFDEsm SScH0j4pgYNm4ALihOPgq0w4EdSllL44QxpzZVE9LLCtPFI4tm/IExllzkHtOrfGUw3FTzHUi5D MDKoZ9WYiJSRTQZwmlV0VZpojE77HemXqbqSl1vn0r9A== X-Zone-Loop: f6d83337c7b6caa7eff60fde5990cf531c17ca8769ac x-campaign-type: default x-transaction-id: beb69862-1969-4380-a14c-db1491c1bb83 x-swg-uid: 01-919144b0-3ebe-4cf3-bbe9-3ac605092d68 X-Mailer: Sweego Message-ID: <1790699586.8631fc262581453bbf619ec5b2062170.1a0ee034220000b504@vates.tech> x-swg-bid: 1790699586.8631fc262581453bbf619ec5b2062170.1a0ee034220000b504 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: [PATCH v3 4/6] xen/riscv: fix A/D bits in Xen's page-table mappings Date: Tue, 29 Sep 2026 18:32:45 +0200 In-Reply-To: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> References: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=7057; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=NxTTVXHRsTwSY9lWWDjt0yaKRyTXaowqbId9133pEl8=; b=oxymPBL7vRDbHp4tyNT+A76AZRvRzGhI9mL280/WyZ/3UfXRCocgQUID4YD1CibKcabIIeN4W og23zJBcT3CBziNNkJkTitee80u2W3/2gmH9GKvGdnbzI2x+UYqaJcq X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699585664 X-purgate-ID: tlsNG-42698a/1790699600-AA0C59EA-F37F4F45/0/0 X-purgate-type: clean X-purgate-size: 7059 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699617435158500 Xen does not handle page faults caused by clear A/D bits, so it presets them when creating PTEs. pt_update_entry() does so, but setup_initial_mapping() (the boot page tables) and arch_pmap_map() (the fixmap) build leaf PTEs directly without going through it. Without Svadu, both would fault on first access. Add PTE_ACCESSED and PTE_DIRTY to PAGE_HYPERVISOR_RO, and build PAGE_HYPERVISOR_RW and PAGE_HYPERVISOR_RX on top of it. PTE_DIRTY is set in all cases for consistency with pt_update_entry() which sets it at runtime. This fixes arch_pmap_map() for free, since it already builds its PTE from PAGE_HYPERVISOR_RW. Switch setup_initial_mapping() to use these macros for its default, text and rodata permissions, and for the temporary root entry built by check_pgtbl_mode_support(), instead of the equivalent raw bit lists. The latter drops PTE_WRITABLE, going from RWX to RX, but this is harmless, as that entry only has to make the current instruction stream fetchable between the two CSR_SATP writes used to probe SATP mode support, and nothing writes through it. Drop the now-redundant PTE_LEAF_DEFAULT, since converting the last open-coded site above leaves it with no user outside page.h itself. pte_is_table() and pte_is_mapping() both assert that a PTE doesn't use one of the two reserved encodings, (V=3D1, W=3D1, R=3D0) and (V=3D1, X=3D1, W= =3D1, R=3D0), by masking it with PAGE_HYPERVISOR_RW. Now that PAGE_HYPERVISOR_RW also carries A and D, a reserved PTE with A or D set would no longer be caught. Mask with the V, R and W bits explicitly instead, and factor the check out into pte_is_reserved(). Fixes: e66003e7be19 ("xen/riscv: introduce setup_initial_pages") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Acked-by: Jan Beulich --- Changes since v2: - add fixes commit ref. - add A/D bits to PAGE_HYPERVISOR_RO and derive PAGE_HYPERVISOR_RW/RX from it for consistency with runtime. - introduce pte_is_reserved() to factor out the reserved-encoding assert shared by pte_is_table() and pte_is_mapping(). - reword commit title --- Changes since v1: - change commit title - mention in patch message that arch_pmap_map() is fixed too, via the PAGE_HYPERVISOR_RW change, not just setup_initial_mapping(). - convert check_pgtbl_mode_support()'s temporary root entry to PAGE_HYPERVISOR_RX, as it's harmless. - drop PTE_LEAF_DEFAULT entirely instead of keeping it, now that no site open-codes it anymore. - drop the pte_is_table() comment line that referenced PAGE_HYPERVISOR_RW, now stale. --- xen/arch/riscv/include/asm/page.h | 33 +++++++++++++++++---------------- xen/arch/riscv/mm.c | 9 ++++----- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index b465a90325..7772e2f572 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -46,12 +46,12 @@ #define PTE_PBMT_NOCACHE BIT(61, UL) #define PTE_PBMT_IO BIT(62, UL) =20 -#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 -#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) -#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) -#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE | \ + PTE_ACCESSED | PTE_DIRTY) +#define PAGE_HYPERVISOR_RW (PAGE_HYPERVISOR_RO | PTE_WRITABLE) +#define PAGE_HYPERVISOR_RX (PAGE_HYPERVISOR_RO | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW /* @@ -161,31 +161,32 @@ static inline bool pte_is_valid(pte_t p) * X W R Meaning * 0 0 0 Pointer to next level of page table. * 0 0 1 Read-only page. - * 0 1 0 Reserved for future use. + * 0 1 0 Reserved for future use. [1] * 0 1 1 Read-write page. * 1 0 0 Execute-only page. * 1 0 1 Read-execute page. - * 1 1 0 Reserved for future use. + * 1 1 0 Reserved for future use. [2] * 1 1 1 Read-write-execute page. + * + * So if V=3D1 and W=3D1 then R also needs to be 1 as R =3D 0 is reserve= d for + * future use ([1], [2]). */ +static inline bool pte_is_reserved(pte_t p) +{ + return (p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) =3D=3D + (PTE_VALID | PTE_WRITABLE); +} + static inline bool pte_is_table(pte_t p) { - /* - * According to the spec if V=3D1 and W=3D1 then R also needs to be 1 = as - * R =3D 0 is reserved for future use ( look at the Table 4.5 ) so che= ck - * in ASSERT that if (V=3D=3D1 && W=3D=3D1) then R isn't 0. - * - * PAGE_HYPERVISOR_RW contains PTE_VALID too. - */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_is_reserved(p)); =20 return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) =3D=3D PTE_VALID); } =20 static inline bool pte_is_mapping(pte_t p) { - /* See pte_is_table() */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_is_reserved(p)); =20 return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); } diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 0e26c5751f..b7b9bff0bf 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,7 +140,7 @@ static void __init setup_initial_mapping(struct mmu_des= c *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int pte_flags =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PAGE_HYPERVISOR_RW; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; @@ -149,11 +149,10 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, =20 if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) - pte_flags =3D - PTE_EXECUTABLE | PTE_READABLE | PTE_VALID; + pte_flags =3D PAGE_HYPERVISOR_RX; =20 if ( is_kernel_rodata(addr) ) - pte_flags =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PAGE_HYPERVISOR_RO; =20 pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 @@ -198,7 +197,7 @@ static bool __init check_pgtbl_mode_support(struct mmu_= desc *mmu_desc, =20 index =3D pt_index(page_table_level, aligned_load_start); stage1_pgtbl_root[index] =3D paddr_to_pte(aligned_load_start, - PTE_LEAF_DEFAULT | PTE_EXECUTA= BLE); + PAGE_HYPERVISOR_RX); =20 sfence_vma(); csr_write(CSR_SATP, --=20 2.55.0 From nobody Fri Oct 23 15:34:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1790699620; cv=none; d=zohomail.com; s=zohoarc; b=lJhJEnKBpq/ILfOaahBO97UtYLzIEg9GAsNkwxyajP8PGq9ZOfu4H8N+W1yS3qeH/PGG+qKGOkt3/oxpfQL5m/4Ay7aq7yVSbb+2l+f4XsW5/qYW3Q/5E1fJ/wzTX7eETDJiO6H5Ikbjavbrf3NPWQy6FNqm5/MdxpcyA7J7h8c= ARC-Message-Signature: i=1; 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=843; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=H8taBvUA6jTgZUfzPnRgv6573OR6Cs4Baa+x6yEI1jI=; b=aSXIMGId6zhCkgNdjuRKU/y+RLztke8YefXSrsIrycCSGqdF8JeeR4+67Y/EOj3AMM9rh42BE sBMVyVvQ+JUDvfwgU+GCsWVVk3PgXHETgAxDslJ0m0xacJFcqLqpzbu X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699585967 X-purgate-ID: tlsNG-ebf023/1790699603-C20D5B50-448A3359/0/0 X-purgate-type: clean X-purgate-size: 845 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699621042158500 Use pte_is_valid() instead of open-coding the PTE_VALID check. No functional change. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- Changes since v2: - new patch. --- xen/arch/riscv/include/asm/page.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 7772e2f572..d357223ce2 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -188,7 +188,7 @@ static inline bool pte_is_mapping(pte_t p) { ASSERT(!pte_is_reserved(p)); =20 - return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); + return pte_is_valid(p) && (p.pte & PTE_ACCESS_MASK); } =20 static inline bool pte_is_superpage(pte_t p, unsigned int level) --=20 2.55.0 From nobody Fri Oct 23 15:34:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Tue, 29 Sep 2026 18:33:06 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=QtEeReohDrT56joXV07q7UEDqQN6ir05HjrVldJ7zVk=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=poah5Y0Xno7GuD+mJJ+E+QzlObBDT09QMM+d9hN3aFSfI73O+Ez6nYnlJPX/Z45KNHciL4Dj7 mXTGkGD4R81uMVtlaUnRz15N7EOiCTdO4k3DEG+tJud3Ydct0bU0CmKJHtI2Ilm79AAoYGMLFCi Ez+EnVbXvrwO1Gou1wXklK+u3owa6NHi5o8g5k4E0NUlN0xkF6nM4Ctzmp+m+xdXaNew5YwfHEO pk7HPtgu1jw68GCE1xf8fE7vsyc7rKYbs086Dr37UuRVQe5sG5RSTBZGZqJRHo5UXAVLsYi/Rc1 rH+Q1HT3uX0IrohVFSgkJxzBxh/d189oXLyT7HhvhBlw== X-Zone-Loop: dbb0accd60713173dad082eecde8a8de48da9f86b2e2 x-campaign-type: default x-transaction-id: f90d3643-613b-45d2-9e15-a710a23097bd x-swg-uid: 01-b8e0be9a-a0c5-4018-a55e-6fc64cddd403 X-Mailer: Sweego Message-ID: <1790699586.8631fc262581453bbf619ec5b2062170.1a0ee034479000b504@vates.tech> x-swg-bid: 1790699586.8631fc262581453bbf619ec5b2062170.1a0ee034479000b504 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: [PATCH v3 6/6] xen/riscv: make Zihintpause no longer a required extension Date: Tue, 29 Sep 2026 18:32:47 +0200 In-Reply-To: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> References: <1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790699289; l=3161; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=WoMBT9/xwT97Z2UudFU580yGvNMK25r/GunTeSHKnhw=; b=0VXexm4THU1RwGaj+gq/JIo/fhZilR1o5Lq0S4ESKSmCc+QuQoBj1MHsTDkpJxOM+KsGDceJw afSjJ8SHgB7ABvL9mYQiSzlP/AgEis7YfpHKyO2HoSBJIwwTT2TdVop X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790699586266 X-purgate-ID: tlsNG-4011c0/1790699606-4B4D7CFC-1D395FA0/0/0 X-purgate-type: clean X-purgate-size: 3163 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790699627120158500 Zihintpause is in required_extensions[] so Xen panics when it is missing, while it does not strictly require hardware support for it. The PAUSE hint (Zihintpause extension) is encoded as FENCE W, 0 (0x0100000F). In accordance with the RISC-V Unprivileged ISA, HINTs are encoded in the space of valid standard instructions. On platforms without Zihintpause support, executing 0x0100000F is treated as a standard FENCE with an empty successor set, which acts as a NOP and never generates an illegal instruction trap. Zihintpause is therefore purely an optimization hint. Drop it from required_extensions[] so Xen can still boot on systems that don't advertise it, and print a warning in that case. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v2: - rewrite commit message - print a warning at boot when Zihintpause is unavailable - drop Zihintpause requirement from booting.txt --- Changes since v1: - rewrite commit message. --- docs/misc/riscv/booting.txt | 3 --- xen/arch/riscv/cpufeature.c | 12 +++++++++++- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt index c99ccafa74..14212ed62f 100644 --- a/docs/misc/riscv/booting.txt +++ b/docs/misc/riscv/booting.txt @@ -19,9 +19,6 @@ them is missing from the riscv,isa property of the CPU no= des: a very simple sequence. The similar issue occurs with other __builtin_, so it is needed to provide a generic version of bitops in RISC-V bitops.h -- Zihintpause: - On a system that doesn't have this extension, cpu_relax() should be - implemented properly. - Svpbmt: Mandatory to enable changing the memory attributes of a page. For platforms that do not support Svpbmt, it is necessary to introduce a diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index ee35c7a17c..91404daac5 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -216,7 +216,6 @@ static const struct riscv_isa_ext_data __initconst requ= ired_extensions[] =3D { RISCV_ISA_EXT_DATA(h), RISCV_ISA_EXT_DATA(zicsr), RISCV_ISA_EXT_DATA(zifencei), - RISCV_ISA_EXT_DATA(zihintpause), RISCV_ISA_EXT_DATA(zbb), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -707,6 +706,17 @@ void __init riscv_fill_hwcap(void) =20 riscv_resolve_ad_scheme(); =20 + /* + * Zihintpause isn't mandatory: the encoding used by cpu_relax() is a + * HINT which executes as a no-op on hardware without the extension. + * Report it, as a platform may provide its own way to hint a spin-wait + * loop, which then has to be wired up in cpu_relax(). + */ + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_zihintpause) ) + printk(XENLOG_WARNING + "Zihintpause unavailable: cpu_relax() gives the CPU no hint= ; " + "wire up this platform's pause equivalent in cpu_relax()\n"= ); + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; --=20 2.55.0