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b=ZrNrmNIK4cVTEAi6nB+/edzEL1qDOO3lJF9uuU2iB5Qqp4ZiMq82hlzHofPvd36xvFTNBFHNd idxYifoHi8NPLfhaLsFEKgqA/eaFe6DZiqm5RrKXG6E5/7nauC2x3p3HZ1X2sszEr+0xxPJeOpc LvMp9OWpKLGyFyMy2NG7CZqiJR8xdaUH+J8UaMM3Sy9QrwA74y2pBZPLnXq0YIGlBFzPjTzY0De e4App96PGHaORFAaRI/h+ErNDRPsfcHAujnq0qr4FrjPIiBCBByIcZbvAy86lbakWuRVhyHCln0 WvXSWaXh0unbl+EwLNBIwA/qG18bvbj54eWC73W62kTQ== X-Zone-Loop: 10b4c05640a8da4398d9b25087e118bc2a72120cd49e x-campaign-type: default x-transaction-id: 69c5737c-279c-481a-ac8c-8068ba8e385f x-swg-uid: 01-c127937a-9dcc-4a91-bc29-95335dd5ff6b X-Mailer: Sweego Message-ID: <1787844808.8631fc262581453bbf619ec5b2062170.1a043dad0d3000c4f3@vates.tech> x-swg-bid: 1787844808.8631fc262581453bbf619ec5b2062170.1a043dad0d3000c4f3 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: zhangzheng@iscas.ac.cn, Baptiste Le Duc , Alistair Francis , Connor Davis , Oleksii Kurochko , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 1/5] xen/riscv: always set A/D bits at boot time Date: Thu, 27 Aug 2026 17:33:15 +0200 In-Reply-To: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> References: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1787844808264 X-purgate-ID: tlsNG-d62444/1787844812-1DC79757-86441F54/0/0 X-purgate-type: clean X-purgate-size: 5404 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1787844842997158500 Always set the PTE A/D bits at boot time to avoid an unhandled page fault on platforms that implement neither Svade nor Svadu, and on platforms that declare both in the device tree. Rewrite the comment to enumerate the four possible Svade/Svadu combinations (inspired by [1]) and set A/D unconditionally, which is correct in all four cases until Svadu is fully supported (full support requires the SBI FWFT call to enable hardware updating of A/D bits). [1] https://lwn.net/Articles/980016/ Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- xen/arch/riscv/p2m.c | 70 ++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 1cea86512c..11dc289f0f 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -591,38 +591,52 @@ static void p2m_set_permission(pte_t *e, p2m_type_t t) e->pte |=3D PTE_USER; =20 /* - * Two schemes to manage the A and D bits are defined: - * =E2=80=A2 The Svade extension: when a virtual page is accessed an= d the A bit - * is clear, or is written and the D bit is clear, a page-fault - * exception is raised. - * =E2=80=A2 When the Svade extension is not implemented, the follow= ing scheme - * applies. - * When a virtual page is accessed and the A bit is clear, the PTE= is - * updated to set the A bit. When the virtual page is written and = the - * D bit is clear, the PTE is updated to set the D bit. When G-sta= ge - * address translation is in use and is not Bare, the G-stage virt= ual - * pages may be accessed or written by implicit accesses to VS-lev= el - * memory management data structures, such as page tables. - * Thereby to avoid a page-fault in case of Svade is available, it is - * necessary to set A and D bits. + * Svade and Svadu extensions represent two schemes for managing the P= TE + * A/D bits. When the PTE A/D bits need to be set, the Svade extension + * indicates that a page fault will be raised. In contrast, the Svadu + * extension supports hardware updating of the PTE A/D bits. * - * TODO: For now, it=E2=80=99s fine to simply set the A/D bits, since = OpenSBI - * delegates page faults to a lower privilege mode and so OpenSBI - * isn't expect to handle page-faults occured in lower modes. - * By setting the A/D bits here, page faults that would otherwise - * be generated due to unset A/D bits will not occur in Xen. + * There are 4 possible combinations of these extensions in the device + * tree. The default hardware behavior for each is: * - * Currently, Xen on RISC-V does not make use of the information - * that could be obtained from handling such page faults, which - * could otherwise be useful for several use cases such as demand - * paging, cache-flushing optimizations, memory access tracking,= etc. + * 1) Neither Svade nor Svadu present in DT =3D> It is technically unk= nown + * whether the platform uses Svade or Svadu. Xen should be prepared= to + * handle either hardware updating of the PTE A/D bits or page faul= ts + * when they need updating. To support both, Xen always sets the 'A= ' and + * 'D' PTE bits at boot time. * - * To support the more general case and the optimizations mentio= ned - * above, it would be better to stop setting the A/D bits here a= nd - * instead handle page faults that occur due to unset A/D bits. + * 2) Only Svade present in DT =3D> Xen must assume Svade to be always + * enabled. + * + * 3) Only Svadu present in DT =3D> Xen must assume Svadu to be always + * enabled. + * + * 4) Both Svade and Svadu present in DT =3D> Xen must assume Svadu is= turned + * off at boot time by setting A/D bits. To use Svadu, the supervis= or + * must explicitly enable it using the SBI FWFT extension. + * + * The Svade extension is mandatory and the Svadu extension is optiona= l in + * the RVA23 profile. Platforms wanting to take advantage of Svadu can + * choose option 3. Platforms aware of the profile can choose option 4= , and + * Linux won't get the benefit of Svadu until the SBI FWFT extension is + * available. + * + * Currently, Xen on RISC-V does not make use of the information that = could + * be obtained from handling such page faults, which could otherwise be + * useful for several use cases such as demand paging, cache-flushing + * optimizations, memory access tracking, etc. + * + * To support the more general case and the optimizations mentioned ab= ove, + * it would be better to stop setting the A/D bits here and instead ha= ndle + * page faults that occur due to unset A/D bits. + */ + + /* + * Preset unconditionally for all 4 cases above, harmless when Svadu + * manages the bits (case 3). Skipping it for case 3 requires SBI FWFT + * which is not yet supported. */ - if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) ) - e->pte |=3D PTE_ACCESSED | PTE_DIRTY; + e->pte |=3D PTE_ACCESSED | PTE_DIRTY; =20 switch ( t ) { From nobody Thu Sep 3 07:05:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=vates.tech Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1787844838536771.7249925026846; Thu, 27 Aug 2026 08:33:58 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1401163.1636917 (Exim 4.92) (envelope-from ) id 1wzc6m-0004FP-Or; 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charset="utf-8" The previous patch made p2m_set_permission() always set the PTE A/D bits to map pages in G-stage, to avoid a page fault on platforms that implement neither Svade nor Svadu, or that declare both in the device tree. Xen's own page tables, built by setup_initial_mapping(), never go through p2m_set_permission() and need the same fix. Add PTE_ACCESSED to PTE_LEAF_DEFAULT and make it the minimal common leaf permission set by dropping PTE_WRITABLE. Rebuild PAGE_HYPERVISOR_RO, PAGE_HYPERVISOR_RW and PAGE_HYPERVISOR_RX from that common base, with PAGE_HYPERVISOR_RW also adding PTE_DIRTY. Switch setup_initial_mapping() to use these macros for its default, text, and rodata permissions instead of the equivalent raw bit lists. A PTE is a table entry iff PTE_VALID is set and R/W/X are all clear, so update pte_is_table() accordingly. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- xen/arch/riscv/include/asm/page.h | 14 ++++++++------ xen/arch/riscv/mm.c | 7 +++---- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index b465a90325..5c02f64a17 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -46,12 +46,12 @@ #define PTE_PBMT_NOCACHE BIT(61, UL) #define PTE_PBMT_IO BIT(62, UL) =20 -#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) +#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_ACCESS= ED) #define PTE_TABLE (PTE_VALID) =20 -#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) -#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) -#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) +#define PAGE_HYPERVISOR_RO (PTE_LEAF_DEFAULT) +#define PAGE_HYPERVISOR_RW (PTE_LEAF_DEFAULT | PTE_WRITABLE | PTE= _DIRTY) +#define PAGE_HYPERVISOR_RX (PTE_LEAF_DEFAULT | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW /* @@ -177,7 +177,8 @@ static inline bool pte_is_table(pte_t p) * * PAGE_HYPERVISOR_RW contains PTE_VALID too. */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT((p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) !=3D + (PTE_VALID | PTE_WRITABLE)); =20 return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) =3D=3D PTE_VALID); } @@ -185,7 +186,8 @@ static inline bool pte_is_table(pte_t p) static inline bool pte_is_mapping(pte_t p) { /* See pte_is_table() */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT((p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) !=3D + (PTE_VALID | PTE_WRITABLE)); =20 return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); } diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 4d3b8c2204..baff49cf09 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,7 +140,7 @@ static void __init setup_initial_mapping(struct mmu_des= c *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int permissions =3D PTE_LEAF_DEFAULT; + unsigned int permissions =3D PAGE_HYPERVISOR_RW; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; @@ -149,11 +149,10 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, =20 if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) - permissions =3D - PTE_EXECUTABLE | PTE_READABLE | PTE_VALID; + permissions =3D PAGE_HYPERVISOR_RX; =20 if ( is_kernel_rodata(addr) ) - permissions =3D PTE_READABLE | PTE_VALID; + permissions =3D PAGE_HYPERVISOR_RO; =20 pte_to_be_written =3D paddr_to_pte(paddr, permissions); From nobody Thu Sep 3 07:05:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=24Z5cEfX20FEssAKJ5JDYU2thxtQEXCNuYQwEhaCNHw=; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding:in-reply-to:references:feedback-id; b=QIHyA+bDeDRk/w40rfz15NeOGbIH+O8a0WAI8D6bwAMWgFadB14oCyLXs8/GPNRhM5iYxeKRO N0mdFG9EBvqJN0Xj53ZnQ9YZIdGLHtKQzM8+7/1XRhoujGnWWDqn4UVW7wKDeL77Z2BMpkI0QBo n8p9vP8G5CAhx31nhyP20pAwb4WJ6M2XZZyridtbM+vJSrC1/tK5pL7HH6lzQHO+y/hkAb/jin0 1r+o5M6U2RCLoo4gvDT/Fl1Dmyo4lgs3qTh88ekJ7RdDR1sHL3Z9U7KdBXGaX+hjxqCS10TLdUc 2sQkMuoNBy8z1Ho9HJYf/D2FrY2zmkY64mAPPQbHn9Fw== X-Zone-Loop: 28b1bd41c377b658159428097b5a8916c244f407a400 x-campaign-type: default x-transaction-id: cd31eacc-04a0-4a67-a765-dc237c755b85 x-swg-uid: 01-a44bb09f-ed3e-4cba-a115-539818405db2 X-Mailer: Sweego Message-ID: <1787844809.8631fc262581453bbf619ec5b2062170.1a043dad34e000c4f3@vates.tech> x-swg-bid: 1787844809.8631fc262581453bbf619ec5b2062170.1a043dad34e000c4f3 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: zhangzheng@iscas.ac.cn, Baptiste Le Duc , Alistair Francis , Connor Davis , Oleksii Kurochko , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 3/5] xen/riscv: make Svpbmt no longer a required extension Date: Thu, 27 Aug 2026 17:33:17 +0200 In-Reply-To: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> References: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1787844809139 X-purgate-ID: tlsNG-d62444/1787844819-1FE68757-E279A184/0/0 X-purgate-type: clean X-purgate-size: 2988 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1787844844929158500 Content-Type: text/plain; charset="utf-8" required_extensions[] panics at boot if Svpbmt is missing, which is a problem on hardware that doesn't implement it. Xen already checks Svpbmt at runtime in some places (vcpu_csr_init()), but not everywhere: p2m_pte_from_mfn() and the PAGE_HYPERVISOR_NOCACHE/WC macros still set the raw PTE_PBMT* encoding unconditionally. Drop Svpbmt from required_extensions, and introduce pte_pbmt(), which masks the requested PBMT encoding down to 0 when Svpbmt is unavailable, using it in both remaining unguarded spots. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- xen/arch/riscv/cpufeature.c | 1 - xen/arch/riscv/include/asm/page.h | 8 ++++++-- xen/arch/riscv/p2m.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 92235fdfd5..900cb9d772 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -157,7 +157,6 @@ static const struct riscv_isa_ext_data __initconst requ= ired_extensions[] =3D { RISCV_ISA_EXT_DATA(zifencei), RISCV_ISA_EXT_DATA(zihintpause), RISCV_ISA_EXT_DATA(zbb), - RISCV_ISA_EXT_DATA(svpbmt), }; =20 static bool __init is_lowercase_extension_name(const char *str) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 5c02f64a17..6a3749526d 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -11,6 +11,7 @@ #include =20 #include +#include #include =20 #define VPN_MASK (PAGETABLE_ENTRIES - 1UL) @@ -54,6 +55,9 @@ #define PAGE_HYPERVISOR_RX (PTE_LEAF_DEFAULT | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW + +#define pte_pbmt(pbmt) \ + (riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ? (pbmt) : = 0UL) /* * PAGE_HYPERVISOR_NOCACHE is used for ioremap(). * @@ -61,8 +65,8 @@ * is that IO is non-idempotent and strongly ordered, which makes it a good * candidate for mapping IOMEM. */ -#define PAGE_HYPERVISOR_NOCACHE (PAGE_HYPERVISOR_RW | PTE_PBMT_IO) -#define PAGE_HYPERVISOR_WC (PAGE_HYPERVISOR_RW | PTE_PBMT_NOCACHE) +#define PAGE_HYPERVISOR_NOCACHE (PAGE_HYPERVISOR_RW | pte_pbmt(PTE_PBM= T_IO)) +#define PAGE_HYPERVISOR_WC (PAGE_HYPERVISOR_RW | pte_pbmt(PTE_PBM= T_NOCACHE)) =20 /* * The PTE format does not contain the following bits within itself; diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 11dc289f0f..f6e635ec1d 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -683,7 +683,7 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, switch ( t ) { case p2m_mmio_direct_io: - e.pte |=3D PTE_PBMT_IO; + e.pte |=3D pte_pbmt(PTE_PBMT_IO); break; =20 default: From nobody Thu Sep 3 07:05:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" required_extensions[] panics at boot if Zihintpause is missing, but Xen never actually depends on it: cpu_relax() only emits the "pause" when the extension is implemented and otherwise falls back to the raw fence encoding, which is a legal no-op on any hart regardless of Zihintpause support. Drop it from required_extensions so hardware without Zihintpause still boots. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- xen/arch/riscv/cpufeature.c | 1 - 1 file changed, 1 deletion(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 900cb9d772..661babc0a6 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -155,7 +155,6 @@ static const struct riscv_isa_ext_data __initconst requ= ired_extensions[] =3D { RISCV_ISA_EXT_DATA(h), RISCV_ISA_EXT_DATA(zicsr), RISCV_ISA_EXT_DATA(zifencei), - RISCV_ISA_EXT_DATA(zihintpause), RISCV_ISA_EXT_DATA(zbb), }; From nobody Thu Sep 3 07:05:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=i+HHq2A31VQb2g0bdrLz5UpxPcOvqCH0udYV5TPCDME=; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding:in-reply-to:references:feedback-id; b=lGSlBITXmfankS51hczo2ipy6y9H1e4NMM6p0eUTdYptAEROv7sCPLjQZ8DbASUPFjRfxof98 gybPD4j2ZgCf+aXUNe7zcCTVLnk8nEfnVbtFNEIYiLYZZU1BOy6JT1Q1l9b9cueZMxrgn8nmDm/ latsATuPJ99wfJr8jUI+yrquobdTa+yaLsm1oGOyIaBCilqhF3/WBfHHBcaRuS6AOQ1liAy6Jm0 iDG/IOQQ/sMNuOjwR5qeO8GlrlrSv1fQr+OLB2aSQ19WhCywXHa04+Sq/OPBCBaIdQyS4Lo92qR bswzFEIT6+q7c/ZRpnEvAL1q4sZCOcX8y5zjqw6M+VqA== X-Zone-Loop: 8dd3241f923ac5462f190502a8fbde2faeef09ccf148 x-campaign-type: default x-transaction-id: 590e34cd-8d8c-4ef1-b2da-a78619f557c2 x-swg-uid: 01-101f5d24-f1c3-4260-9a82-43a570afc621 X-Mailer: Sweego Message-ID: <1787844810.8631fc262581453bbf619ec5b2062170.1a043dad5be000c4f3@vates.tech> x-swg-bid: 1787844810.8631fc262581453bbf619ec5b2062170.1a043dad5be000c4f3 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: zhangzheng@iscas.ac.cn, Baptiste Le Duc , Alistair Francis , Connor Davis , Oleksii Kurochko , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 5/5] xen/riscv: add SFENCE.VMA after enabling paging Date: Thu, 27 Aug 2026 17:33:19 +0200 In-Reply-To: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> References: <1787844438.8631fc262581453bbf619ec5b2062170.1a043d52a06000c4f3@vates.tech> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1787844809736 X-purgate-ID: tlsNG-42698a/1787844826-AAAD89EA-3FF432D2/0/0 X-purgate-type: clean X-purgate-size: 1850 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1787844851365158500 Content-Type: text/plain; charset="utf-8" turn_on_mmu() writes satp to switch on Sv39 paging but never fences afterwards. Xen never allocates a non-zero ASID, so per the Privileged spec, sec. 12.2.1 "Supervisor Memory-Management Fence Instruction": "If the implementation does not provide ASIDs, or software chooses to always use ASID 0, then after every satp write, software should execute SFENCE.VMA with rs1=3Dx0." The spec text around this rule hedges with "may be necessary", but RISC-V spec co-author Andrew Waterman confirmed on the ISA manual issue tracker that the fence after a satp write is not optional in this case: "The SFENCE after the SATP write is definitely necessary ... In general, you need to SFENCE after you've recycled an ASID. Since we don't use ASIDs in the Linux kernel yet, every context switch is effectively an ASID reuse, hence the full TLB flush." [1] The same reasoning applies to Xen: with ASID always 0, this satp write is indistinguishable from an ASID reuse to the hart, so the fence is required for correctness. Add the missing SFENCE.VMA to order those page-table stores before the hart's first translation under the new mapping. [1] https://github.com/riscv/riscv-isa-manual/issues/226 Fixes: f5035d480f7a ("xen: add files needed for minimal riscv build") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- xen/arch/riscv/riscv64/head.S | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 9c40512e61..7f6edc972f 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -98,6 +98,7 @@ FUNC(turn_on_mmu) srli t1, t1, PAGE_SHIFT or t1, t1, t0 csrw CSR_SATP, t1 + sfence.vma =20 jr a0 END(turn_on_mmu)