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Fri, 07 Aug 2026 21:28:41 +0000 Received: from localhost.localdomain (88-188-240-210.subs.proxad.net [88.188.240.210]) (Authenticated sender: teddy.astie@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id 540A1835D6; Fri, 7 Aug 2026 23:28:40 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=siQjNhS1rXHQWa6eDG4c4KcvJWFe9SWt3KniEaLmaqw=; h=from:subject:date:message-id:to:cc:mime-version:content-type:feedback-id; b=oOchjdIjqNY73vWIm+X3lBJirJzsJpZnFCh+IN2ROdO7Nm4qe4Qv5qUmQ5mWndQQ3DHXGwTK6 PytkPhENDY8BW2FP5j/tKa1hD1XvZHfFBJFgx6p6csPsOgZxFK4HJ61RosdYGe5DW///shObQjq cEmHuNsc/b+1jmJ06gaY15+OI6/crVWEuyvrNt8lZ6YGwRrcRSX0LN9hZAho+4UYrazo/GOANUD qgf3hP1+dChhmszwOi+Pld/h6+3lunu67hDyN1lhymUhpdOSxENItYXUfU3bv6KjtEne/T2jp4+ 1UqtERyGqjcJTPp9XZPGip8FxCqn4B3bvQqYSJHgxUeQ== X-Zone-Loop: 0f7696cbc95cc987e045f65c6e6af76de5cb2c0eb37c x-campaign-type: default x-transaction-id: fd0e310a-1f27-4724-be14-41255f131e87 x-swg-uid: 01-db421d96-5e6c-44da-b753-4c378dd236cc X-Mailer: Sweego Message-ID: <1786138121.8631fc262581453bbf619ec5b2062170.19fde20d3e4000e099@vates.tech> x-swg-bid: 1786138121.8631fc262581453bbf619ec5b2062170.19fde20d3e4000e099 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Teddy Astie To: xen-devel@lists.xenproject.org Cc: Teddy Astie , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Kevin Lampis Subject: [PATCH] public/xen.h: Update comment on mmu_update sub-command size and PTE alignment Date: Fri, 7 Aug 2026 23:28:10 +0200 MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.1f09.34907377b737dadc.19fde20d17d.acbe1d96dc5fb6c6=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1786138120576 X-purgate-ID: tlsNG-720697/1786138125-323D42AC-1DCA6395/0/0 X-purgate-type: clean X-purgate-size: 4436 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1786138175391158500 ---=Part.1f09.34907377b737dadc.19fde20d17d.acbe1d96dc5fb6c6=- Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" HYPERVISOR_mmu_update passes a set of request, where each request has a poi= nter to the PTE along with a sub-command. The PTE alignment padding is used to transport the sub-command while the re= st is used as a address to a PTE entry. The current documentation state that t= he 2 first bits are used for sub-command, hence the other ones for PTE which imply here a 4-bytes alignment on PTEs. On PV64 and PV32-PAE guests, all pagetable PTEs are 8-bytes aligned, hence off-by-4 PTEs addresses are always incorrect. Non-PAE PV32 guests used "legacy pagetables" which had 4-byte aligned PTEs. However, support had been completely removed since Xen 4.0, and were only available when Xen was built in 32-bits non-PAE mode [1]. Current Xen logic behave as if 3 bits are used as sub-command, thus all off-by-4 PTEs are actually rejected as being unknown sub-commands. Adjust the documentation to match the current logic implemented in Xen, also expanding the documented sub-command parameter to 3 bits. [1] 84d54d5d8b31 ("i386: Remove non-PAE hypervisor build target.") Signed-off-by: Teddy Astie --- This happens to be a complete rewording of [2]. I'm not sure what to do exa= ctly regarding the signed-off. CC: Kevin Lampis This now expanded sub-command field can be used for your "unmap_page_range = optimisation" series to avoid having to introduce a new dedicated hypercall. [2] https://lore.kernel.org/xen-devel/20260528075539.10209-3-frediano.zigli= o@cloud.com/ xen/include/public/xen.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index 2149b8dd38..b4fef2c5ba 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -218,16 +218,16 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * x =3D=3D 0 =3D> PFD =3D=3D DOMID_SELF * x !=3D 0 =3D> PFD =3D=3D x - 1 * - * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. + * Sub-commands: ptr[2:0] specifies the appropriate MMU_* command. * ------------- - * ptr[1:0] =3D=3D MMU_NORMAL_PT_UPDATE: + * ptr[2:0] =3D=3D MMU_NORMAL_PT_UPDATE: * Updates an entry in a page table belonging to PFD. If updating an L1 ta= ble, * and the new table entry is valid/present, the mapped frame must belong = to * FD. If attempting to map an I/O page then the caller assumes the privil= ege * of the FD. * FD =3D=3D DOMID_IO: Permit /only/ I/O mappings, at the priv level of th= e caller. * FD =3D=3D DOMID_XEN: Map restricted areas of Xen's heap space. - * ptr[:2] -- Machine address of the page-table entry to modify. + * ptr[:3] -- Machine address of the page-table entry to modify. * val -- Value to write. * * There also certain implicit requirements when using this hypercall. The @@ -264,17 +264,17 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and = the * pagetable MUST not be in use (meaning that the cr3 is not set to it). * - * ptr[1:0] =3D=3D MMU_MACHPHYS_UPDATE: + * ptr[2:0] =3D=3D MMU_MACHPHYS_UPDATE: * Updates an entry in the machine->pseudo-physical mapping table. - * ptr[:2] -- Machine address within the frame whose mapping to modify. + * ptr[:3] -- Machine address within the frame whose mapping to modify. * The frame must belong to the FD, if one is specified. * val -- Value to write into the mapping entry. * - * ptr[1:0] =3D=3D MMU_PT_UPDATE_PRESERVE_AD: + * ptr[2:0] =3D=3D MMU_PT_UPDATE_PRESERVE_AD: * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are OR= ed * with those in @val. * - * ptr[1:0] =3D=3D MMU_PT_UPDATE_NO_TRANSLATE: + * ptr[2:0] =3D=3D MMU_PT_UPDATE_NO_TRANSLATE: * As MMU_NORMAL_PT_UPDATE above, but @val is not translated though FD * page tables. * --=20 2.54.0 --=20 | Vates=20 XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech ---=Part.1f09.34907377b737dadc.19fde20d17d.acbe1d96dc5fb6c6=---