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Tue, 16 Jun 2020 17:20:39 +0200 (CEST) X-Inumbo-ID: 0607135e-afe5-11ea-b8fa-12813bfff9fa X-Virus-Scanned: amavisd-new at bagnar.nask.net.pl X-Virus-Scanned: amavisd-new at belindir.nask.net.pl Date: Tue, 16 Jun 2020 17:20:39 +0200 (CEST) From: =?utf-8?Q?Micha=C5=82_Leszczy=C5=84ski?= To: Xen-devel Message-ID: <1672321493.8765712.1592320839082.JavaMail.zimbra@cert.pl> In-Reply-To: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> References: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> Subject: [PATCH v1 2/7] x86/vmx: add IPT cpu feature MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.16.10.10] X-Mailer: Zimbra 8.6.0_GA_1194 (ZimbraWebClient - GC83 (Win)/8.6.0_GA_1194) Thread-Topic: x86/vmx: add IPT cpu feature Thread-Index: KAn5ItxMsuAqHW3ZzkheyNf1oni9hgbflCcQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Jun Nakajima , Wei Liu , Andrew Cooper , Jan Beulich , Roger Pau =?utf-8?Q?Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Content-Type: text/plain; charset="utf-8" Check if Intel Processor Trace feature is supported by current processor. Define hvm_ipt_supported function. Signed-off-by: Michal Leszczynski --- xen/arch/x86/hvm/vmx/vmx.c | 24 +++++++++++++++++++++ xen/include/asm-x86/cpufeature.h | 1 + xen/include/asm-x86/hvm/hvm.h | 9 ++++++++ xen/include/asm-x86/hvm/vmx/vmcs.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 36 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index ab19d9424e..a91bbdb798 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2484,6 +2484,7 @@ static bool __init has_if_pschange_mc(void) =20 const struct hvm_function_table * __init start_vmx(void) { + u64 _vmx_misc_cap; set_in_cr4(X86_CR4_VMXE); =20 if ( vmx_vmcs_init() ) @@ -2557,6 +2558,29 @@ const struct hvm_function_table * __init start_vmx(v= oid) vmx_function_table.get_guest_bndcfgs =3D vmx_get_guest_bndcfgs; } =20 + /* Check whether IPT is supported in VMX operation */ + vmx_function_table.ipt_supported =3D 1; + + if ( !cpu_has_ipt ) + { + vmx_function_table.ipt_supported =3D 0; + printk("VMX: Missing support for Intel Processor Trace x86 feature= .\n"); + } + + rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); + + if ( !( _vmx_misc_cap & VMX_MISC_PT_SUPPORTED ) ) + { + vmx_function_table.ipt_supported =3D 0; + printk("VMX: Missing support for Intel Processor Trace in VMX oper= ation, VMX_MISC caps: %llx\n", + (unsigned long long)_vmx_misc_cap); + } + + if (vmx_function_table.ipt_supported) + { + printk("VMX: Intel Processor Trace is SUPPORTED"); + } + lbr_tsx_fixup_check(); ler_to_fixup_check(); =20 diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index f790d5c1f8..8d7955dd87 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -104,6 +104,7 @@ #define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) #define cpu_has_avx512er boot_cpu_has(X86_FEATURE_AVX512ER) #define cpu_has_avx512cd boot_cpu_has(X86_FEATURE_AVX512CD) +#define cpu_has_ipt boot_cpu_has(X86_FEATURE_IPT) #define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA) #define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW) #define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL) diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index 1eb377dd82..48465b6067 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -96,6 +96,9 @@ struct hvm_function_table { /* Necessary hardware support for alternate p2m's? */ bool altp2m_supported; =20 + /* Hardware support for IPT? */ + bool ipt_supported; + /* Hardware virtual interrupt delivery enable? */ bool virtual_intr_delivery_enabled; =20 @@ -630,6 +633,12 @@ static inline bool hvm_altp2m_supported(void) return hvm_funcs.altp2m_supported; } =20 +/* returns true if hardware supports Intel Processor Trace */ +static inline bool hvm_ipt_supported(void) +{ + return hvm_funcs.ipt_supported; +} + /* updates the current hardware p2m */ static inline void altp2m_vcpu_update_p2m(struct vcpu *v) { diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/v= mx/vmcs.h index 906810592f..4c81093aba 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -285,6 +285,7 @@ extern u64 vmx_ept_vpid_cap; =20 #define VMX_MISC_CR3_TARGET 0x01ff0000 #define VMX_MISC_VMWRITE_ALL 0x20000000 +#define VMX_MISC_PT_SUPPORTED 0x00004000 =20 #define VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL =20 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 5ca35d9d97..7cfcac451d 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -217,6 +217,7 @@ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor = Mode Access Prevention */ XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply= Add */ XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(IPT, 5*32+25) /*H Intel Processor Trace */ XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions = */ XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal = Instrs */ XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Ins= trs */ --=20 2.20.1