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Sat, 27 Nov 2021 09:51:52 -0800 (PST) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Yoshihiro Shimoda Subject: [PATCH 01/10] iommu/ipmmu-vmsa: Remove all unused register definitions Date: Sat, 27 Nov 2021 19:51:36 +0200 Message-Id: <1638035505-16931-2-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638035505-16931-1-git-send-email-olekstysh@gmail.com> References: <1638035505-16931-1-git-send-email-olekstysh@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1638035562331100009 From: Oleksandr Tyshchenko This is a non-verbatim port of corresponding Linux upsteam commit: 77cf983892b2e0d40dc256b784930a9ffaad4fc8 Original commit message: commit 77cf983892b2e0d40dc256b784930a9ffaad4fc8 Author: Yoshihiro Shimoda Date: Wed Nov 6 11:35:45 2019 +0900 iommu/ipmmu-vmsa: Remove all unused register definitions To support different registers memory mapping hardware easily in the future, this patch removes all unused register definitions. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Niklas S=C3=B6derlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Although Linux and Xen drivers have a lot in common, the main differences are in translation stages (table formats), VMSAv8 modes, supported SoC generations, etc, therefore that's why there is a slight difference in registers/bits each driver considers unused. No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 59 ++--------------------------= ---- 1 file changed, 2 insertions(+), 57 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index 1255b0d..4a8a974 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -166,15 +166,11 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); =20 #define IMCTR 0x0000 /* - * These fields are implemented in IPMMU-MM only. So, can be set for + * This field is implemented in IPMMU-MM only. So, can be set for * Root IPMMU only. */ #define IMCTR_VA64 (1 << 29) -#define IMCTR_TRE (1 << 17) -#define IMCTR_AFE (1 << 16) -#define IMCTR_RTSEL_MASK (3 << 4) -#define IMCTR_RTSEL_SHIFT 4 -#define IMCTR_TREN (1 << 3) + /* * These fields are common for all IPMMU devices. So, can be set for * Cache IPMMUs as well. @@ -184,42 +180,9 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMCTR_MMUEN (1 << 0) #define IMCTR_COMMON_MASK (7 << 0) =20 -#define IMCAAR 0x0004 - #define IMTTBCR 0x0008 #define IMTTBCR_EAE (1U << 31) #define IMTTBCR_PMB (1 << 30) -#define IMTTBCR_SH1_NON_SHAREABLE (0 << 28) -#define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28) -#define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28) -#define IMTTBCR_SH1_MASK (3 << 28) -#define IMTTBCR_ORGN1_NC (0 << 26) -#define IMTTBCR_ORGN1_WB_WA (1 << 26) -#define IMTTBCR_ORGN1_WT (2 << 26) -#define IMTTBCR_ORGN1_WB (3 << 26) -#define IMTTBCR_ORGN1_MASK (3 << 26) -#define IMTTBCR_IRGN1_NC (0 << 24) -#define IMTTBCR_IRGN1_WB_WA (1 << 24) -#define IMTTBCR_IRGN1_WT (2 << 24) -#define IMTTBCR_IRGN1_WB (3 << 24) -#define IMTTBCR_IRGN1_MASK (3 << 24) -#define IMTTBCR_TSZ1_MASK (0x1f << 16) -#define IMTTBCR_TSZ1_SHIFT 16 -#define IMTTBCR_SH0_NON_SHAREABLE (0 << 12) -#define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12) -#define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) -#define IMTTBCR_SH0_MASK (3 << 12) -#define IMTTBCR_ORGN0_NC (0 << 10) -#define IMTTBCR_ORGN0_WB_WA (1 << 10) -#define IMTTBCR_ORGN0_WT (2 << 10) -#define IMTTBCR_ORGN0_WB (3 << 10) -#define IMTTBCR_ORGN0_MASK (3 << 10) -#define IMTTBCR_IRGN0_NC (0 << 8) -#define IMTTBCR_IRGN0_WB_WA (1 << 8) -#define IMTTBCR_IRGN0_WT (2 << 8) -#define IMTTBCR_IRGN0_WB (3 << 8) -#define IMTTBCR_IRGN0_MASK (3 << 8) -#define IMTTBCR_SL0_LVL_2 (0 << 6) #define IMTTBCR_SL0_LVL_1 (1 << 6) #define IMTTBCR_TSZ0_MASK (0x1f << 0) #define IMTTBCR_TSZ0_SHIFT 0 @@ -228,18 +191,8 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMTTLBR0_TTBR_MASK (0xfffff << 12) #define IMTTUBR0 0x0014 #define IMTTUBR0_TTBR_MASK (0xff << 0) -#define IMTTLBR1 0x0018 -#define IMTTLBR1_TTBR_MASK (0xfffff << 12) -#define IMTTUBR1 0x001c -#define IMTTUBR1_TTBR_MASK (0xff << 0) =20 #define IMSTR 0x0020 -#define IMSTR_ERRLVL_MASK (3 << 12) -#define IMSTR_ERRLVL_SHIFT 12 -#define IMSTR_ERRCODE_TLB_FORMAT (1 << 8) -#define IMSTR_ERRCODE_ACCESS_PERM (4 << 8) -#define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8) -#define IMSTR_ERRCODE_MASK (7 << 8) #define IMSTR_MHIT (1 << 4) #define IMSTR_ABORT (1 << 2) #define IMSTR_PF (1 << 1) @@ -251,11 +204,7 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) #define IMUCTR0(n) (0x0300 + ((n) * 16)) #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) -#define IMUCTR_FIXADDEN (1U << 31) -#define IMUCTR_FIXADD_MASK (0xff << 16) -#define IMUCTR_FIXADD_SHIFT 16 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) -#define IMUCTR_TTSEL_PMB (8 << 4) #define IMUCTR_TTSEL_MASK (15 << 4) #define IMUCTR_TTSEL_SHIFT 4 #define IMUCTR_FLUSH (1 << 1) @@ -264,10 +213,6 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) #define IMUASID0(n) (0x0308 + ((n) * 16)) #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) -#define IMUASID_ASID8_MASK (0xff << 8) -#define IMUASID_ASID8_SHIFT 8 -#define IMUASID_ASID0_MASK (0xff << 0) -#define IMUASID_ASID0_SHIFT 0 =20 #define IMSAUXCTLR 0x0504 #define IMSAUXCTLR_S2PTE (1 << 3) --=20 2.7.4