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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6932 Subject: [Xen-devel] [RFC 1/2] arm, smmu: add support for iommu_fwspec functions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Brian Woods Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Modify the smmu driver so that it uses the iommu_fwspec helper functions. This means both ARM IOMMU drivers will both use the iommu_fwspec helper functions, making enabling generic device tree bindings in the SMMU driver much cleaner. Signed-off-by: Brian Woods --- RFC especially wanted on: - Check in device_tree.c. This is needed, otherwise it won't boot due to dev_iommu_fwspec_get(dev) being true and returning EEXIST. I'm not completely sure what type of check is best here. xen/drivers/passthrough/arm/smmu.c | 74 ++++++++++++++++++++++---------= ---- xen/drivers/passthrough/device_tree.c | 3 ++ 2 files changed, 49 insertions(+), 28 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index 94662a8..c5db5be 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -49,6 +49,7 @@ #include #include #include +#include #include =20 /* Xen: The below defines are redefined within the file. Undef it */ @@ -597,8 +598,7 @@ struct arm_smmu_smr { }; =20 struct arm_smmu_master_cfg { - int num_streamids; - u16 streamids[MAX_MASTER_STREAMIDS]; + struct iommu_fwspec *fwspec; struct arm_smmu_smr *smrs; }; =20 @@ -779,7 +779,7 @@ static int register_smmu_master(struct arm_smmu_device = *smmu, struct device *dev, struct of_phandle_args *masterspec) { - int i; + int i, ret =3D 0; struct arm_smmu_master *master; =20 master =3D find_smmu_master(smmu, masterspec->np); @@ -798,26 +798,37 @@ static int register_smmu_master(struct arm_smmu_devic= e *smmu, } =20 master =3D devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); - if (!master) + if (!master) { return -ENOMEM; + } + master->of_node =3D masterspec->np; + + ret =3D iommu_fwspec_init(&master->of_node->dev, smmu->dev); + if (ret) { + kfree(master); + return ret; + } + master->cfg.fwspec =3D dev_iommu_fwspec_get(&master->of_node->dev); =20 - master->of_node =3D masterspec->np; - master->cfg.num_streamids =3D masterspec->args_count; + /* adding the ids here */ + ret =3D iommu_fwspec_add_ids(&masterspec->np->dev, + masterspec->args, + masterspec->args_count); + if (ret) + return ret; =20 /* Xen: Let Xen know that the device is protected by an SMMU */ dt_device_set_protected(masterspec->np); =20 - for (i =3D 0; i < master->cfg.num_streamids; ++i) { - u16 streamid =3D masterspec->args[i]; - - if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && - (streamid >=3D smmu->num_mapping_groups)) { - dev_err(dev, - "stream ID for master device %s greater than maximum allowed (%d)\n", - masterspec->np->name, smmu->num_mapping_groups); - return -ERANGE; + if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) { + for (i =3D 0; i < master->cfg.fwspec->num_ids; ++i) { + if (masterspec->args[i] >=3D smmu->num_mapping_groups) { + dev_err(dev, + "stream ID for master device %s greater than maximum allowed (%d)\n", + masterspec->np->name, smmu->num_mapping_groups); + return -ERANGE; + } } - master->cfg.streamids[i] =3D streamid; } return insert_smmu_master(smmu, master); } @@ -1397,15 +1408,15 @@ static int arm_smmu_master_configure_smrs(struct ar= m_smmu_device *smmu, if (cfg->smrs) return -EEXIST; =20 - smrs =3D kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); + smrs =3D kmalloc_array(cfg->fwspec->num_ids, sizeof(*smrs), GFP_KERNEL); if (!smrs) { dev_err(smmu->dev, "failed to allocate %d SMRs\n", - cfg->num_streamids); + cfg->fwspec->num_ids); return -ENOMEM; } =20 /* Allocate the SMRs on the SMMU */ - for (i =3D 0; i < cfg->num_streamids; ++i) { + for (i =3D 0; i < cfg->fwspec->num_ids; ++i) { int idx =3D __arm_smmu_alloc_bitmap(smmu->smr_map, 0, smmu->num_mapping_groups); if (IS_ERR_VALUE(idx)) { @@ -1416,12 +1427,12 @@ static int arm_smmu_master_configure_smrs(struct ar= m_smmu_device *smmu, smrs[i] =3D (struct arm_smmu_smr) { .idx =3D idx, .mask =3D 0, /* We don't currently share SMRs */ - .id =3D cfg->streamids[i], + .id =3D cfg->fwspec->ids[i], }; } =20 /* It worked! Now, poke the actual hardware */ - for (i =3D 0; i < cfg->num_streamids; ++i) { + for (i =3D 0; i < cfg->fwspec->num_ids; ++i) { u32 reg =3D SMR_VALID | smrs[i].id << SMR_ID_SHIFT | smrs[i].mask << SMR_MASK_SHIFT; writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); @@ -1448,7 +1459,7 @@ static void arm_smmu_master_free_smrs(struct arm_smmu= _device *smmu, return; =20 /* Invalidate the SMRs before freeing back to the allocator */ - for (i =3D 0; i < cfg->num_streamids; ++i) { + for (i =3D 0; i < cfg->fwspec->num_ids; ++i) { u8 idx =3D smrs[i].idx; =20 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); @@ -1471,10 +1482,10 @@ static int arm_smmu_domain_add_master(struct arm_sm= mu_domain *smmu_domain, if (ret) return ret =3D=3D -EEXIST ? 0 : ret; =20 - for (i =3D 0; i < cfg->num_streamids; ++i) { + for (i =3D 0; i < cfg->fwspec->num_ids; ++i) { u32 idx, s2cr; =20 - idx =3D cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; + idx =3D cfg->smrs ? cfg->smrs[i].idx : cfg->fwspec->ids[i]; s2cr =3D S2CR_TYPE_TRANS | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); @@ -1499,8 +1510,8 @@ static void arm_smmu_domain_remove_master(struct arm_= smmu_domain *smmu_domain, * that it can be re-allocated immediately. * Xen: Unlike Linux, any access to non-configured stream will fault. */ - for (i =3D 0; i < cfg->num_streamids; ++i) { - u32 idx =3D cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; + for (i =3D 0; i < cfg->fwspec->num_ids; ++i) { + u32 idx =3D cfg->smrs ? cfg->smrs[i].idx : cfg->fwspec->ids[i]; =20 writel_relaxed(S2CR_TYPE_FAULT, gr0_base + ARM_SMMU_GR0_S2CR(idx)); @@ -1924,14 +1935,21 @@ static int arm_smmu_add_device(struct device *dev) ret =3D -ENOMEM; goto out_put_group; } + cfg->fwspec =3D kzalloc(sizeof(struct iommu_fwspec), GFP_KERNEL); + if (!cfg->fwspec) { + kfree(cfg); + ret =3D -ENOMEM; + goto out_put_group; + } + iommu_fwspec_init(dev, smmu->dev); =20 - cfg->num_streamids =3D 1; + cfg->fwspec->num_ids =3D 1; /* * Assume Stream ID =3D=3D Requester ID for now. * We need a way to describe the ID mappings in FDT. */ pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, - &cfg->streamids[0]); + &cfg->fwspec->ids[0]); releasefn =3D __arm_smmu_release_pci_iommudata; } else { struct arm_smmu_master *master; diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthroug= h/device_tree.c index 999b831..acf6b62 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -140,6 +140,9 @@ int iommu_add_dt_device(struct dt_device_node *np) if ( !ops ) return -EINVAL; =20 + if ( dt_device_is_protected(np) ) + return 0; + if ( dev_iommu_fwspec_get(dev) ) return -EEXIST; =20 --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel