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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id r8sm3497515lfc.39.2019.08.21.11.17.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Aug 2019 11:17:46 -0700 (PDT) X-Inumbo-ID: fae2103c-c43f-11e9-8980-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=mQ5Rpzq7aM64R/HD5Xc/vIfSvgZBK4XbNSWXhY8+S88=; b=KFMR40h8shRo0/XMsX3AscM7b8njOFRbgqFI9PIfiZCDgvU254geHqjRB6veEGggXN H91zIz/A+q0xVBOgxGIE+cdka4aAalxhVcrPpnCSAHZK20ewbY1KFE2RcmmUmHgzlfVB fSx7FPP4X+gdd7kIPEPYtSoUW9n+zimf9RLUhv9SuhSTxrIAjiqxbMJ/OeenNlIFxPvy o3CPMj+UicyCNmPbpicnROIRzmUImgI/3Cex0A1yDbQDllf7+8fCOE3cjhW10rA7eAba SPv5SDjTEFOx7HOVxI6LBII40xKk0snebDcnTk3PyZvOVuQlSQvjWUTibcCOhooQGmpV UO6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=mQ5Rpzq7aM64R/HD5Xc/vIfSvgZBK4XbNSWXhY8+S88=; b=qyaQqWfgSV4bAelm0e5615rdGuN0BwjqIK/T0nYW0vzDUeaLZP0nXV/5iiAG3kCvKv jRH34GtfUTQYt2aT3hUf9uPmjrJ4Vwr6L81PcBLMBr7J0aPMYS5UFc1Qtroqkzd0EeH3 VrCZtmac0b5GvdPKPmgtHgpm2nCJSjHs60+UIuO8Ahht6A1LbT1KVBjfzVDFVvEPnoP1 rwT4uaFFHgvFVq59rcisyJ4P4Zb0qXZZnxfz2KXoKgF0J1osSIuViTq2MMSt/2L0FmNe corYfMC88M92pXZ+5FdW+lnKN61lAePg2TPeMxEUBAwTU8uo8Kcf9XjwPkK8qMglka6L k5bg== X-Gm-Message-State: APjAAAUlO8o1WjgUpA6ELfdN8QjPJ0uO1uxOx9v8mmDP78KLoVtYzhz2 upe5/lmABHyEgql8vlAMOSDcU12/ X-Google-Smtp-Source: APXvYqyrRAOQeGJJ9KkRq0UbKY78bHRTRsPo3EUzn+KkuaZhRiaK5mwTGwjpMwKKdKf3nw3cOCRybg== X-Received: by 2002:a2e:884c:: with SMTP id z12mr1172651ljj.148.1566411467568; Wed, 21 Aug 2019 11:17:47 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Wed, 21 Aug 2019 21:17:24 +0300 Message-Id: <1566411444-7124-1-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 Subject: [Xen-devel] [PATCH] [RFC] xen/arm: Restrict "pa_range" according to the IOMMU requirements X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko There is a strict requirement for the IOMMU which wants to share the P2M table with the CPU. The maximum supported by the IOMMU Stage-2 input size must be greater or equal to the P2M IPA size. So, first initialize the IOMMU and gather the requirements and then initialize the P2M. In the P2M code, take into the account the IOMMU requirements and restrict "pa_range" if necessary. Signed-off-by: Oleksandr Tyshchenko --- CC: Julien Grall Why RFC? 1. Patch assumes that IPMMU support is already in. 2. Not sure for the SMMU. If there are no objections I will craft a proper patch. --- xen/arch/arm/p2m.c | 19 +++++++++++++++++-- xen/arch/arm/setup.c | 4 ++-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 20 +++++--------------- xen/drivers/passthrough/arm/smmu.c | 14 +++++++------- 4 files changed, 31 insertions(+), 26 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index c171568..1262ae9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -34,7 +34,7 @@ static unsigned int __read_mostly max_vmid =3D MAX_VMID_8= _BIT; =20 #define P2M_ROOT_PAGES (1<=3D 64 - pa_range_info[i].t0sz ) + pa_range =3D i; + else + break; + } + } + for_each_online_cpu ( cpu ) { const struct cpuinfo_arm *info =3D &cpu_data[cpu]; diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 51a6677..01cd83d 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -936,12 +936,12 @@ void __init start_xen(unsigned long boot_phys_offset, printk("Brought up %ld CPUs\n", (long)num_online_cpus()); /* TODO: smp_cpus_done(); */ =20 - setup_virt_paging(); - rc =3D iommu_setup(); if ( !iommu_enabled && rc !=3D -ENODEV ) panic("Couldn't configure correctly all the IOMMUs."); =20 + setup_virt_paging(); + do_initcalls(); =20 /* diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index ec543c3..0dc6351 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -526,6 +526,7 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_= domain *domain) * to TTBR0. Use 4KB page granule. Start page table walks at first lev= el. * Always bypass stage 1 translation. */ + ASSERT(p2m_ipa_bits <=3D IPMMU_MAX_P2M_IPA_BITS); tsz0 =3D (64 - p2m_ipa_bits) << IMTTBCR_TSZ0_SHIFT; ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | IMTTBCR_PMB | IMTTBCR_SL0_LVL_1 | tsz0); @@ -1314,23 +1315,12 @@ static __init int ipmmu_init(struct dt_device_node = *node, const void *data) return -ENODEV; } else - { /* - * As 4-level translation table is not supported in IPMMU, we need - * to check IPA size used for P2M table beforehand to be sure it is - * 3-level and the IPMMU will be able to use it. - * - * TODO: First initialize the IOMMU and gather the requirements and - * then initialize the P2M. In the P2M code, take into the account - * the IOMMU requirements and restrict "pa_range" if necessary. + * Set max Stage-2 input size supported by the IPMMU. We expect + * the P2M code will take into the account the IOMMU requirements = and + * restrict "pa_range" if necessary. */ - if ( IPMMU_MAX_P2M_IPA_BITS < p2m_ipa_bits ) - { - printk_once(XENLOG_ERR "ipmmu: P2M IPA size is not supported (= P2M=3D%u IPMMU=3D%u)!\n", - p2m_ipa_bits, IPMMU_MAX_P2M_IPA_BITS); - return -ENODEV; - } - } + p2m_ipa_bits =3D IPMMU_MAX_P2M_IPA_BITS; =20 ret =3D ipmmu_probe(node); if ( ret ) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index 8ae986a..9b3867d 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1110,6 +1110,7 @@ static void arm_smmu_init_context_bank(struct arm_smm= u_domain *smmu_domain) reg =3D TTBCR_TG0_64K; =20 if (!stage1) { + ASSERT(p2m_ipa_bits <=3D smmu->s2_input_size); reg |=3D (64 - smmu->s2_input_size) << TTBCR_T0SZ_SHIFT; =20 switch (smmu->s2_output_size) { @@ -2198,13 +2199,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smm= u_device *smmu) size =3D arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); smmu->s1_output_size =3D min_t(unsigned long, PHYS_MASK_SHIFT, size); =20 - /* Xen: Stage-2 input size has to match p2m_ipa_bits. */ - if (size < p2m_ipa_bits) { - dev_err(smmu->dev, - "P2M IPA size not supported (P2M=3D%u SMMU=3D%lu)!\n", - p2m_ipa_bits, size); - return -ENODEV; - } + /* + * Xen: Set max Stage-2 input size supported by the SMMU. We expect + * the P2M code will take into the account the IOMMU requirements and + * restrict "pa_range" if necessary. + */ + p2m_ipa_bits =3D size; smmu->s2_input_size =3D p2m_ipa_bits; #if 0 /* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */ --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel