From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177771; cv=none; d=zoho.com; s=zohoarc; b=H38ig8e05CxLqPY/ZhC8cQolE7Pmh2d+LcvkqtTXPNVtS9uw8+nQyGKYiCXlTd2UQTPPRID5w5HuY7NXYFGF7P8Tx+/94/5ClIsOMOVOQx8XE45z87jtkNnkrOhcDhGTiL8VZiJBssoV8prLPlDa8IICf2Nx7jc0ioHdhWa5JEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566177771; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bOhDf1dCFThRSX1RoCzdLW0O2wfbxpa9rnrlRwx4QiI=; b=M9JuQiivAdJUqaElvJ8x9xRfHJuu9nBNRjxG1ABb67DlPMa6zf6kNsGiZ1sBMg3dLYv8xs7lXoJWy2IiheM1JadP2kClM264N/9Y4LIbpNStVG3W4LT7trseDOOkMDiWXHJGe/sb6A0FCWy+S/QRp73eNrVujtD1g96OOuTByYc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1566177771417956.0230393859283; Sun, 18 Aug 2019 18:22:51 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMU-00013K-Tx; Mon, 19 Aug 2019 01:21:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMT-00012z-PF for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:21:29 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id ab9613b0-c21f-11e9-8be3-12813bfff9fa; Mon, 19 Aug 2019 01:21:29 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:21:28 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:27 -0700 X-Inumbo-ID: ab9613b0-c21f-11e9-8be3-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683825" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:14 +0800 Message-Id: <1566177928-19114-2-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v9 01/15] microcode/intel: extend microcode_update_match() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" to a more generic function. So that it can be used alone to check an update against the CPU signature and current update revision. Note that enum microcode_match_result will be used in common code (aka microcode.c), it has been placed in the common header. Signed-off-by: Chao Gao Reviewed-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- Changes in v9: - microcode_update_match() doesn't accept (sig, pf, rev) any longer. Hence, it won't be used to compare two arbitrary updates. - rewrite patch description Changes in v8: - make sure enough room for an extended header and signature array Changes in v6: - eliminate unnecessary type casting in microcode_update_match - check if a patch has an extend header Changes in v5: - constify the extended_signature - use named enum type for the return value of microcode_update_match --- xen/arch/x86/microcode_intel.c | 60 ++++++++++++++++++++++---------------= ---- xen/include/asm-x86/microcode.h | 6 +++++ 2 files changed, 39 insertions(+), 27 deletions(-) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 22fdeca..c185b5c 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -134,14 +134,39 @@ static int collect_cpu_info(unsigned int cpu_num, str= uct cpu_signature *csig) return 0; } =20 -static inline int microcode_update_match( - unsigned int cpu_num, const struct microcode_header_intel *mc_header, - int sig, int pf) +/* Check an update against the CPU signature and current update revision */ +static enum microcode_match_result microcode_update_match( + const struct microcode_header_intel *mc_header, unsigned int cpu) { - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu_num); - - return (sigmatch(sig, uci->cpu_sig.sig, pf, uci->cpu_sig.pf) && - (mc_header->rev > uci->cpu_sig.rev)); + const struct extended_sigtable *ext_header; + const struct extended_signature *ext_sig; + unsigned int i; + struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + unsigned int sig =3D uci->cpu_sig.sig; + unsigned int pf =3D uci->cpu_sig.pf; + unsigned int rev =3D uci->cpu_sig.rev; + unsigned long data_size =3D get_datasize(mc_header); + const void *end =3D (const void *)mc_header + get_totalsize(mc_header); + + if ( sigmatch(sig, mc_header->sig, pf, mc_header->pf) ) + return (mc_header->rev > rev) ? NEW_UCODE : OLD_UCODE; + + ext_header =3D (const void *)(mc_header + 1) + data_size; + ext_sig =3D (const void *)(ext_header + 1); + + /* + * Make sure there is enough space to hold an extended header and enou= gh + * array elements. + */ + if ( (end < (const void *)ext_sig) || + (end < (const void *)(ext_sig + ext_header->count)) ) + return MIS_UCODE; + + for ( i =3D 0; i < ext_header->count; i++ ) + if ( sigmatch(sig, ext_sig[i].sig, pf, ext_sig[i].pf) ) + return (mc_header->rev > rev) ? NEW_UCODE : OLD_UCODE; + + return MIS_UCODE; } =20 static int microcode_sanity_check(void *mc) @@ -243,31 +268,12 @@ static int get_matching_microcode(const void *mc, uns= igned int cpu) { struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); const struct microcode_header_intel *mc_header =3D mc; - const struct extended_sigtable *ext_header; unsigned long total_size =3D get_totalsize(mc_header); - int ext_sigcount, i; - struct extended_signature *ext_sig; void *new_mc; =20 - if ( microcode_update_match(cpu, mc_header, - mc_header->sig, mc_header->pf) ) - goto find; - - if ( total_size <=3D (get_datasize(mc_header) + MC_HEADER_SIZE) ) + if ( microcode_update_match(mc, cpu) !=3D NEW_UCODE ) return 0; =20 - ext_header =3D mc + get_datasize(mc_header) + MC_HEADER_SIZE; - ext_sigcount =3D ext_header->count; - ext_sig =3D (void *)ext_header + EXT_HEADER_SIZE; - for ( i =3D 0; i < ext_sigcount; i++ ) - { - if ( microcode_update_match(cpu, mc_header, - ext_sig->sig, ext_sig->pf) ) - goto find; - ext_sig++; - } - return 0; - find: pr_debug("microcode: CPU%d found a matching microcode update with" " version %#x (current=3D%#x)\n", cpu, mc_header->rev, uci->cpu_sig.rev); diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 23ea954..882f560 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -3,6 +3,12 @@ =20 #include =20 +enum microcode_match_result { + OLD_UCODE, /* signature matched, but revision id is older or equal */ + NEW_UCODE, /* signature matched, but revision id is newer */ + MIS_UCODE, /* signature mismatched */ +}; + struct cpu_signature; struct ucode_cpu_info; =20 --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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18 Aug 2019 18:21:31 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:29 -0700 X-Inumbo-ID: ad189712-c21f-11e9-8be3-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683837" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:15 +0800 Message-Id: <1566177928-19114-3-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 02/15] microcode/amd: fix memory leak X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Two buffers, '->equiv_cpu_table' and '->mpb', inside 'mc_amd' might be allocated and in the error-handing path they are not freed properly. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- Changes in v9: - use xzalloc() to get rid of explicitly initializing some fields to NULL/0. changes in v8: - new - it is found by reading code. No test is done. --- xen/arch/x86/microcode_amd.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 7a854c0..3069784 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -425,7 +425,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, goto out; } =20 - mc_amd =3D xmalloc(struct microcode_amd); + mc_amd =3D xzalloc(struct microcode_amd); if ( !mc_amd ) { printk(KERN_ERR "microcode: Cannot allocate memory for microcode p= atch\n"); @@ -479,6 +479,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, =20 if ( error ) { + xfree(mc_amd->equiv_cpu_table); xfree(mc_amd); goto out; } @@ -491,8 +492,6 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, * It's possible the data file has multiple matching ucode, * lets keep searching till the latest version */ - mc_amd->mpb =3D NULL; - mc_amd->mpb_size =3D 0; last_offset =3D offset; while ( (error =3D get_ucode_from_buffer_amd(mc_amd, buf, bufsize, &offset)) =3D=3D 0 ) @@ -549,11 +548,13 @@ static int cpu_request_microcode(unsigned int cpu, co= nst void *buf, =20 if ( save_error ) { - xfree(mc_amd); uci->mc.mc_amd =3D mc_old; + mc_old =3D mc_amd; } - else - xfree(mc_old); + + xfree(mc_old->mpb); + xfree(mc_old->equiv_cpu_table); + xfree(mc_old); =20 out: #if CONFIG_HVM --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1566177764644196.38746932529966; Sun, 18 Aug 2019 18:22:44 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMa-000145-Ef; Mon, 19 Aug 2019 01:21:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMY-00013u-P9 for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:21:34 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id aeb07cac-c21f-11e9-8be3-12813bfff9fa; Mon, 19 Aug 2019 01:21:34 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:21:34 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:32 -0700 X-Inumbo-ID: aeb07cac-c21f-11e9-8be3-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683854" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:16 +0800 Message-Id: <1566177928-19114-4-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 03/15] microcode/amd: distinguish old and mismatched ucode in microcode_fits() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Sometimes, an ucode with a level lower than or equal to current CPU's patch level is useful. For example, to work around a broken bios which only loads ucode for BSP, when BSP parses an ucode blob during bootup, it is better to save an ucode with lower or equal level for APs No functional change is made in this patch. But following patch would handle "old ucode" and "mismatched ucode" separately. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- Changes in v8: - new --- xen/arch/x86/microcode_amd.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 3069784..3db3555 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -152,8 +152,8 @@ static bool_t find_equiv_cpu_id(const struct equiv_cpu_= entry *equiv_cpu_table, return 0; } =20 -static bool_t microcode_fits(const struct microcode_amd *mc_amd, - unsigned int cpu) +static enum microcode_match_result microcode_fits( + const struct microcode_amd *mc_amd, unsigned int cpu) { struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); const struct microcode_header_amd *mc_header =3D mc_amd->mpb; @@ -167,27 +167,27 @@ static bool_t microcode_fits(const struct microcode_a= md *mc_amd, current_cpu_id =3D cpuid_eax(0x00000001); =20 if ( !find_equiv_cpu_id(equiv_cpu_table, current_cpu_id, &equiv_cpu_id= ) ) - return 0; + return MIS_UCODE; =20 if ( (mc_header->processor_rev_id) !=3D equiv_cpu_id ) - return 0; + return MIS_UCODE; =20 if ( !verify_patch_size(mc_amd->mpb_size) ) { pr_debug("microcode: patch size mismatch\n"); - return 0; + return MIS_UCODE; } =20 if ( mc_header->patch_id <=3D uci->cpu_sig.rev ) { pr_debug("microcode: patch is already at required level or greater= .\n"); - return 0; + return OLD_UCODE; } =20 pr_debug("microcode: CPU%d found a matching microcode update with vers= ion %#x (current=3D%#x)\n", cpu, mc_header->patch_id, uci->cpu_sig.rev); =20 - return 1; + return NEW_UCODE; } =20 static int apply_microcode(unsigned int cpu) @@ -496,7 +496,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, while ( (error =3D get_ucode_from_buffer_amd(mc_amd, buf, bufsize, &offset)) =3D=3D 0 ) { - if ( microcode_fits(mc_amd, cpu) ) + if ( microcode_fits(mc_amd, cpu) =3D=3D NEW_UCODE ) { error =3D apply_microcode(cpu); if ( error ) @@ -576,7 +576,7 @@ static int microcode_resume_match(unsigned int cpu, con= st void *mc) struct microcode_amd *mc_amd =3D uci->mc.mc_amd; const struct microcode_amd *src =3D mc; =20 - if ( !microcode_fits(src, cpu) ) + if ( microcode_fits(src, cpu) !=3D NEW_UCODE ) return 0; =20 if ( src !=3D mc_amd ) --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177769; cv=none; d=zoho.com; s=zohoarc; b=N/gyROpaXyhcfvH79MrDDs+vgAFP0QRLmd739XlGtPGb5orCzEkMn3bT+ZfTNDbM8CTtOfIvUwJGGHOP4YG+qaq5Uo9Jg++FtZJuEuTMUv5k2KcgdrCmGgEPEBskOMHE/HxMX3iIsYkX0SP3DdaAUHOXZofWVQwxeOUerf1Bx5I= ARC-Message-Signature: i=1; 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Mon, 19 Aug 2019 01:21:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMb-00014w-Sg for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:21:37 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id b056ee6a-c21f-11e9-8be3-12813bfff9fa; Mon, 19 Aug 2019 01:21:37 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:21:36 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:34 -0700 X-Inumbo-ID: b056ee6a-c21f-11e9-8be3-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683865" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:17 +0800 Message-Id: <1566177928-19114-5-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 04/15] microcode: introduce a global cache of ucode patch X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" to replace the current per-cpu cache 'uci->mc'. With the assumption that all CPUs in the system have the same signature (family, model, stepping and 'pf'), one microcode update matches with one cpu should match with others. Having multiple microcode revisions on different cpus would cause system unstable and should be avoided. Hence, caching only one microcode update is good enough for all cases. Introduce a global variable, microcode_cache, to store the newest matching microcode update. Whenever we get a new valid microcode update, its revision id is compared against that of the microcode update to determine whether the "microcode_cache" needs to be replaced. And this global cache is loaded to cpu in apply_microcode(). All operations on the cache is protected by 'microcode_mutex'. Note that I deliberately avoid touching the old per-cpu cache ('uci->mc') as I am going to remove it completely in the following patches. We copy everything to create the new cache blob to avoid reusing some buffers previously allocated for the old per-cpu cache. It is not so efficient, but it is already corrected by a patch later in this series. Signed-off-by: Chao Gao Reviewed-by: Roger Pau Monn=C3=A9 --- Changes in v9: - on Intel side, ->compare_patch just checks the patch revision number. - explain why all buffers are copied in alloc_microcode_patch() in patch description. Changes in v8: - Free generic wrapper struct in general code - Try to update cache as long as a patch covers current cpu. Previsouly, cache is updated only if the patch is newer than current update revision in the CPU. The small difference can work around a broken bios which only applies microcode update to BSP and software has to apply the same update to other CPUs. Changes in v7: - reworked to cache only one microcode patch rather than a list of microcode patches. --- xen/arch/x86/microcode.c | 39 ++++++++++++++++++ xen/arch/x86/microcode_amd.c | 90 +++++++++++++++++++++++++++++++++++++= ---- xen/arch/x86/microcode_intel.c | 73 ++++++++++++++++++++++++++------- xen/include/asm-x86/microcode.h | 17 ++++++++ 4 files changed, 197 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 421d57e..0ecd2fd 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -61,6 +61,9 @@ static struct ucode_mod_blob __initdata ucode_blob; */ static bool_t __initdata ucode_scan; =20 +/* Protected by microcode_mutex */ +static struct microcode_patch *microcode_cache; + void __init microcode_set_module(unsigned int idx) { ucode_mod_idx =3D idx; @@ -262,6 +265,42 @@ int microcode_resume_cpu(unsigned int cpu) return err; } =20 +void microcode_free_patch(struct microcode_patch *microcode_patch) +{ + microcode_ops->free_patch(microcode_patch->mc); + xfree(microcode_patch); +} + +const struct microcode_patch *microcode_get_cache(void) +{ + ASSERT(spin_is_locked(µcode_mutex)); + + return microcode_cache; +} + +/* Return true if cache gets updated. Otherwise, return false */ +bool microcode_update_cache(struct microcode_patch *patch) +{ + + ASSERT(spin_is_locked(µcode_mutex)); + + if ( !microcode_cache ) + microcode_cache =3D patch; + else if ( microcode_ops->compare_patch(patch, + microcode_cache) =3D=3D NEW_UCO= DE ) + { + microcode_free_patch(microcode_cache); + microcode_cache =3D patch; + } + else + { + microcode_free_patch(patch); + return false; + } + + return true; +} + static int microcode_update_cpu(const void *buf, size_t size) { int err; diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 3db3555..30129ca 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -190,24 +190,83 @@ static enum microcode_match_result microcode_fits( return NEW_UCODE; } =20 +static bool match_cpu(const struct microcode_patch *patch) +{ + if ( !patch ) + return false; + return microcode_fits(patch->mc_amd, smp_processor_id()) =3D=3D NEW_UC= ODE; +} + +static struct microcode_patch *alloc_microcode_patch( + const struct microcode_amd *mc_amd) +{ + struct microcode_patch *microcode_patch =3D xmalloc(struct microcode_p= atch); + struct microcode_amd *cache =3D xmalloc(struct microcode_amd); + void *mpb =3D xmalloc_bytes(mc_amd->mpb_size); + struct equiv_cpu_entry *equiv_cpu_table =3D + xmalloc_bytes(mc_amd->equiv_cpu_table_size= ); + + if ( !microcode_patch || !cache || !mpb || !equiv_cpu_table ) + { + xfree(microcode_patch); + xfree(cache); + xfree(mpb); + xfree(equiv_cpu_table); + return ERR_PTR(-ENOMEM); + } + + memcpy(mpb, mc_amd->mpb, mc_amd->mpb_size); + cache->mpb =3D mpb; + cache->mpb_size =3D mc_amd->mpb_size; + memcpy(equiv_cpu_table, mc_amd->equiv_cpu_table, + mc_amd->equiv_cpu_table_size); + cache->equiv_cpu_table =3D equiv_cpu_table; + cache->equiv_cpu_table_size =3D mc_amd->equiv_cpu_table_size; + microcode_patch->mc_amd =3D cache; + + return microcode_patch; +} + +static void free_patch(void *mc) +{ + struct microcode_amd *mc_amd =3D mc; + + xfree(mc_amd->equiv_cpu_table); + xfree(mc_amd->mpb); + xfree(mc_amd); +} + +static enum microcode_match_result compare_patch( + const struct microcode_patch *new, const struct microcode_patch *old) +{ + const struct microcode_amd *new_mc =3D new->mc_amd; + const struct microcode_header_amd *new_header =3D new_mc->mpb; + const struct microcode_amd *old_mc =3D old->mc_amd; + const struct microcode_header_amd *old_header =3D old_mc->mpb; + + if ( new_header->processor_rev_id =3D=3D old_header->processor_rev_id ) + return (new_header->patch_id > old_header->patch_id) ? + NEW_UCODE : OLD_UCODE; + + return MIS_UCODE; +} + static int apply_microcode(unsigned int cpu) { unsigned long flags; struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); uint32_t rev; - struct microcode_amd *mc_amd =3D uci->mc.mc_amd; - struct microcode_header_amd *hdr; int hw_err; + const struct microcode_header_amd *hdr; + const struct microcode_patch *patch =3D microcode_get_cache(); =20 /* We should bind the task to the CPU */ BUG_ON(raw_smp_processor_id() !=3D cpu); =20 - if ( mc_amd =3D=3D NULL ) + if ( !match_cpu(patch) ) return -EINVAL; =20 - hdr =3D mc_amd->mpb; - if ( hdr =3D=3D NULL ) - return -EINVAL; + hdr =3D patch->mc_amd->mpb; =20 spin_lock_irqsave(µcode_update_lock, flags); =20 @@ -496,7 +555,21 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, while ( (error =3D get_ucode_from_buffer_amd(mc_amd, buf, bufsize, &offset)) =3D=3D 0 ) { - if ( microcode_fits(mc_amd, cpu) =3D=3D NEW_UCODE ) + struct microcode_patch *new_patch =3D alloc_microcode_patch(mc_amd= ); + + if ( IS_ERR(new_patch) ) + { + error =3D PTR_ERR(new_patch); + break; + } + + /* Update cache if this patch covers current CPU */ + if ( microcode_fits(new_patch->mc_amd, cpu) !=3D MIS_UCODE ) + microcode_update_cache(new_patch); + else + microcode_free_patch(new_patch); + + if ( match_cpu(microcode_get_cache()) ) { error =3D apply_microcode(cpu); if ( error ) @@ -640,6 +713,9 @@ static const struct microcode_ops microcode_amd_ops =3D= { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, .start_update =3D start_update, + .free_patch =3D free_patch, + .compare_patch =3D compare_patch, + .match_cpu =3D match_cpu, }; =20 int __init microcode_init_amd(void) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index c185b5c..14485dc 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -259,6 +259,31 @@ static int microcode_sanity_check(void *mc) return 0; } =20 +static bool match_cpu(const struct microcode_patch *patch) +{ + if ( !patch ) + return false; + + return microcode_update_match(&patch->mc_intel->hdr, + smp_processor_id()) =3D=3D NEW_UCODE; +} + +static void free_patch(void *mc) +{ + xfree(mc); +} + +/* + * Both patches to compare are supposed to be applicable to local CPU. + * Just compare the revision number. + */ +static enum microcode_match_result compare_patch( + const struct microcode_patch *new, const struct microcode_patch *old) +{ + return (new->mc_intel->hdr.rev > old->mc_intel->hdr.rev) ? NEW_UCODE : + OLD_UCODE; +} + /* * return 0 - no update found * return 1 - found update @@ -269,10 +294,26 @@ static int get_matching_microcode(const void *mc, uns= igned int cpu) struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); const struct microcode_header_intel *mc_header =3D mc; unsigned long total_size =3D get_totalsize(mc_header); - void *new_mc; + void *new_mc =3D xmalloc_bytes(total_size); + struct microcode_patch *new_patch =3D xmalloc(struct microcode_patch); =20 - if ( microcode_update_match(mc, cpu) !=3D NEW_UCODE ) + if ( !new_patch || !new_mc ) + { + xfree(new_patch); + xfree(new_mc); + return -ENOMEM; + } + memcpy(new_mc, mc, total_size); + new_patch->mc_intel =3D new_mc; + + /* Make sure that this patch covers current CPU */ + if ( microcode_update_match(mc, cpu) =3D=3D MIS_UCODE ) + { + microcode_free_patch(new_patch); return 0; + } + + microcode_update_cache(new_patch); =20 pr_debug("microcode: CPU%d found a matching microcode update with" " version %#x (current=3D%#x)\n", @@ -297,18 +338,22 @@ static int apply_microcode(unsigned int cpu) unsigned int val[2]; unsigned int cpu_num =3D raw_smp_processor_id(); struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu_num); + const struct microcode_intel *mc_intel; + const struct microcode_patch *patch =3D microcode_get_cache(); =20 /* We should bind the task to the CPU */ BUG_ON(cpu_num !=3D cpu); =20 - if ( uci->mc.mc_intel =3D=3D NULL ) + if ( !match_cpu(patch) ) return -EINVAL; =20 + mc_intel =3D patch->mc_intel; + /* serialize access to the physical write to MSR 0x79 */ spin_lock_irqsave(µcode_update_lock, flags); =20 /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)uci->mc.mc_intel->bits); + wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL); =20 /* As documented in the SDM: Do a CPUID 1 here */ @@ -319,19 +364,17 @@ static int apply_microcode(unsigned int cpu) val[1] =3D (uint32_t)(msr_content >> 32); =20 spin_unlock_irqrestore(µcode_update_lock, flags); - if ( val[1] !=3D uci->mc.mc_intel->hdr.rev ) + if ( val[1] !=3D mc_intel->hdr.rev ) { printk(KERN_ERR "microcode: CPU%d update from revision " "%#x to %#x failed. Resulting revision is %#x.\n", cpu_num, - uci->cpu_sig.rev, uci->mc.mc_intel->hdr.rev, val[1]); + uci->cpu_sig.rev, mc_intel->hdr.rev, val[1]); return -EIO; } printk(KERN_INFO "microcode: CPU%d updated from revision " "%#x to %#x, date =3D %04x-%02x-%02x \n", - cpu_num, uci->cpu_sig.rev, val[1], - uci->mc.mc_intel->hdr.year, - uci->mc.mc_intel->hdr.month, - uci->mc.mc_intel->hdr.day); + cpu_num, uci->cpu_sig.rev, val[1], mc_intel->hdr.year, + mc_intel->hdr.month, mc_intel->hdr.day); uci->cpu_sig.rev =3D val[1]; =20 return 0; @@ -371,7 +414,6 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, long offset =3D 0; int error =3D 0; void *mc; - unsigned int matching_count =3D 0; =20 /* We should bind the task to the CPU */ BUG_ON(cpu !=3D raw_smp_processor_id()); @@ -389,10 +431,8 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, * lets keep searching till the latest version */ if ( error =3D=3D 1 ) - { - matching_count++; error =3D 0; - } + xfree(mc); } if ( offset > 0 ) @@ -400,7 +440,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, if ( offset < 0 ) error =3D offset; =20 - if ( !error && matching_count ) + if ( !error && match_cpu(microcode_get_cache()) ) error =3D apply_microcode(cpu); =20 return error; @@ -416,6 +456,9 @@ static const struct microcode_ops microcode_intel_ops = =3D { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, + .free_patch =3D free_patch, + .compare_patch =3D compare_patch, + .match_cpu =3D match_cpu, }; =20 int __init microcode_init_intel(void) diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 882f560..42949b1 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -12,6 +12,14 @@ enum microcode_match_result { struct cpu_signature; struct ucode_cpu_info; =20 +struct microcode_patch { + union { + struct microcode_intel *mc_intel; + struct microcode_amd *mc_amd; + void *mc; + }; +}; + struct microcode_ops { int (*microcode_resume_match)(unsigned int cpu, const void *mc); int (*cpu_request_microcode)(unsigned int cpu, const void *buf, @@ -19,6 +27,11 @@ struct microcode_ops { int (*collect_cpu_info)(unsigned int cpu, struct cpu_signature *csig); int (*apply_microcode)(unsigned int cpu); int (*start_update)(void); + void (*free_patch)(void *mc); + bool (*match_cpu)(const struct microcode_patch *patch); + enum microcode_match_result (*compare_patch)( + const struct microcode_patch *new, + const struct microcode_patch *old); }; =20 struct cpu_signature { @@ -39,4 +52,8 @@ struct ucode_cpu_info { DECLARE_PER_CPU(struct ucode_cpu_info, ucode_cpu_info); extern const struct microcode_ops *microcode_ops; =20 +const struct microcode_patch *microcode_get_cache(void); +bool microcode_update_cache(struct microcode_patch *patch); +void microcode_free_patch(struct microcode_patch *patch); + #endif /* ASM_X86__MICROCODE_H */ --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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18 Aug 2019 18:21:39 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:37 -0700 X-Inumbo-ID: b1c1ff7e-c21f-11e9-8be3-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683877" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:18 +0800 Message-Id: <1566177928-19114-6-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 05/15] microcode: clean up microcode_resume_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Previously, a per-cpu ucode cache is maintained. Then each CPU had one per-cpu update cache and there might be multiple versions of microcode. Thus microcode_resume_cpu tried best to update microcode by loading every update cache until a successful load. But now the cache struct is simplified a lot and only a single ucode is cached. a single invocation of ->apply_microcode() would load the cache and make microcode updated. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- changes in v8: - new - separated from the following patch --- xen/arch/x86/microcode.c | 40 ++--------------------------------- xen/arch/x86/microcode_amd.c | 47 -------------------------------------= ---- xen/arch/x86/microcode_intel.c | 6 ------ xen/include/asm-x86/microcode.h | 1 - 4 files changed, 2 insertions(+), 92 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 0ecd2fd..ca5ee37 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -215,8 +215,6 @@ int microcode_resume_cpu(unsigned int cpu) { int err; struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); - struct cpu_signature nsig; - unsigned int cpu2; =20 if ( !microcode_ops ) return 0; @@ -224,42 +222,8 @@ int microcode_resume_cpu(unsigned int cpu) spin_lock(µcode_mutex); =20 err =3D microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - if ( err ) - { - __microcode_fini_cpu(cpu); - spin_unlock(µcode_mutex); - return err; - } - - if ( uci->mc.mc_valid ) - { - err =3D microcode_ops->microcode_resume_match(cpu, uci->mc.mc_vali= d); - if ( err >=3D 0 ) - { - if ( err ) - err =3D microcode_ops->apply_microcode(cpu); - spin_unlock(µcode_mutex); - return err; - } - } - - nsig =3D uci->cpu_sig; - __microcode_fini_cpu(cpu); - uci->cpu_sig =3D nsig; - - err =3D -EIO; - for_each_online_cpu ( cpu2 ) - { - uci =3D &per_cpu(ucode_cpu_info, cpu2); - if ( uci->mc.mc_valid && - microcode_ops->microcode_resume_match(cpu, uci->mc.mc_valid) = > 0 ) - { - err =3D microcode_ops->apply_microcode(cpu); - break; - } - } - - __microcode_fini_cpu(cpu); + if ( likely(!err) ) + err =3D microcode_ops->apply_microcode(cpu); spin_unlock(µcode_mutex); =20 return err; diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 30129ca..b351894 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -643,52 +643,6 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, return error; } =20 -static int microcode_resume_match(unsigned int cpu, const void *mc) -{ - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); - struct microcode_amd *mc_amd =3D uci->mc.mc_amd; - const struct microcode_amd *src =3D mc; - - if ( microcode_fits(src, cpu) !=3D NEW_UCODE ) - return 0; - - if ( src !=3D mc_amd ) - { - if ( mc_amd ) - { - xfree(mc_amd->equiv_cpu_table); - xfree(mc_amd->mpb); - xfree(mc_amd); - } - - mc_amd =3D xmalloc(struct microcode_amd); - uci->mc.mc_amd =3D mc_amd; - if ( !mc_amd ) - return -ENOMEM; - mc_amd->equiv_cpu_table =3D xmalloc_bytes(src->equiv_cpu_table_siz= e); - if ( !mc_amd->equiv_cpu_table ) - goto err1; - mc_amd->mpb =3D xmalloc_bytes(src->mpb_size); - if ( !mc_amd->mpb ) - goto err2; - - mc_amd->equiv_cpu_table_size =3D src->equiv_cpu_table_size; - mc_amd->mpb_size =3D src->mpb_size; - memcpy(mc_amd->mpb, src->mpb, src->mpb_size); - memcpy(mc_amd->equiv_cpu_table, src->equiv_cpu_table, - src->equiv_cpu_table_size); - } - - return 1; - -err2: - xfree(mc_amd->equiv_cpu_table); -err1: - xfree(mc_amd); - uci->mc.mc_amd =3D NULL; - return -ENOMEM; -} - static int start_update(void) { #if CONFIG_HVM @@ -708,7 +662,6 @@ static int start_update(void) } =20 static const struct microcode_ops microcode_amd_ops =3D { - .microcode_resume_match =3D microcode_resume_match, .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 14485dc..58eb186 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -446,13 +446,7 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, return error; } =20 -static int microcode_resume_match(unsigned int cpu, const void *mc) -{ - return get_matching_microcode(mc, cpu); -} - static const struct microcode_ops microcode_intel_ops =3D { - .microcode_resume_match =3D microcode_resume_match, .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 42949b1..3238743 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -21,7 +21,6 @@ struct microcode_patch { }; =20 struct microcode_ops { - int (*microcode_resume_match)(unsigned int cpu, const void *mc); int (*cpu_request_microcode)(unsigned int cpu, const void *buf, size_t size); int (*collect_cpu_info)(unsigned int cpu, struct cpu_signature *csig); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177770; cv=none; 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d="scan'208";a="261683886" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:19 +0800 Message-Id: <1566177928-19114-7-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 06/15] microcode: remove struct ucode_cpu_info X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Remove the per-cpu cache field in struct ucode_cpu_info since it has been replaced by a global cache. It would leads to only one field remaining in ucode_cpu_info. Then, this struct is removed and the remaining field (cpu signature) is stored in per-cpu area. The cpu status notifier is also removed. It was used to free the "mc" field to avoid memory leak. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- Changes in v9: - rebase and fix conflict Changes in v8: - split microcode_resume_cpu() cleanup to a separate patch. Changes in v6: - remove the whole struct ucode_cpu_info instead of the per-cpu cache in it. --- xen/arch/x86/apic.c | 2 +- xen/arch/x86/microcode.c | 57 +++++++------------------------------= --- xen/arch/x86/microcode_amd.c | 58 +++++++++++--------------------------= ---- xen/arch/x86/microcode_intel.c | 28 +++++++------------- xen/arch/x86/spec_ctrl.c | 2 +- xen/include/asm-x86/microcode.h | 12 +-------- 6 files changed, 36 insertions(+), 123 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index 9c3c998..ae1f1e9 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1193,7 +1193,7 @@ static void __init check_deadline_errata(void) else rev =3D (unsigned long)m->driver_data; =20 - if ( this_cpu(ucode_cpu_info).cpu_sig.rev >=3D rev ) + if ( this_cpu(cpu_sig).rev >=3D rev ) return; =20 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE); diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index ca5ee37..552e7fe 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -187,7 +187,7 @@ const struct microcode_ops *microcode_ops; =20 static DEFINE_SPINLOCK(microcode_mutex); =20 -DEFINE_PER_CPU(struct ucode_cpu_info, ucode_cpu_info); +DEFINE_PER_CPU(struct cpu_signature, cpu_sig); =20 struct microcode_info { unsigned int cpu; @@ -196,32 +196,17 @@ struct microcode_info { char buffer[1]; }; =20 -static void __microcode_fini_cpu(unsigned int cpu) -{ - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); - - xfree(uci->mc.mc_valid); - memset(uci, 0, sizeof(*uci)); -} - -static void microcode_fini_cpu(unsigned int cpu) -{ - spin_lock(µcode_mutex); - __microcode_fini_cpu(cpu); - spin_unlock(µcode_mutex); -} - int microcode_resume_cpu(unsigned int cpu) { int err; - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); =20 if ( !microcode_ops ) return 0; =20 spin_lock(µcode_mutex); =20 - err =3D microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + err =3D microcode_ops->collect_cpu_info(cpu, sig); if ( likely(!err) ) err =3D microcode_ops->apply_microcode(cpu); spin_unlock(µcode_mutex); @@ -269,16 +254,13 @@ static int microcode_update_cpu(const void *buf, size= _t size) { int err; unsigned int cpu =3D smp_processor_id(); - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); =20 spin_lock(µcode_mutex); =20 - err =3D microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + err =3D microcode_ops->collect_cpu_info(cpu, sig); if ( likely(!err) ) err =3D microcode_ops->cpu_request_microcode(cpu, buf, size); - else - __microcode_fini_cpu(cpu); - spin_unlock(µcode_mutex); =20 return err; @@ -365,29 +347,10 @@ static int __init microcode_init(void) } __initcall(microcode_init); =20 -static int microcode_percpu_callback( - struct notifier_block *nfb, unsigned long action, void *hcpu) -{ - unsigned int cpu =3D (unsigned long)hcpu; - - switch ( action ) - { - case CPU_DEAD: - microcode_fini_cpu(cpu); - break; - } - - return NOTIFY_DONE; -} - -static struct notifier_block microcode_percpu_nfb =3D { - .notifier_call =3D microcode_percpu_callback, -}; - int __init early_microcode_update_cpu(bool start_update) { unsigned int cpu =3D smp_processor_id(); - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); int rc =3D 0; void *data =3D NULL; size_t len; @@ -406,7 +369,7 @@ int __init early_microcode_update_cpu(bool start_update) data =3D bootstrap_map(&ucode_mod); } =20 - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + microcode_ops->collect_cpu_info(cpu, sig); =20 if ( data ) { @@ -425,7 +388,7 @@ int __init early_microcode_update_cpu(bool start_update) int __init early_microcode_init(void) { unsigned int cpu =3D smp_processor_id(); - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); int rc; =20 rc =3D microcode_init_intel(); @@ -438,12 +401,10 @@ int __init early_microcode_init(void) =20 if ( microcode_ops ) { - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + microcode_ops->collect_cpu_info(cpu, sig); =20 if ( ucode_mod.mod_end || ucode_blob.size ) rc =3D early_microcode_update_cpu(true); - - register_cpu_notifier(µcode_percpu_nfb); } =20 return rc; diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index b351894..9e4ec73 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -155,7 +155,7 @@ static bool_t find_equiv_cpu_id(const struct equiv_cpu_= entry *equiv_cpu_table, static enum microcode_match_result microcode_fits( const struct microcode_amd *mc_amd, unsigned int cpu) { - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + const struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_header_amd *mc_header =3D mc_amd->mpb; const struct equiv_cpu_entry *equiv_cpu_table =3D mc_amd->equiv_cpu_ta= ble; unsigned int current_cpu_id; @@ -178,14 +178,14 @@ static enum microcode_match_result microcode_fits( return MIS_UCODE; } =20 - if ( mc_header->patch_id <=3D uci->cpu_sig.rev ) + if ( mc_header->patch_id <=3D sig->rev ) { pr_debug("microcode: patch is already at required level or greater= .\n"); return OLD_UCODE; } =20 pr_debug("microcode: CPU%d found a matching microcode update with vers= ion %#x (current=3D%#x)\n", - cpu, mc_header->patch_id, uci->cpu_sig.rev); + cpu, mc_header->patch_id, sig->rev); =20 return NEW_UCODE; } @@ -254,9 +254,9 @@ static enum microcode_match_result compare_patch( static int apply_microcode(unsigned int cpu) { unsigned long flags; - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); uint32_t rev; int hw_err; + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_header_amd *hdr; const struct microcode_patch *patch =3D microcode_get_cache(); =20 @@ -292,9 +292,9 @@ static int apply_microcode(unsigned int cpu) } =20 printk(KERN_WARNING "microcode: CPU%d updated from revision %#x to %#x= \n", - cpu, uci->cpu_sig.rev, hdr->patch_id); + cpu, sig->rev, hdr->patch_id); =20 - uci->cpu_sig.rev =3D rev; + sig->rev =3D rev; =20 return 0; } @@ -440,14 +440,14 @@ static bool_t check_final_patch_levels(unsigned int c= pu) * any of the 'final_levels', then we should not update the microcode * patch on the cpu as system will hang otherwise. */ - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + const struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); unsigned int i; =20 if ( boot_cpu_data.x86 !=3D 0x10 ) return 0; =20 for ( i =3D 0; i < ARRAY_SIZE(final_levels); i++ ) - if ( uci->cpu_sig.rev =3D=3D final_levels[i] ) + if ( sig->rev =3D=3D final_levels[i] ) return 1; =20 return 0; @@ -456,13 +456,12 @@ static bool_t check_final_patch_levels(unsigned int c= pu) static int cpu_request_microcode(unsigned int cpu, const void *buf, size_t bufsize) { - struct microcode_amd *mc_amd, *mc_old; + struct microcode_amd *mc_amd; size_t offset =3D 0; - size_t last_offset, applied_offset =3D 0; - int error =3D 0, save_error =3D 1; - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); + int error =3D 0; unsigned int current_cpu_id; unsigned int equiv_cpu_id; + const struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); =20 /* We should bind the task to the CPU */ BUG_ON(cpu !=3D raw_smp_processor_id()); @@ -531,7 +530,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, { printk(KERN_ERR "microcode: CPU%d incorrect or corrupt contain= er file\n" "microcode: Failed to update patch level. " - "Current lvl:%#x\n", cpu, uci->cpu_sig.rev); + "Current lvl:%#x\n", cpu, sig->rev); break; } } @@ -543,15 +542,10 @@ static int cpu_request_microcode(unsigned int cpu, co= nst void *buf, goto out; } =20 - mc_old =3D uci->mc.mc_amd; - /* implicitely validates uci->mc.mc_valid */ - uci->mc.mc_amd =3D mc_amd; - /* * It's possible the data file has multiple matching ucode, * lets keep searching till the latest version */ - last_offset =3D offset; while ( (error =3D get_ucode_from_buffer_amd(mc_amd, buf, bufsize, &offset)) =3D=3D 0 ) { @@ -574,11 +568,8 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, error =3D apply_microcode(cpu); if ( error ) break; - applied_offset =3D last_offset; } =20 - last_offset =3D offset; - if ( offset >=3D bufsize ) break; =20 @@ -606,28 +597,9 @@ static int cpu_request_microcode(unsigned int cpu, con= st void *buf, *(const uint32_t *)(buf + offset) =3D=3D UCODE_MAGIC ) break; } - - /* On success keep the microcode patch for - * re-apply on resume. - */ - if ( applied_offset ) - { - save_error =3D get_ucode_from_buffer_amd( - mc_amd, buf, bufsize, &applied_offset); - - if ( save_error ) - error =3D save_error; - } - - if ( save_error ) - { - uci->mc.mc_amd =3D mc_old; - mc_old =3D mc_amd; - } - - xfree(mc_old->mpb); - xfree(mc_old->equiv_cpu_table); - xfree(mc_old); + xfree(mc_amd->mpb); + xfree(mc_amd->equiv_cpu_table); + xfree(mc_amd); =20 out: #if CONFIG_HVM diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 58eb186..fafaa79 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -141,10 +141,10 @@ static enum microcode_match_result microcode_update_m= atch( const struct extended_sigtable *ext_header; const struct extended_signature *ext_sig; unsigned int i; - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); - unsigned int sig =3D uci->cpu_sig.sig; - unsigned int pf =3D uci->cpu_sig.pf; - unsigned int rev =3D uci->cpu_sig.rev; + struct cpu_signature *cpu_sig =3D &per_cpu(cpu_sig, cpu); + unsigned int sig =3D cpu_sig->sig; + unsigned int pf =3D cpu_sig->pf; + unsigned int rev =3D cpu_sig->rev; unsigned long data_size =3D get_datasize(mc_header); const void *end =3D (const void *)mc_header + get_totalsize(mc_header); =20 @@ -291,7 +291,6 @@ static enum microcode_match_result compare_patch( */ static int get_matching_microcode(const void *mc, unsigned int cpu) { - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu); const struct microcode_header_intel *mc_header =3D mc; unsigned long total_size =3D get_totalsize(mc_header); void *new_mc =3D xmalloc_bytes(total_size); @@ -317,17 +316,8 @@ static int get_matching_microcode(const void *mc, unsi= gned int cpu) =20 pr_debug("microcode: CPU%d found a matching microcode update with" " version %#x (current=3D%#x)\n", - cpu, mc_header->rev, uci->cpu_sig.rev); - new_mc =3D xmalloc_bytes(total_size); - if ( new_mc =3D=3D NULL ) - { - printk(KERN_ERR "microcode: error! Can not allocate memory\n"); - return -ENOMEM; - } + cpu, mc_header->rev, per_cpu(cpu_sig, cpu).rev); =20 - memcpy(new_mc, mc, total_size); - xfree(uci->mc.mc_intel); - uci->mc.mc_intel =3D new_mc; return 1; } =20 @@ -337,7 +327,7 @@ static int apply_microcode(unsigned int cpu) uint64_t msr_content; unsigned int val[2]; unsigned int cpu_num =3D raw_smp_processor_id(); - struct ucode_cpu_info *uci =3D &per_cpu(ucode_cpu_info, cpu_num); + struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_intel *mc_intel; const struct microcode_patch *patch =3D microcode_get_cache(); =20 @@ -368,14 +358,14 @@ static int apply_microcode(unsigned int cpu) { printk(KERN_ERR "microcode: CPU%d update from revision " "%#x to %#x failed. Resulting revision is %#x.\n", cpu_num, - uci->cpu_sig.rev, mc_intel->hdr.rev, val[1]); + sig->rev, mc_intel->hdr.rev, val[1]); return -EIO; } printk(KERN_INFO "microcode: CPU%d updated from revision " "%#x to %#x, date =3D %04x-%02x-%02x \n", - cpu_num, uci->cpu_sig.rev, val[1], mc_intel->hdr.year, + cpu_num, sig->rev, val[1], mc_intel->hdr.year, mc_intel->hdr.month, mc_intel->hdr.day); - uci->cpu_sig.rev =3D val[1]; + sig->rev =3D val[1]; =20 return 0; } diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 468a847..4761be8 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -438,7 +438,7 @@ static bool __init check_smt_enabled(void) /* Calculate whether Retpoline is known-safe on this CPU. */ static bool __init retpoline_safe(uint64_t caps) { - unsigned int ucode_rev =3D this_cpu(ucode_cpu_info).cpu_sig.rev; + unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; =20 if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 3238743..5b8289f 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -10,7 +10,6 @@ enum microcode_match_result { }; =20 struct cpu_signature; -struct ucode_cpu_info; =20 struct microcode_patch { union { @@ -39,16 +38,7 @@ struct cpu_signature { unsigned int rev; }; =20 -struct ucode_cpu_info { - struct cpu_signature cpu_sig; - union { - struct microcode_intel *mc_intel; - struct microcode_amd *mc_amd; - void *mc_valid; - } mc; -}; - -DECLARE_PER_CPU(struct ucode_cpu_info, ucode_cpu_info); +DECLARE_PER_CPU(struct cpu_signature, cpu_sig); extern const struct microcode_ops *microcode_ops; =20 const struct microcode_patch *microcode_get_cache(void); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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18 Aug 2019 18:21:44 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:42 -0700 X-Inumbo-ID: b519343a-c21f-11e9-8be5-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683894" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:20 +0800 Message-Id: <1566177928-19114-8-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 07/15] microcode: remove pointless 'cpu' parameter X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some callbacks in microcode_ops or related functions take a cpu id parameter. But at current call sites, the cpu id parameter is always equal to current cpu id. Some of them even use an assertion to guarantee this. Remove this redundent 'cpu' parameter. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- Changes in v9: - use a convenience variable 'cpu' in collect_cpu_info() on AMD side - rebase and fix conflicts Changes in v8: - Use current_cpu_data in collect_cpu_info() - keep the cpu parameter of check_final_patch_levels() - use smp_processor_id() in get_matching_microcode() rather than define a local variable and label it "__maybe_unused" --- xen/arch/x86/acpi/power.c | 2 +- xen/arch/x86/microcode.c | 20 ++++++++------------ xen/arch/x86/microcode_amd.c | 30 +++++++++++------------------- xen/arch/x86/microcode_intel.c | 35 +++++++++++++---------------------- xen/arch/x86/smpboot.c | 2 +- xen/include/asm-x86/microcode.h | 7 +++---- xen/include/asm-x86/processor.h | 2 +- 7 files changed, 38 insertions(+), 60 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index aecc754..4f21903 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -253,7 +253,7 @@ static int enter_state(u32 state) =20 console_end_sync(); =20 - microcode_resume_cpu(0); + microcode_resume_cpu(); =20 if ( !recheck_cpu_features(0) ) panic("Missing previously available feature(s)\n"); diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 552e7fe..3b87c72 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -196,19 +196,19 @@ struct microcode_info { char buffer[1]; }; =20 -int microcode_resume_cpu(unsigned int cpu) +int microcode_resume_cpu(void) { int err; - struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); + struct cpu_signature *sig =3D &this_cpu(cpu_sig); =20 if ( !microcode_ops ) return 0; =20 spin_lock(µcode_mutex); =20 - err =3D microcode_ops->collect_cpu_info(cpu, sig); + err =3D microcode_ops->collect_cpu_info(sig); if ( likely(!err) ) - err =3D microcode_ops->apply_microcode(cpu); + err =3D microcode_ops->apply_microcode(); spin_unlock(µcode_mutex); =20 return err; @@ -258,9 +258,9 @@ static int microcode_update_cpu(const void *buf, size_t= size) =20 spin_lock(µcode_mutex); =20 - err =3D microcode_ops->collect_cpu_info(cpu, sig); + err =3D microcode_ops->collect_cpu_info(sig); if ( likely(!err) ) - err =3D microcode_ops->cpu_request_microcode(cpu, buf, size); + err =3D microcode_ops->cpu_request_microcode(buf, size); spin_unlock(µcode_mutex); =20 return err; @@ -349,8 +349,6 @@ __initcall(microcode_init); =20 int __init early_microcode_update_cpu(bool start_update) { - unsigned int cpu =3D smp_processor_id(); - struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); int rc =3D 0; void *data =3D NULL; size_t len; @@ -369,7 +367,7 @@ int __init early_microcode_update_cpu(bool start_update) data =3D bootstrap_map(&ucode_mod); } =20 - microcode_ops->collect_cpu_info(cpu, sig); + microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); =20 if ( data ) { @@ -387,8 +385,6 @@ int __init early_microcode_update_cpu(bool start_update) =20 int __init early_microcode_init(void) { - unsigned int cpu =3D smp_processor_id(); - struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); int rc; =20 rc =3D microcode_init_intel(); @@ -401,7 +397,7 @@ int __init early_microcode_init(void) =20 if ( microcode_ops ) { - microcode_ops->collect_cpu_info(cpu, sig); + microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); =20 if ( ucode_mod.mod_end || ucode_blob.size ) rc =3D early_microcode_update_cpu(true); diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 9e4ec73..dd3821c 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -78,8 +78,9 @@ struct mpbhdr { static DEFINE_SPINLOCK(microcode_update_lock); =20 /* See comment in start_update() for cases when this routine fails */ -static int collect_cpu_info(unsigned int cpu, struct cpu_signature *csig) +static int collect_cpu_info(struct cpu_signature *csig) { + unsigned int cpu =3D smp_processor_id(); struct cpuinfo_x86 *c =3D &cpu_data[cpu]; =20 memset(csig, 0, sizeof(*csig)); @@ -153,17 +154,15 @@ static bool_t find_equiv_cpu_id(const struct equiv_cp= u_entry *equiv_cpu_table, } =20 static enum microcode_match_result microcode_fits( - const struct microcode_amd *mc_amd, unsigned int cpu) + const struct microcode_amd *mc_amd) { + unsigned int cpu =3D smp_processor_id(); const struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_header_amd *mc_header =3D mc_amd->mpb; const struct equiv_cpu_entry *equiv_cpu_table =3D mc_amd->equiv_cpu_ta= ble; unsigned int current_cpu_id; unsigned int equiv_cpu_id; =20 - /* We should bind the task to the CPU */ - BUG_ON(cpu !=3D raw_smp_processor_id()); - current_cpu_id =3D cpuid_eax(0x00000001); =20 if ( !find_equiv_cpu_id(equiv_cpu_table, current_cpu_id, &equiv_cpu_id= ) ) @@ -192,9 +191,7 @@ static enum microcode_match_result microcode_fits( =20 static bool match_cpu(const struct microcode_patch *patch) { - if ( !patch ) - return false; - return microcode_fits(patch->mc_amd, smp_processor_id()) =3D=3D NEW_UC= ODE; + return patch && (microcode_fits(patch->mc_amd) =3D=3D NEW_UCODE); } =20 static struct microcode_patch *alloc_microcode_patch( @@ -251,18 +248,16 @@ static enum microcode_match_result compare_patch( return MIS_UCODE; } =20 -static int apply_microcode(unsigned int cpu) +static int apply_microcode(void) { unsigned long flags; uint32_t rev; int hw_err; + unsigned int cpu =3D smp_processor_id(); struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_header_amd *hdr; const struct microcode_patch *patch =3D microcode_get_cache(); =20 - /* We should bind the task to the CPU */ - BUG_ON(raw_smp_processor_id() !=3D cpu); - if ( !match_cpu(patch) ) return -EINVAL; =20 @@ -453,19 +448,16 @@ static bool_t check_final_patch_levels(unsigned int c= pu) return 0; } =20 -static int cpu_request_microcode(unsigned int cpu, const void *buf, - size_t bufsize) +static int cpu_request_microcode(const void *buf, size_t bufsize) { struct microcode_amd *mc_amd; size_t offset =3D 0; int error =3D 0; unsigned int current_cpu_id; unsigned int equiv_cpu_id; + unsigned int cpu =3D smp_processor_id(); const struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); =20 - /* We should bind the task to the CPU */ - BUG_ON(cpu !=3D raw_smp_processor_id()); - current_cpu_id =3D cpuid_eax(0x00000001); =20 if ( *(const uint32_t *)buf !=3D UCODE_MAGIC ) @@ -558,14 +550,14 @@ static int cpu_request_microcode(unsigned int cpu, co= nst void *buf, } =20 /* Update cache if this patch covers current CPU */ - if ( microcode_fits(new_patch->mc_amd, cpu) !=3D MIS_UCODE ) + if ( microcode_fits(new_patch->mc_amd) !=3D MIS_UCODE ) microcode_update_cache(new_patch); else microcode_free_patch(new_patch); =20 if ( match_cpu(microcode_get_cache()) ) { - error =3D apply_microcode(cpu); + error =3D apply_microcode(); if ( error ) break; } diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index fafaa79..a5452d4 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -96,13 +96,12 @@ struct extended_sigtable { /* serialize access to the physical write to MSR 0x79 */ static DEFINE_SPINLOCK(microcode_update_lock); =20 -static int collect_cpu_info(unsigned int cpu_num, struct cpu_signature *cs= ig) +static int collect_cpu_info(struct cpu_signature *csig) { + unsigned int cpu_num =3D smp_processor_id(); struct cpuinfo_x86 *c =3D &cpu_data[cpu_num]; uint64_t msr_content; =20 - BUG_ON(cpu_num !=3D smp_processor_id()); - memset(csig, 0, sizeof(*csig)); =20 if ( (c->x86_vendor !=3D X86_VENDOR_INTEL) || (c->x86 < 6) ) @@ -136,12 +135,12 @@ static int collect_cpu_info(unsigned int cpu_num, str= uct cpu_signature *csig) =20 /* Check an update against the CPU signature and current update revision */ static enum microcode_match_result microcode_update_match( - const struct microcode_header_intel *mc_header, unsigned int cpu) + const struct microcode_header_intel *mc_header) { const struct extended_sigtable *ext_header; const struct extended_signature *ext_sig; unsigned int i; - struct cpu_signature *cpu_sig =3D &per_cpu(cpu_sig, cpu); + struct cpu_signature *cpu_sig =3D &this_cpu(cpu_sig); unsigned int sig =3D cpu_sig->sig; unsigned int pf =3D cpu_sig->pf; unsigned int rev =3D cpu_sig->rev; @@ -264,8 +263,7 @@ static bool match_cpu(const struct microcode_patch *pat= ch) if ( !patch ) return false; =20 - return microcode_update_match(&patch->mc_intel->hdr, - smp_processor_id()) =3D=3D NEW_UCODE; + return microcode_update_match(&patch->mc_intel->hdr) =3D=3D NEW_UCODE; } =20 static void free_patch(void *mc) @@ -289,7 +287,7 @@ static enum microcode_match_result compare_patch( * return 1 - found update * return < 0 - error */ -static int get_matching_microcode(const void *mc, unsigned int cpu) +static int get_matching_microcode(const void *mc) { const struct microcode_header_intel *mc_header =3D mc; unsigned long total_size =3D get_totalsize(mc_header); @@ -306,7 +304,7 @@ static int get_matching_microcode(const void *mc, unsig= ned int cpu) new_patch->mc_intel =3D new_mc; =20 /* Make sure that this patch covers current CPU */ - if ( microcode_update_match(mc, cpu) =3D=3D MIS_UCODE ) + if ( microcode_update_match(mc) =3D=3D MIS_UCODE ) { microcode_free_patch(new_patch); return 0; @@ -316,24 +314,21 @@ static int get_matching_microcode(const void *mc, uns= igned int cpu) =20 pr_debug("microcode: CPU%d found a matching microcode update with" " version %#x (current=3D%#x)\n", - cpu, mc_header->rev, per_cpu(cpu_sig, cpu).rev); + smp_processor_id(), mc_header->rev, this_cpu(cpu_sig).rev); =20 return 1; } =20 -static int apply_microcode(unsigned int cpu) +static int apply_microcode(void) { unsigned long flags; uint64_t msr_content; unsigned int val[2]; unsigned int cpu_num =3D raw_smp_processor_id(); - struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); + struct cpu_signature *sig =3D &this_cpu(cpu_sig); const struct microcode_intel *mc_intel; const struct microcode_patch *patch =3D microcode_get_cache(); =20 - /* We should bind the task to the CPU */ - BUG_ON(cpu_num !=3D cpu); - if ( !match_cpu(patch) ) return -EINVAL; =20 @@ -398,22 +393,18 @@ static long get_next_ucode_from_buffer(void **mc, con= st u8 *buf, return offset + total_size; } =20 -static int cpu_request_microcode(unsigned int cpu, const void *buf, - size_t size) +static int cpu_request_microcode(const void *buf, size_t size) { long offset =3D 0; int error =3D 0; void *mc; =20 - /* We should bind the task to the CPU */ - BUG_ON(cpu !=3D raw_smp_processor_id()); - while ( (offset =3D get_next_ucode_from_buffer(&mc, buf, size, offset)= ) > 0 ) { error =3D microcode_sanity_check(mc); if ( error ) break; - error =3D get_matching_microcode(mc, cpu); + error =3D get_matching_microcode(mc); if ( error < 0 ) break; /* @@ -431,7 +422,7 @@ static int cpu_request_microcode(unsigned int cpu, cons= t void *buf, error =3D offset; =20 if ( !error && match_cpu(microcode_get_cache()) ) - error =3D apply_microcode(cpu); + error =3D apply_microcode(); =20 return error; } diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 65e9cee..c818cfc 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -364,7 +364,7 @@ void start_secondary(void *unused) if ( system_state <=3D SYS_STATE_smp_boot ) early_microcode_update_cpu(false); else - microcode_resume_cpu(cpu); + microcode_resume_cpu(); =20 /* * If MSR_SPEC_CTRL is available, apply Xen's default setting and disc= ard diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 5b8289f..35223eb 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -20,10 +20,9 @@ struct microcode_patch { }; =20 struct microcode_ops { - int (*cpu_request_microcode)(unsigned int cpu, const void *buf, - size_t size); - int (*collect_cpu_info)(unsigned int cpu, struct cpu_signature *csig); - int (*apply_microcode)(unsigned int cpu); + int (*cpu_request_microcode)(const void *buf, size_t size); + int (*collect_cpu_info)(struct cpu_signature *csig); + int (*apply_microcode)(void); int (*start_update)(void); void (*free_patch)(void *mc); bool (*match_cpu)(const struct microcode_patch *patch); diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 2862321..104faa9 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -568,7 +568,7 @@ int guest_wrmsr_xen(struct vcpu *v, uint32_t idx, uint6= 4_t val); =20 void microcode_set_module(unsigned int); int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void), unsigned long len= ); -int microcode_resume_cpu(unsigned int cpu); +int microcode_resume_cpu(void); int early_microcode_update_cpu(bool start_update); int early_microcode_init(void); int microcode_init_intel(void); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="261683905" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:21 +0800 Message-Id: <1566177928-19114-9-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 08/15] microcode/amd: call svm_host_osvw_init() in common code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Introduce a vendor hook, .end_update, for svm_host_osvw_init(). The hook function is called on each cpu after loading an update. It is a preparation for spliting out apply_microcode() from cpu_request_microcode(). Note that svm_host_osvm_init() should be called regardless of the result of loading an update. Signed-off-by: Chao Gao Reviewed-by: Roger Pau Monn=C3=A9 --- Changes in v9: - call .end_update in early loading path - on AMD side, initialize .{start,end}_update only if "CONFIG_HVM" is true. --- xen/arch/x86/microcode.c | 10 +++++++++- xen/arch/x86/microcode_amd.c | 23 ++++++++++------------- xen/include/asm-x86/microcode.h | 1 + 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 3b87c72..c9401a7 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -277,6 +277,9 @@ static long do_microcode_update(void *_info) if ( error ) info->error =3D error; =20 + if ( microcode_ops->end_update ) + microcode_ops->end_update(); + info->cpu =3D cpumask_next(info->cpu, &cpu_online_map); if ( info->cpu < nr_cpu_ids ) return continue_hypercall_on_cpu(info->cpu, do_microcode_update, i= nfo); @@ -377,7 +380,12 @@ int __init early_microcode_update_cpu(bool start_updat= e) if ( rc ) return rc; =20 - return microcode_update_cpu(data, len); + rc =3D microcode_update_cpu(data, len); + + if ( microcode_ops->end_update ) + microcode_ops->end_update(); + + return rc; } else return -ENOMEM; diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index dd3821c..b85fb04 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -594,10 +594,6 @@ static int cpu_request_microcode(const void *buf, size= _t bufsize) xfree(mc_amd); =20 out: -#if CONFIG_HVM - svm_host_osvw_init(); -#endif - /* * In some cases we may return an error even if processor's microcode = has * been updated. For example, the first patch in a container file is l= oaded @@ -609,27 +605,28 @@ static int cpu_request_microcode(const void *buf, siz= e_t bufsize) =20 static int start_update(void) { -#if CONFIG_HVM /* - * We assume here that svm_host_osvw_init() will be called on each cpu= (from - * cpu_request_microcode()). - * - * Note that if collect_cpu_info() returns an error then - * cpu_request_microcode() will not invoked thus leaving OSVW bits not - * updated. Currently though collect_cpu_info() will not fail on proce= ssors - * supporting OSVW so we will not deal with this possibility. + * svm_host_osvw_init() will be called on each cpu by calling '.end_up= date' + * in common code. */ svm_host_osvw_reset(); -#endif =20 return 0; } =20 +static void end_update(void) +{ + svm_host_osvw_init(); +} + static const struct microcode_ops microcode_amd_ops =3D { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, +#if CONFIG_HVM .start_update =3D start_update, + .end_update =3D end_update, +#endif .free_patch =3D free_patch, .compare_patch =3D compare_patch, .match_cpu =3D match_cpu, diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 35223eb..c8d2c4f 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -24,6 +24,7 @@ struct microcode_ops { int (*collect_cpu_info)(struct cpu_signature *csig); int (*apply_microcode)(void); int (*start_update)(void); + void (*end_update)(void); void (*free_patch)(void *mc); bool (*match_cpu)(const struct microcode_patch *patch); enum microcode_match_result (*compare_patch)( --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177772; cv=none; d=zoho.com; s=zohoarc; b=ZWHGAsK3fUJOQgIGNBnBqsVm8tbUB6ex7FaRpM59i92EnKeRphRZQKpmYjCcGXkGONHLps9vwwKtaGsEGgSCUzkPi8FeZ+nZNEm5lJxgpC90PJHmFoiqge66TV1zz90AhfBVCLPtoONG6xJ6TQdKRe10K1vDKaS/QXpPHtyMHkc= ARC-Message-Signature: i=1; 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Mon, 19 Aug 2019 01:21:52 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMp-0001F2-6a for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:21:51 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id b7af3619-c21f-11e9-8be6-12813bfff9fa; Mon, 19 Aug 2019 01:21:50 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:21:50 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:48 -0700 X-Inumbo-ID: b7af3619-c21f-11e9-8be6-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683912" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:22 +0800 Message-Id: <1566177928-19114-10-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 09/15] microcode: pass a patch pointer to apply_microcode() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" apply_microcode()'s always loading the cached ucode patch forces a patch to be stored before being loading. Make apply_microcode() accept a patch pointer to remove the limitation so that a patch can be stored after a successful loading. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- xen/arch/x86/microcode.c | 2 +- xen/arch/x86/microcode_amd.c | 5 ++--- xen/arch/x86/microcode_intel.c | 5 ++--- xen/include/asm-x86/microcode.h | 2 +- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index c9401a7..0e9322a 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -208,7 +208,7 @@ int microcode_resume_cpu(void) =20 err =3D microcode_ops->collect_cpu_info(sig); if ( likely(!err) ) - err =3D microcode_ops->apply_microcode(); + err =3D microcode_ops->apply_microcode(microcode_cache); spin_unlock(µcode_mutex); =20 return err; diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index b85fb04..21cdfe0 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -248,7 +248,7 @@ static enum microcode_match_result compare_patch( return MIS_UCODE; } =20 -static int apply_microcode(void) +static int apply_microcode(const struct microcode_patch *patch) { unsigned long flags; uint32_t rev; @@ -256,7 +256,6 @@ static int apply_microcode(void) unsigned int cpu =3D smp_processor_id(); struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); const struct microcode_header_amd *hdr; - const struct microcode_patch *patch =3D microcode_get_cache(); =20 if ( !match_cpu(patch) ) return -EINVAL; @@ -557,7 +556,7 @@ static int cpu_request_microcode(const void *buf, size_= t bufsize) =20 if ( match_cpu(microcode_get_cache()) ) { - error =3D apply_microcode(); + error =3D apply_microcode(microcode_get_cache()); if ( error ) break; } diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index a5452d4..8c0008c 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -319,7 +319,7 @@ static int get_matching_microcode(const void *mc) return 1; } =20 -static int apply_microcode(void) +static int apply_microcode(const struct microcode_patch *patch) { unsigned long flags; uint64_t msr_content; @@ -327,7 +327,6 @@ static int apply_microcode(void) unsigned int cpu_num =3D raw_smp_processor_id(); struct cpu_signature *sig =3D &this_cpu(cpu_sig); const struct microcode_intel *mc_intel; - const struct microcode_patch *patch =3D microcode_get_cache(); =20 if ( !match_cpu(patch) ) return -EINVAL; @@ -422,7 +421,7 @@ static int cpu_request_microcode(const void *buf, size_= t size) error =3D offset; =20 if ( !error && match_cpu(microcode_get_cache()) ) - error =3D apply_microcode(); + error =3D apply_microcode(microcode_get_cache()); =20 return error; } diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index c8d2c4f..8c7de9d 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -22,7 +22,7 @@ struct microcode_patch { struct microcode_ops { int (*cpu_request_microcode)(const void *buf, size_t size); int (*collect_cpu_info)(struct cpu_signature *csig); - int (*apply_microcode)(void); + int (*apply_microcode)(const struct microcode_patch *patch); int (*start_update)(void); void (*end_update)(void); void (*free_patch)(void *mc); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177780; cv=none; d=zoho.com; s=zohoarc; b=Q/rQ4ebev7HsvHbX759S7MAe0nBkGBu+UWysYTKs9LPg9o8YfhCo6hDtRBz4C25H8PmbeaFe7eYaT3IMe51vQb54z89B5AXST3Nn5muXoRKK+ZZJrNG1rEmKba0+ZRnG9+9nli8Eop6Ksvqdv6ekhccrGDSuOY0sBa+3RauYJfk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Mon, 19 Aug 2019 01:21:56 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMs-0001Ik-Qp for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:21:54 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id ba902162-c21f-11e9-8be6-12813bfff9fa; Mon, 19 Aug 2019 01:21:54 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:21:54 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:52 -0700 X-Inumbo-ID: ba902162-c21f-11e9-8be6-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683929" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:23 +0800 Message-Id: <1566177928-19114-11-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 10/15] microcode: split out apply_microcode() from cpu_request_microcode() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" During late microcode loading, apply_microcode() is invoked in cpu_request_microcode(). To make late microcode update more reliable, we want to put the apply_microcode() into stop_machine context. So we split out it from cpu_request_microcode(). In general, for both early loading on BSP and late loading, cpu_request_microcode() is called first to get the matching microcode update contained by the blob and then apply_microcode() is invoked explicitly on each cpu in common code. Given that all CPUs are supposed to have the same signature, parsing microcode only needs to be done once. So cpu_request_microcode() is also moved out of microcode_update_cpu(). In some cases (e.g. a broken bios), the system may have multiple revisions of microcode update. So we would try to load a microcode update as long as it covers current cpu. And if a cpu loads this patch successfully, the patch would be stored into the patch cache. Signed-off-by: Chao Gao Reviewed-by: Roger Pau Monn=C3=A9 --- Changes in v9: - remove the calling of ->compare_patch in microcode_update_cpu(). - drop "microcode_" prefix for static function - microcode_parse_blob(). - rebase and fix conflict Changes in v8: - divide the original patch into three patches to improve readability - load an update on each cpu as long as the update covers current cpu - store an update after the first successful loading on a CPU - Make sure the current CPU (especially pf value) is covered by updates. changes in v7: - to handle load failure, unvalidated patches won't be cached. They are passed as function arguments. So if update failed, we needn't any cleanup to microcode cache. --- xen/arch/x86/microcode.c | 177 ++++++++++++++++++++++++++----------= ---- xen/arch/x86/microcode_amd.c | 38 +++++---- xen/arch/x86/microcode_intel.c | 66 +++++++-------- xen/include/asm-x86/microcode.h | 5 +- 4 files changed, 172 insertions(+), 114 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 0e9322a..a2febc7 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -189,12 +189,19 @@ static DEFINE_SPINLOCK(microcode_mutex); =20 DEFINE_PER_CPU(struct cpu_signature, cpu_sig); =20 -struct microcode_info { - unsigned int cpu; - uint32_t buffer_size; - int error; - char buffer[1]; -}; +/* + * Return a patch that covers current CPU. If there are multiple patches, + * return the one with the highest revision number. Return error If no + * patch is found and an error occurs during the parsing process. Otherwise + * return NULL. + */ +static struct microcode_patch *parse_blob(const char *buf, uint32_t len) +{ + if ( likely(!microcode_ops->collect_cpu_info(&this_cpu(cpu_sig))) ) + return microcode_ops->cpu_request_microcode(buf, len); + + return NULL; +} =20 int microcode_resume_cpu(void) { @@ -220,13 +227,6 @@ void microcode_free_patch(struct microcode_patch *micr= ocode_patch) xfree(microcode_patch); } =20 -const struct microcode_patch *microcode_get_cache(void) -{ - ASSERT(spin_is_locked(µcode_mutex)); - - return microcode_cache; -} - /* Return true if cache gets updated. Otherwise, return false */ bool microcode_update_cache(struct microcode_patch *patch) { @@ -250,49 +250,71 @@ bool microcode_update_cache(struct microcode_patch *p= atch) return true; } =20 -static int microcode_update_cpu(const void *buf, size_t size) +/* + * Load a microcode update to current CPU. + * + * If no patch is provided, the cached patch will be loaded. Microcode upd= ate + * during APs bringup and CPU resuming falls into this case. + */ +static int microcode_update_cpu(const struct microcode_patch *patch) { - int err; - unsigned int cpu =3D smp_processor_id(); - struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); + int err =3D microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); =20 - spin_lock(µcode_mutex); + if ( unlikely(err) ) + return err; =20 - err =3D microcode_ops->collect_cpu_info(sig); - if ( likely(!err) ) - err =3D microcode_ops->cpu_request_microcode(buf, size); - spin_unlock(µcode_mutex); + if ( patch ) + err =3D microcode_ops->apply_microcode(patch); + else if ( microcode_cache ) + { + spin_lock(µcode_mutex); + err =3D microcode_ops->apply_microcode(microcode_cache); + if ( err =3D=3D -EIO ) + { + microcode_free_patch(microcode_cache); + microcode_cache =3D NULL; + } + spin_unlock(µcode_mutex); + } + else + /* No patch to update */ + err =3D -ENOENT; =20 return err; } =20 -static long do_microcode_update(void *_info) +static long do_microcode_update(void *patch) { - struct microcode_info *info =3D _info; - int error; - - BUG_ON(info->cpu !=3D smp_processor_id()); + unsigned int cpu; =20 - error =3D microcode_update_cpu(info->buffer, info->buffer_size); - if ( error ) - info->error =3D error; + /* Store the patch after a successful loading */ + if ( !microcode_update_cpu(patch) && patch ) + { + spin_lock(µcode_mutex); + microcode_update_cache(patch); + spin_unlock(µcode_mutex); + patch =3D NULL; + } =20 if ( microcode_ops->end_update ) microcode_ops->end_update(); =20 - info->cpu =3D cpumask_next(info->cpu, &cpu_online_map); - if ( info->cpu < nr_cpu_ids ) - return continue_hypercall_on_cpu(info->cpu, do_microcode_update, i= nfo); + cpu =3D cpumask_next(smp_processor_id(), &cpu_online_map); + if ( cpu < nr_cpu_ids ) + return continue_hypercall_on_cpu(cpu, do_microcode_update, patch); =20 - error =3D info->error; - xfree(info); - return error; + /* Free the patch if no CPU has loaded it successfully. */ + if ( patch ) + microcode_free_patch(patch); + + return 0; } =20 int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void) buf, unsigned long= len) { int ret; - struct microcode_info *info; + void *buffer; + struct microcode_patch *patch; =20 if ( len !=3D (uint32_t)len ) return -E2BIG; @@ -300,32 +322,44 @@ int microcode_update(XEN_GUEST_HANDLE_PARAM(const_voi= d) buf, unsigned long len) if ( microcode_ops =3D=3D NULL ) return -EINVAL; =20 - info =3D xmalloc_bytes(sizeof(*info) + len); - if ( info =3D=3D NULL ) + buffer =3D xmalloc_bytes(len); + if ( !buffer ) return -ENOMEM; =20 - ret =3D copy_from_guest(info->buffer, buf, len); - if ( ret !=3D 0 ) + if ( copy_from_guest(buffer, buf, len) ) { - xfree(info); - return ret; + ret =3D -EFAULT; + goto free; } =20 - info->buffer_size =3D len; - info->error =3D 0; - info->cpu =3D cpumask_first(&cpu_online_map); - if ( microcode_ops->start_update ) { ret =3D microcode_ops->start_update(); if ( ret !=3D 0 ) - { - xfree(info); - return ret; - } + goto free; } =20 - return continue_hypercall_on_cpu(info->cpu, do_microcode_update, info); + patch =3D parse_blob(buffer, len); + if ( IS_ERR(patch) ) + { + ret =3D PTR_ERR(patch); + printk(XENLOG_INFO "Parsing microcode blob error %d\n", ret); + goto free; + } + + if ( !patch ) + { + printk(XENLOG_INFO "No ucode found. Update aborted!\n"); + ret =3D -EINVAL; + goto free; + } + + ret =3D continue_hypercall_on_cpu(cpumask_first(&cpu_online_map), + do_microcode_update, patch); + + free: + xfree(buffer); + return ret; } =20 static int __init microcode_init(void) @@ -372,23 +406,46 @@ int __init early_microcode_update_cpu(bool start_upda= te) =20 microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); =20 - if ( data ) + if ( !data ) + return -ENOMEM; + + if ( start_update ) { - if ( start_update && microcode_ops->start_update ) + struct microcode_patch *patch; + + if ( microcode_ops->start_update ) rc =3D microcode_ops->start_update(); =20 if ( rc ) return rc; =20 - rc =3D microcode_update_cpu(data, len); + patch =3D parse_blob(data, len); + if ( IS_ERR(patch) ) + { + printk(XENLOG_INFO "Parsing microcode blob error %ld\n", + PTR_ERR(patch)); + return PTR_ERR(patch); + } + + if ( !patch ) + { + printk(XENLOG_INFO "No ucode found. Update aborted!\n"); + return -EINVAL; + } =20 - if ( microcode_ops->end_update ) - microcode_ops->end_update(); + spin_lock(µcode_mutex); + rc =3D microcode_update_cache(patch); + spin_unlock(µcode_mutex); =20 - return rc; + ASSERT(rc); } - else - return -ENOMEM; + + rc =3D microcode_update_cpu(NULL); + + if ( microcode_ops->end_update ) + microcode_ops->end_update(); + + return rc; } =20 int __init early_microcode_init(void) diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 21cdfe0..6353323 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -447,9 +447,11 @@ static bool_t check_final_patch_levels(unsigned int cp= u) return 0; } =20 -static int cpu_request_microcode(const void *buf, size_t bufsize) +static struct microcode_patch *cpu_request_microcode(const void *buf, + size_t bufsize) { struct microcode_amd *mc_amd; + struct microcode_patch *patch =3D NULL; size_t offset =3D 0; int error =3D 0; unsigned int current_cpu_id; @@ -548,19 +550,22 @@ static int cpu_request_microcode(const void *buf, siz= e_t bufsize) break; } =20 - /* Update cache if this patch covers current CPU */ - if ( microcode_fits(new_patch->mc_amd) !=3D MIS_UCODE ) - microcode_update_cache(new_patch); - else - microcode_free_patch(new_patch); - - if ( match_cpu(microcode_get_cache()) ) + /* + * If the new patch covers current CPU, compare patches and store = the + * one with higher revision. + */ + if ( (microcode_fits(new_patch->mc_amd) !=3D MIS_UCODE) && + (!patch || (compare_patch(new_patch, patch) =3D=3D NEW_UCODE)= ) ) { - error =3D apply_microcode(microcode_get_cache()); - if ( error ) - break; + struct microcode_patch *tmp =3D patch; + + patch =3D new_patch; + new_patch =3D tmp; } =20 + if ( new_patch ) + microcode_free_patch(new_patch); + if ( offset >=3D bufsize ) break; =20 @@ -593,13 +598,10 @@ static int cpu_request_microcode(const void *buf, siz= e_t bufsize) xfree(mc_amd); =20 out: - /* - * In some cases we may return an error even if processor's microcode = has - * been updated. For example, the first patch in a container file is l= oaded - * successfully but subsequent container file processing encounters a - * failure. - */ - return error; + if ( error && !patch ) + patch =3D ERR_PTR(error); + + return patch; } =20 static int start_update(void) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 8c0008c..96b38f8 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -282,14 +282,9 @@ static enum microcode_match_result compare_patch( OLD_UCODE; } =20 -/* - * return 0 - no update found - * return 1 - found update - * return < 0 - error - */ -static int get_matching_microcode(const void *mc) +static struct microcode_patch *alloc_microcode_patch( + const struct microcode_header_intel *mc_header) { - const struct microcode_header_intel *mc_header =3D mc; unsigned long total_size =3D get_totalsize(mc_header); void *new_mc =3D xmalloc_bytes(total_size); struct microcode_patch *new_patch =3D xmalloc(struct microcode_patch); @@ -298,25 +293,12 @@ static int get_matching_microcode(const void *mc) { xfree(new_patch); xfree(new_mc); - return -ENOMEM; + return ERR_PTR(-ENOMEM); } - memcpy(new_mc, mc, total_size); + memcpy(new_mc, mc_header, total_size); new_patch->mc_intel =3D new_mc; =20 - /* Make sure that this patch covers current CPU */ - if ( microcode_update_match(mc) =3D=3D MIS_UCODE ) - { - microcode_free_patch(new_patch); - return 0; - } - - microcode_update_cache(new_patch); - - pr_debug("microcode: CPU%d found a matching microcode update with" - " version %#x (current=3D%#x)\n", - smp_processor_id(), mc_header->rev, this_cpu(cpu_sig).rev); - - return 1; + return new_patch; } =20 static int apply_microcode(const struct microcode_patch *patch) @@ -392,26 +374,44 @@ static long get_next_ucode_from_buffer(void **mc, con= st u8 *buf, return offset + total_size; } =20 -static int cpu_request_microcode(const void *buf, size_t size) +static struct microcode_patch *cpu_request_microcode(const void *buf, + size_t size) { long offset =3D 0; int error =3D 0; void *mc; + struct microcode_patch *patch =3D NULL; =20 while ( (offset =3D get_next_ucode_from_buffer(&mc, buf, size, offset)= ) > 0 ) { + struct microcode_patch *new_patch; + error =3D microcode_sanity_check(mc); if ( error ) break; - error =3D get_matching_microcode(mc); - if ( error < 0 ) + + new_patch =3D alloc_microcode_patch(mc); + if ( IS_ERR(new_patch) ) + { + error =3D PTR_ERR(new_patch); break; + } + /* - * It's possible the data file has multiple matching ucode, - * lets keep searching till the latest version + * If the new patch covers current CPU, compare patches and store = the + * one with higher revision. */ - if ( error =3D=3D 1 ) - error =3D 0; + if ( (microcode_update_match(&new_patch->mc_intel->hdr) !=3D MIS_U= CODE) && + (!patch || (compare_patch(new_patch, patch) =3D=3D NEW_UCODE)= ) ) + { + struct microcode_patch *tmp =3D patch; + + patch =3D new_patch; + new_patch =3D tmp; + } + + if ( new_patch ) + microcode_free_patch(new_patch); =20 xfree(mc); } @@ -420,10 +420,10 @@ static int cpu_request_microcode(const void *buf, siz= e_t size) if ( offset < 0 ) error =3D offset; =20 - if ( !error && match_cpu(microcode_get_cache()) ) - error =3D apply_microcode(microcode_get_cache()); + if ( error && !patch ) + patch =3D ERR_PTR(error); =20 - return error; + return patch; } =20 static const struct microcode_ops microcode_intel_ops =3D { diff --git a/xen/include/asm-x86/microcode.h b/xen/include/asm-x86/microcod= e.h index 8c7de9d..8e71615 100644 --- a/xen/include/asm-x86/microcode.h +++ b/xen/include/asm-x86/microcode.h @@ -20,7 +20,8 @@ struct microcode_patch { }; =20 struct microcode_ops { - int (*cpu_request_microcode)(const void *buf, size_t size); + struct microcode_patch *(*cpu_request_microcode)(const void *buf, + size_t size); int (*collect_cpu_info)(struct cpu_signature *csig); int (*apply_microcode)(const struct microcode_patch *patch); int (*start_update)(void); @@ -41,8 +42,6 @@ struct cpu_signature { DECLARE_PER_CPU(struct cpu_signature, cpu_sig); extern const struct microcode_ops *microcode_ops; =20 -const struct microcode_patch *microcode_get_cache(void); -bool microcode_update_cache(struct microcode_patch *patch); void microcode_free_patch(struct microcode_patch *patch); =20 #endif /* ASM_X86__MICROCODE_H */ --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; 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d="scan'208";a="261683934" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:24 +0800 Message-Id: <1566177928-19114-12-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 11/15] microcode: unify loading update during CPU resuming and AP wakeup X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Both are loading the cached patch. Since APs call the unified function, microcode_update_one(), during wakeup, the 'start_update' parameter which originally used to distinguish BSP and APs is redundant. So remove this parameter. Signed-off-by: Chao Gao --- Note that here is a functional change: resuming a CPU would call ->end_update() now while previously it wasn't. Not quite sure whether it is correct. Changes in v9: - return -EOPNOTSUPP rather than 0 if microcode_ops is NULL in microcode_update_one() - rebase and fix conflicts. Changes in v8: - split out from the previous patch --- xen/arch/x86/acpi/power.c | 2 +- xen/arch/x86/microcode.c | 90 ++++++++++++++++++-------------------= ---- xen/arch/x86/smpboot.c | 5 +-- xen/include/asm-x86/processor.h | 4 +- 4 files changed, 44 insertions(+), 57 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 4f21903..24798d5 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -253,7 +253,7 @@ static int enter_state(u32 state) =20 console_end_sync(); =20 - microcode_resume_cpu(); + microcode_update_one(); =20 if ( !recheck_cpu_features(0) ) panic("Missing previously available feature(s)\n"); diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index a2febc7..bdd9c9f 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -203,24 +203,6 @@ static struct microcode_patch *parse_blob(const char *= buf, uint32_t len) return NULL; } =20 -int microcode_resume_cpu(void) -{ - int err; - struct cpu_signature *sig =3D &this_cpu(cpu_sig); - - if ( !microcode_ops ) - return 0; - - spin_lock(µcode_mutex); - - err =3D microcode_ops->collect_cpu_info(sig); - if ( likely(!err) ) - err =3D microcode_ops->apply_microcode(microcode_cache); - spin_unlock(µcode_mutex); - - return err; -} - void microcode_free_patch(struct microcode_patch *microcode_patch) { microcode_ops->free_patch(microcode_patch->mc); @@ -384,11 +366,29 @@ static int __init microcode_init(void) } __initcall(microcode_init); =20 -int __init early_microcode_update_cpu(bool start_update) +/* Load a cached update to current cpu */ +int microcode_update_one(void) +{ + int rc; + + if ( !microcode_ops ) + return -EOPNOTSUPP; + + rc =3D microcode_update_cpu(NULL); + + if ( microcode_ops->end_update ) + microcode_ops->end_update(); + + return rc; +} + +/* BSP calls this function to parse ucode blob and then apply an update. */ +int __init early_microcode_update_cpu(void) { int rc =3D 0; void *data =3D NULL; size_t len; + struct microcode_patch *patch; =20 if ( !microcode_ops ) return -ENOSYS; @@ -409,43 +409,33 @@ int __init early_microcode_update_cpu(bool start_upda= te) if ( !data ) return -ENOMEM; =20 - if ( start_update ) - { - struct microcode_patch *patch; - - if ( microcode_ops->start_update ) - rc =3D microcode_ops->start_update(); - - if ( rc ) - return rc; - - patch =3D parse_blob(data, len); - if ( IS_ERR(patch) ) - { - printk(XENLOG_INFO "Parsing microcode blob error %ld\n", - PTR_ERR(patch)); - return PTR_ERR(patch); - } + if ( microcode_ops->start_update ) + rc =3D microcode_ops->start_update(); =20 - if ( !patch ) - { - printk(XENLOG_INFO "No ucode found. Update aborted!\n"); - return -EINVAL; - } + if ( rc ) + return rc; =20 - spin_lock(µcode_mutex); - rc =3D microcode_update_cache(patch); - spin_unlock(µcode_mutex); + patch =3D parse_blob(data, len); + if ( IS_ERR(patch) ) + { + printk(XENLOG_INFO "Parsing microcode blob error %ld\n", + PTR_ERR(patch)); + return PTR_ERR(patch); + } =20 - ASSERT(rc); + if ( !patch ) + { + printk(XENLOG_INFO "No ucode found. Update aborted!\n"); + return -EINVAL; } =20 - rc =3D microcode_update_cpu(NULL); + spin_lock(µcode_mutex); + rc =3D microcode_update_cache(patch); + spin_unlock(µcode_mutex); =20 - if ( microcode_ops->end_update ) - microcode_ops->end_update(); + ASSERT(rc); =20 - return rc; + return microcode_update_one(); } =20 int __init early_microcode_init(void) @@ -465,7 +455,7 @@ int __init early_microcode_init(void) microcode_ops->collect_cpu_info(&this_cpu(cpu_sig)); =20 if ( ucode_mod.mod_end || ucode_blob.size ) - rc =3D early_microcode_update_cpu(true); + rc =3D early_microcode_update_cpu(); } =20 return rc; diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index c818cfc..e62a1ca 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -361,10 +361,7 @@ void start_secondary(void *unused) =20 initialize_cpu_data(cpu); =20 - if ( system_state <=3D SYS_STATE_smp_boot ) - early_microcode_update_cpu(false); - else - microcode_resume_cpu(); + microcode_update_one(); =20 /* * If MSR_SPEC_CTRL is available, apply Xen's default setting and disc= ard diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 104faa9..2a76d90 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -568,9 +568,9 @@ int guest_wrmsr_xen(struct vcpu *v, uint32_t idx, uint6= 4_t val); =20 void microcode_set_module(unsigned int); int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void), unsigned long len= ); -int microcode_resume_cpu(void); -int early_microcode_update_cpu(bool start_update); +int early_microcode_update_cpu(void); int early_microcode_init(void); +int microcode_update_one(void); int microcode_init_intel(void); int microcode_init_amd(void); =20 --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 156617778495186.73385767125797; Sun, 18 Aug 2019 18:23:04 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWN0-0001Qq-O9; Mon, 19 Aug 2019 01:22:02 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWMz-0001Px-RL for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:22:01 +0000 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id bebbd22c-c21f-11e9-8be6-12813bfff9fa; Mon, 19 Aug 2019 01:22:01 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:22:01 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:21:59 -0700 X-Inumbo-ID: bebbd22c-c21f-11e9-8be6-12813bfff9fa X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683947" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:25 +0800 Message-Id: <1566177928-19114-13-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 12/15] microcode: reduce memory allocation and copy when creating a patch X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To create a microcode patch from a vendor-specific update, allocate_microcode_patch() copied everything from the update. It is not efficient. Essentially, we just need to go through ucodes in the blob, find the one with the newest revision and install it into the microcode_patch. In the process, buffers like mc_amd, equiv_cpu_table (on AMD side), and mc (on Intel side) can be reused. microcode_patch now is allocated after it is sure that there is a matching ucode. Signed-off-by: Chao Gao Reviewed-by: Roger Pau Monn=C3=A9 --- Changes in v9: - new --- xen/arch/x86/microcode_amd.c | 99 +++++++++++++++-----------------------= ---- xen/arch/x86/microcode_intel.c | 65 ++++++++++----------------- 2 files changed, 58 insertions(+), 106 deletions(-) diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index 6353323..ec1c2eb 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -194,36 +194,6 @@ static bool match_cpu(const struct microcode_patch *pa= tch) return patch && (microcode_fits(patch->mc_amd) =3D=3D NEW_UCODE); } =20 -static struct microcode_patch *alloc_microcode_patch( - const struct microcode_amd *mc_amd) -{ - struct microcode_patch *microcode_patch =3D xmalloc(struct microcode_p= atch); - struct microcode_amd *cache =3D xmalloc(struct microcode_amd); - void *mpb =3D xmalloc_bytes(mc_amd->mpb_size); - struct equiv_cpu_entry *equiv_cpu_table =3D - xmalloc_bytes(mc_amd->equiv_cpu_table_size= ); - - if ( !microcode_patch || !cache || !mpb || !equiv_cpu_table ) - { - xfree(microcode_patch); - xfree(cache); - xfree(mpb); - xfree(equiv_cpu_table); - return ERR_PTR(-ENOMEM); - } - - memcpy(mpb, mc_amd->mpb, mc_amd->mpb_size); - cache->mpb =3D mpb; - cache->mpb_size =3D mc_amd->mpb_size; - memcpy(equiv_cpu_table, mc_amd->equiv_cpu_table, - mc_amd->equiv_cpu_table_size); - cache->equiv_cpu_table =3D equiv_cpu_table; - cache->equiv_cpu_table_size =3D mc_amd->equiv_cpu_table_size; - microcode_patch->mc_amd =3D cache; - - return microcode_patch; -} - static void free_patch(void *mc) { struct microcode_amd *mc_amd =3D mc; @@ -320,18 +290,10 @@ static int get_ucode_from_buffer_amd( return -EINVAL; } =20 - if ( mc_amd->mpb_size < mpbuf->len ) - { - if ( mc_amd->mpb ) - { - xfree(mc_amd->mpb); - mc_amd->mpb_size =3D 0; - } - mc_amd->mpb =3D xmalloc_bytes(mpbuf->len); - if ( mc_amd->mpb =3D=3D NULL ) - return -ENOMEM; - mc_amd->mpb_size =3D mpbuf->len; - } + mc_amd->mpb =3D xmalloc_bytes(mpbuf->len); + if ( mc_amd->mpb =3D=3D NULL ) + return -ENOMEM; + mc_amd->mpb_size =3D mpbuf->len; memcpy(mc_amd->mpb, mpbuf->data, mpbuf->len); =20 pr_debug("microcode: CPU%d size %zu, block size %u offset %zu equivID = %#x rev %#x\n", @@ -451,8 +413,9 @@ static struct microcode_patch *cpu_request_microcode(co= nst void *buf, size_t bufsize) { struct microcode_amd *mc_amd; + struct microcode_header_amd *saved =3D NULL; struct microcode_patch *patch =3D NULL; - size_t offset =3D 0; + size_t offset =3D 0, saved_size =3D 0; int error =3D 0; unsigned int current_cpu_id; unsigned int equiv_cpu_id; @@ -542,29 +505,21 @@ static struct microcode_patch *cpu_request_microcode(= const void *buf, while ( (error =3D get_ucode_from_buffer_amd(mc_amd, buf, bufsize, &offset)) =3D=3D 0 ) { - struct microcode_patch *new_patch =3D alloc_microcode_patch(mc_amd= ); - - if ( IS_ERR(new_patch) ) - { - error =3D PTR_ERR(new_patch); - break; - } - /* - * If the new patch covers current CPU, compare patches and store = the + * If the new ucode covers current CPU, compare ucodes and store t= he * one with higher revision. */ - if ( (microcode_fits(new_patch->mc_amd) !=3D MIS_UCODE) && - (!patch || (compare_patch(new_patch, patch) =3D=3D NEW_UCODE)= ) ) +#define REV_ID(mpb) (((struct microcode_header_amd *)(mpb))->processor_rev= _id) + if ( (microcode_fits(mc_amd) !=3D MIS_UCODE) && + (!saved || (REV_ID(mc_amd->mpb) > REV_ID(saved))) ) +#undef REV_ID { - struct microcode_patch *tmp =3D patch; - - patch =3D new_patch; - new_patch =3D tmp; + xfree(saved); + saved =3D mc_amd->mpb; + saved_size =3D mc_amd->mpb_size; } - - if ( new_patch ) - microcode_free_patch(new_patch); + else + xfree(mc_amd->mpb); =20 if ( offset >=3D bufsize ) break; @@ -593,9 +548,25 @@ static struct microcode_patch *cpu_request_microcode(c= onst void *buf, *(const uint32_t *)(buf + offset) =3D=3D UCODE_MAGIC ) break; } - xfree(mc_amd->mpb); - xfree(mc_amd->equiv_cpu_table); - xfree(mc_amd); + + if ( saved ) + { + mc_amd->mpb =3D saved; + mc_amd->mpb_size =3D saved_size; + patch =3D xmalloc(struct microcode_patch); + if ( patch ) + patch->mc_amd =3D mc_amd; + else + { + free_patch(mc_amd); + error =3D -ENOMEM; + } + } + else + { + mc_amd->mpb =3D NULL; + free_patch(mc_amd); + } =20 out: if ( error && !patch ) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 96b38f8..ae5759f 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -282,25 +282,6 @@ static enum microcode_match_result compare_patch( OLD_UCODE; } =20 -static struct microcode_patch *alloc_microcode_patch( - const struct microcode_header_intel *mc_header) -{ - unsigned long total_size =3D get_totalsize(mc_header); - void *new_mc =3D xmalloc_bytes(total_size); - struct microcode_patch *new_patch =3D xmalloc(struct microcode_patch); - - if ( !new_patch || !new_mc ) - { - xfree(new_patch); - xfree(new_mc); - return ERR_PTR(-ENOMEM); - } - memcpy(new_mc, mc_header, total_size); - new_patch->mc_intel =3D new_mc; - - return new_patch; -} - static int apply_microcode(const struct microcode_patch *patch) { unsigned long flags; @@ -379,47 +360,47 @@ static struct microcode_patch *cpu_request_microcode(= const void *buf, { long offset =3D 0; int error =3D 0; - void *mc; + struct microcode_intel *mc, *saved =3D NULL; struct microcode_patch *patch =3D NULL; =20 - while ( (offset =3D get_next_ucode_from_buffer(&mc, buf, size, offset)= ) > 0 ) + while ( (offset =3D get_next_ucode_from_buffer((void **)&mc, buf, + size, offset)) > 0 ) { - struct microcode_patch *new_patch; - error =3D microcode_sanity_check(mc); if ( error ) - break; - - new_patch =3D alloc_microcode_patch(mc); - if ( IS_ERR(new_patch) ) { - error =3D PTR_ERR(new_patch); + xfree(mc); break; } =20 /* - * If the new patch covers current CPU, compare patches and store = the + * If the new update covers current CPU, compare updates and store= the * one with higher revision. */ - if ( (microcode_update_match(&new_patch->mc_intel->hdr) !=3D MIS_U= CODE) && - (!patch || (compare_patch(new_patch, patch) =3D=3D NEW_UCODE)= ) ) + if ( (microcode_update_match(&mc->hdr) !=3D MIS_UCODE) && + (!saved || (mc->hdr.rev > saved->hdr.rev)) ) { - struct microcode_patch *tmp =3D patch; - - patch =3D new_patch; - new_patch =3D tmp; + xfree(saved); + saved =3D mc; } - - if ( new_patch ) - microcode_free_patch(new_patch); - - xfree(mc); + else + xfree(mc); } - if ( offset > 0 ) - xfree(mc); if ( offset < 0 ) error =3D offset; =20 + if ( saved ) + { + patch =3D xmalloc(struct microcode_patch); + if ( patch ) + patch->mc_intel =3D saved; + else + { + xfree(saved); + error =3D -ENOMEM; + } + } + if ( error && !patch ) patch =3D ERR_PTR(error); =20 --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177815; cv=none; d=zoho.com; s=zohoarc; b=RzPTQPq9dlhtjMlXvcfJnGk2pueDuy4RANKlWQFMiSNQ1HGdDrlhG9fdsIB6SE3hNdNP07PmX9SJ+1xKgYqHSTiAPhBaSlLjSPWjlQhML5cOKeFFz29Y9M+TkR2c0DKMK+mdYvSVq7nZa23jtfth6tOr1Q+Oy9pBl45i2a8JNiw= ARC-Message-Signature: i=1; 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Mon, 19 Aug 2019 01:22:24 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWNK-0001h2-I7 for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:22:22 +0000 Received: from mga09.intel.com (unknown [134.134.136.24]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ca6eb12a-c21f-11e9-aee9-bc764e2007e4; Mon, 19 Aug 2019 01:22:21 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:22:20 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:22:17 -0700 X-Inumbo-ID: ca6eb12a-c21f-11e9-aee9-bc764e2007e4 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261683986" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:26 +0800 Message-Id: <1566177928-19114-14-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 13/15] x86/microcode: Synchronize late microcode loading X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Borislav Petkov , Ashok Raj , Wei Liu , Jun Nakajima , Andrew Cooper , Jan Beulich , Thomas Gleixner , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch ports microcode improvement patches from linux kernel. Before you read any further: the early loading method is still the preferred one and you should always do that. The following patch is improving the late loading mechanism for long running jobs and cloud use cases. Gather all cores and serialize the microcode update on them by doing it one-by-one to make the late update process as reliable as possible and avoid potential issues caused by the microcode update. Signed-off-by: Chao Gao Tested-by: Chao Gao [linux commit: a5321aec6412b20b5ad15db2d6b916c05349dbff] [linux commit: bb8c13d61a629276a162c1d2b1a20a815cbcfbb7] Cc: Kevin Tian Cc: Jun Nakajima Cc: Ashok Raj Cc: Borislav Petkov Cc: Thomas Gleixner Cc: Andrew Cooper Cc: Jan Beulich --- Changes in v9: - log __buildin_return_address(0) when timeout - divide CPUs into three logical sets and they will call different functions during ucode loading. The 'control thread' is chosen to coordinate ucode loading on all CPUs. Since only control thread would set 'loading_state', we can get rid of 'cmpxchg' stuff in v8. - s/rep_nop/cpu_relax - each thread updates its revision number itself - add XENLOG_ERR prefix for each line of multi-line log messages Changes in v8: - to support blocking #NMI handling during loading ucode * introduce a flag, 'loading_state', to mark the start or end of ucode loading. * use a bitmap for cpu callin since if cpu may stay in #NMI handling, there are two places for a cpu to call in. bitmap won't be counted twice. * don't wait for all CPUs callout, just wait for CPUs that perform the update. We have to do this because some threads may be stuck in NMI handling (where cannot reach the rendezvous). - emit a warning if the system stays in stop_machine context for more than 1s - comment that rdtsc is fine while loading an update - use cmpxchg() to avoid panic being called on multiple CPUs - Propagate revision number to other threads - refine comments and prompt messages Changes in v7: - Check whether 'timeout' is 0 rather than "<=3D0" since it is unsigned in= t. - reword the comment above microcode_update_cpu() to clearly state that one thread per core should do the update. --- xen/arch/x86/microcode.c | 289 +++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 267 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index bdd9c9f..91f9e81 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -30,18 +30,52 @@ #include #include #include +#include #include #include #include +#include =20 +#include #include #include #include #include =20 +/* + * Before performing a late microcode update on any thread, we + * rendezvous all cpus in stop_machine context. The timeout for + * waiting for cpu rendezvous is 30ms. It is the timeout used by + * live patching + */ +#define MICROCODE_CALLIN_TIMEOUT_US 30000 + +/* + * Timeout for each thread to complete update is set to 1s. It is a + * conservative choice considering all possible interference. + */ +#define MICROCODE_UPDATE_TIMEOUT_US 1000000 + static module_t __initdata ucode_mod; static signed int __initdata ucode_mod_idx; static bool_t __initdata ucode_mod_forced; +static unsigned int nr_cores; + +/* + * These states help to coordinate CPUs during loading an update. + * + * The semantics of each state is as follow: + * - LOADING_PREPARE: initial state of 'loading_state'. + * - LOADING_CALLIN: CPUs are allowed to callin. + * - LOADING_ENTER: all CPUs have called in. Initiate ucode loading. + * - LOADING_EXIT: ucode loading is done or aborted. + */ +static enum { + LOADING_PREPARE, + LOADING_CALLIN, + LOADING_ENTER, + LOADING_EXIT, +} loading_state; =20 /* * If we scan the initramfs.cpio for the early microcode code @@ -190,6 +224,16 @@ static DEFINE_SPINLOCK(microcode_mutex); DEFINE_PER_CPU(struct cpu_signature, cpu_sig); =20 /* + * Count the CPUs that have entered, exited the rendezvous and succeeded in + * microcode update during late microcode update respectively. + * + * Note that a bitmap is used for callin to allow cpu to set a bit multiple + * times. It is required to do busy-loop in #NMI handling. + */ +static cpumask_t cpu_callin_map; +static atomic_t cpu_out, cpu_updated; + +/* * Return a patch that covers current CPU. If there are multiple patches, * return the one with the highest revision number. Return error If no * patch is found and an error occurs during the parsing process. Otherwise @@ -232,6 +276,34 @@ bool microcode_update_cache(struct microcode_patch *pa= tch) return true; } =20 +/* Wait for a condition to be met with a timeout (us). */ +static int wait_for_condition(int (*func)(void *data), void *data, + unsigned int timeout) +{ + while ( !func(data) ) + { + if ( !timeout-- ) + { + printk("CPU%u: Timeout in %pS\n", + smp_processor_id(), __builtin_return_address(0)); + return -EBUSY; + } + udelay(1); + } + + return 0; +} + +static int wait_cpu_callin(void *nr) +{ + return cpumask_weight(&cpu_callin_map) >=3D (unsigned long)nr; +} + +static int wait_cpu_callout(void *nr) +{ + return atomic_read(&cpu_out) >=3D (unsigned long)nr; +} + /* * Load a microcode update to current CPU. * @@ -265,37 +337,155 @@ static int microcode_update_cpu(const struct microco= de_patch *patch) return err; } =20 -static long do_microcode_update(void *patch) +static int slave_thread_fn(void) +{ + unsigned int cpu =3D smp_processor_id(); + unsigned int master =3D cpumask_first(this_cpu(cpu_sibling_mask)); + + while ( loading_state !=3D LOADING_CALLIN ) + cpu_relax(); + + cpumask_set_cpu(cpu, &cpu_callin_map); + + while ( loading_state !=3D LOADING_EXIT ) + cpu_relax(); + + /* Copy update revision from the "master" thread. */ + this_cpu(cpu_sig).rev =3D per_cpu(cpu_sig, master).rev; + + return 0; +} + +static int master_thread_fn(const struct microcode_patch *patch) +{ + unsigned int cpu =3D smp_processor_id(); + int ret =3D 0; + + while ( loading_state !=3D LOADING_CALLIN ) + cpu_relax(); + + cpumask_set_cpu(cpu, &cpu_callin_map); + + while ( loading_state !=3D LOADING_ENTER ) + cpu_relax(); + + /* + * If an error happened, control thread would set 'loading_state' + * to LOADING_EXIT. Don't perform ucode loading for this case + */ + if ( loading_state =3D=3D LOADING_EXIT ) + return ret; + + ret =3D microcode_ops->apply_microcode(patch); + if ( !ret ) + atomic_inc(&cpu_updated); + atomic_inc(&cpu_out); + + while ( loading_state !=3D LOADING_EXIT ) + cpu_relax(); + + return ret; +} + +static int control_thread_fn(const struct microcode_patch *patch) { - unsigned int cpu; + unsigned int cpu =3D smp_processor_id(), done; + unsigned long tick; + int ret; =20 - /* Store the patch after a successful loading */ - if ( !microcode_update_cpu(patch) && patch ) + /* Allow threads to call in */ + loading_state =3D LOADING_CALLIN; + smp_mb(); + + cpumask_set_cpu(cpu, &cpu_callin_map); + + /* Waiting for all threads calling in */ + ret =3D wait_for_condition(wait_cpu_callin, + (void *)(unsigned long)num_online_cpus(), + MICROCODE_CALLIN_TIMEOUT_US); + if ( ret ) { + loading_state =3D LOADING_EXIT; + return ret; + } + + /* Let master threads load the given ucode update */ + loading_state =3D LOADING_ENTER; + smp_mb(); + + ret =3D microcode_ops->apply_microcode(patch); + if ( !ret ) + atomic_inc(&cpu_updated); + atomic_inc(&cpu_out); + + tick =3D rdtsc_ordered(); + /* Waiting for master threads finishing update */ + done =3D atomic_read(&cpu_out); + while ( done !=3D nr_cores ) { - spin_lock(µcode_mutex); - microcode_update_cache(patch); - spin_unlock(µcode_mutex); - patch =3D NULL; + /* + * During each timeout interval, at least a CPU is expected to + * finish its update. Otherwise, something goes wrong. + * + * Note that RDTSC (in wait_for_condition()) is safe for threads to + * execute while waiting for completion of loading an update. + */ + if ( wait_for_condition(wait_cpu_callout, + (void *)(unsigned long)(done + 1), + MICROCODE_UPDATE_TIMEOUT_US) ) + panic("Timeout when finished updating microcode (finished %u/%= u)", + done, nr_cores); + + /* Print warning message once if long time is spent here */ + if ( tick && rdtsc_ordered() - tick >=3D cpu_khz * 1000 ) + { + printk(XENLOG_WARNING + "WARNING: UPDATING MICROCODE HAS CONSUMED MORE THAN 1 S= ECOND!\n"); + tick =3D 0; + } + done =3D atomic_read(&cpu_out); } =20 - if ( microcode_ops->end_update ) - microcode_ops->end_update(); + /* Mark loading is done to unblock other threads */ + loading_state =3D LOADING_EXIT; + smp_mb(); =20 - cpu =3D cpumask_next(smp_processor_id(), &cpu_online_map); - if ( cpu < nr_cpu_ids ) - return continue_hypercall_on_cpu(cpu, do_microcode_update, patch); + return ret; +} =20 - /* Free the patch if no CPU has loaded it successfully. */ - if ( patch ) - microcode_free_patch(patch); +static int do_microcode_update(void *patch) +{ + unsigned int cpu =3D smp_processor_id(); + /* + * "master" thread is the one with the lowest thread id among all sibl= ings + * thread in a core or a compute unit. It is chosen to load a microcode + * update. + */ + unsigned int master =3D cpumask_first(this_cpu(cpu_sibling_mask)); + int ret; =20 - return 0; + /* + * The control thread set state to coordinate ucode loading. Master th= reads + * load the given ucode patch. Slave threads just wait for the complet= ion + * of the ucode loading process. + */ + if ( cpu =3D=3D cpumask_first(&cpu_online_map) ) + ret =3D control_thread_fn(patch); + else if ( cpu =3D=3D master ) + ret =3D master_thread_fn(patch); + else + ret =3D slave_thread_fn(); + + if ( microcode_ops->end_update ) + microcode_ops->end_update(); + + return ret; } =20 int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void) buf, unsigned long= len) { int ret; void *buffer; + unsigned int cpu, updated; struct microcode_patch *patch; =20 if ( len !=3D (uint32_t)len ) @@ -314,11 +504,18 @@ int microcode_update(XEN_GUEST_HANDLE_PARAM(const_voi= d) buf, unsigned long len) goto free; } =20 + /* cpu_online_map must not change during update */ + if ( !get_cpu_maps() ) + { + ret =3D -EBUSY; + goto free; + } + if ( microcode_ops->start_update ) { ret =3D microcode_ops->start_update(); if ( ret !=3D 0 ) - goto free; + goto put; } =20 patch =3D parse_blob(buffer, len); @@ -326,19 +523,67 @@ int microcode_update(XEN_GUEST_HANDLE_PARAM(const_voi= d) buf, unsigned long len) { ret =3D PTR_ERR(patch); printk(XENLOG_INFO "Parsing microcode blob error %d\n", ret); - goto free; + goto put; } =20 if ( !patch ) { printk(XENLOG_INFO "No ucode found. Update aborted!\n"); ret =3D -EINVAL; - goto free; + goto put; + } + + cpumask_clear(&cpu_callin_map); + atomic_set(&cpu_out, 0); + atomic_set(&cpu_updated, 0); + loading_state =3D LOADING_PREPARE; + + /* Calculate the number of online CPU core */ + nr_cores =3D 0; + for_each_online_cpu(cpu) + if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu)) ) + nr_cores++; + + printk(XENLOG_INFO "%u cores are to update their microcode\n", nr_core= s); + + /* + * We intend to disable interrupt for long time, which may lead to + * watchdog timeout. + */ + watchdog_disable(); + /* + * Late loading dance. Why the heavy-handed stop_machine effort? + * + * - HT siblings must be idle and not execute other code while the oth= er + * sibling is loading microcode in order to avoid any negative + * interactions cause by the loading. + * + * - In addition, microcode update on the cores must be serialized unt= il + * this requirement can be relaxed in the future. Right now, this is + * conservative and good. + */ + ret =3D stop_machine_run(do_microcode_update, patch, NR_CPUS); + watchdog_enable(); + + updated =3D atomic_read(&cpu_updated); + if ( updated > 0 ) + { + spin_lock(µcode_mutex); + microcode_update_cache(patch); + spin_unlock(µcode_mutex); } + else + microcode_free_patch(patch); =20 - ret =3D continue_hypercall_on_cpu(cpumask_first(&cpu_online_map), - do_microcode_update, patch); + if ( updated && updated !=3D nr_cores ) + printk(XENLOG_ERR "ERROR: Updating microcode succeeded on %u cores= and failed\n" + XENLOG_ERR "on other %u cores. A system with differing micr= ocode \n" + XENLOG_ERR "revisions is considered unstable. Please reboot= and do not\n" + XENLOG_ERR "load the microcode that triggersthis warning!\n= ", + updated, nr_cores - updated); =20 + put: + put_cpu_maps(); free: xfree(buffer); return ret; --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566177812; cv=none; d=zoho.com; s=zohoarc; b=f2iVXpRvTmuVGT6+CaF4Pzcr/7EOAwenZ/Sw1bwv5s17rxL/aas5VDZVTe319KMdvUgHXTZU7VrQBolfjq5XG6t8iMNy4mg4vMFBMd+U4it7elq1XoXnKQI+qflANVHV8NXYWmcZPyh38Ip5DEUYkbfNGByw60mn/ahclmaLGmo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566177812; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=q0nKuoCUMT0RxlgejaVo9PkgWYzKwW6docccxCcI3M8=; b=VGXU4nNubGOICv2hAUuSeNY0vrMHMXIl5JFy2Q9ivdctGx1iNHk6d79tvbGCbJrXg2s+DFLsWGJDX2IpHLCF0GFfivx7v2SfX5m/a/owUlZSqfSSiNwgy8j2ByhAml4bar1bTWazb++aAeh1Q3HDl3cRttN3/9Ug9Hogi1zf0JE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1566177812809580.4919415699832; Sun, 18 Aug 2019 18:23:32 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWNR-0001ml-Dq; Mon, 19 Aug 2019 01:22:29 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hzWNQ-0001la-Az for xen-devel@lists.xenproject.org; Mon, 19 Aug 2019 01:22:28 +0000 Received: from mga09.intel.com (unknown [134.134.136.24]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ce4549f8-c21f-11e9-aee9-bc764e2007e4; Mon, 19 Aug 2019 01:22:27 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Aug 2019 18:22:27 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:22:25 -0700 X-Inumbo-ID: ce4549f8-c21f-11e9-aee9-bc764e2007e4 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261684027" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:27 +0800 Message-Id: <1566177928-19114-15-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 14/15] microcode: remove microcode_update_lock X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" microcode_update_lock is to prevent logic threads of a same core from updating microcode at the same time. But due to using a global lock, it also prevented parallel microcode updating on different cores. Remove this lock in order to update microcode in parallel. It is safe because we have already ensured serialization of sibling threads at the caller side. 1.For late microcode update, do_microcode_update() ensures that only one sibiling thread of a core can update microcode. 2.For microcode update during system startup or CPU-hotplug, microcode_mutex() guarantees update serialization of logical threads. 3.get/put_cpu_bitmaps() prevents the concurrency of CPU-hotplug and late microcode update. Note that printk in apply_microcode() and svm_host_osvm_init() (for AMD only) are still processed sequentially. Signed-off-by: Chao Gao Reviewed-by: Jan Beulich --- Changes in v7: - reworked. Remove complex lock logics introduced in v5 and v6. The microc= ode patch to be applied is passed as an argument without any global variable. = Thus no lock is added to serialize potential readers/writers. Callers of apply_microcode() will guarantee the correctness: the patch poninted by the arguments won't be changed by others. Changes in v6: - introduce early_ucode_update_lock to serialize early ucode update. Changes in v5: - newly add --- xen/arch/x86/microcode_amd.c | 8 +------- xen/arch/x86/microcode_intel.c | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/xen/arch/x86/microcode_amd.c b/xen/arch/x86/microcode_amd.c index ec1c2eb..8685b3e 100644 --- a/xen/arch/x86/microcode_amd.c +++ b/xen/arch/x86/microcode_amd.c @@ -74,9 +74,6 @@ struct mpbhdr { uint8_t data[]; }; =20 -/* serialize access to the physical write */ -static DEFINE_SPINLOCK(microcode_update_lock); - /* See comment in start_update() for cases when this routine fails */ static int collect_cpu_info(struct cpu_signature *csig) { @@ -220,7 +217,6 @@ static enum microcode_match_result compare_patch( =20 static int apply_microcode(const struct microcode_patch *patch) { - unsigned long flags; uint32_t rev; int hw_err; unsigned int cpu =3D smp_processor_id(); @@ -232,15 +228,13 @@ static int apply_microcode(const struct microcode_pat= ch *patch) =20 hdr =3D patch->mc_amd->mpb; =20 - spin_lock_irqsave(µcode_update_lock, flags); + BUG_ON(local_irq_is_enabled()); =20 hw_err =3D wrmsr_safe(MSR_AMD_PATCHLOADER, (unsigned long)hdr); =20 /* get patch id after patching */ rdmsrl(MSR_AMD_PATCHLEVEL, rev); =20 - spin_unlock_irqrestore(µcode_update_lock, flags); - /* * Some processors leave the ucode blob mapping as UC after the update. * Flush the mapping to regain normal cacheability. diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index ae5759f..6186461 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -93,9 +93,6 @@ struct extended_sigtable { =20 #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_S= IZE) =20 -/* serialize access to the physical write to MSR 0x79 */ -static DEFINE_SPINLOCK(microcode_update_lock); - static int collect_cpu_info(struct cpu_signature *csig) { unsigned int cpu_num =3D smp_processor_id(); @@ -284,7 +281,6 @@ static enum microcode_match_result compare_patch( =20 static int apply_microcode(const struct microcode_patch *patch) { - unsigned long flags; uint64_t msr_content; unsigned int val[2]; unsigned int cpu_num =3D raw_smp_processor_id(); @@ -296,8 +292,7 @@ static int apply_microcode(const struct microcode_patch= *patch) =20 mc_intel =3D patch->mc_intel; =20 - /* serialize access to the physical write to MSR 0x79 */ - spin_lock_irqsave(µcode_update_lock, flags); + BUG_ON(local_irq_is_enabled()); =20 /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); @@ -310,7 +305,6 @@ static int apply_microcode(const struct microcode_patch= *patch) rdmsrl(MSR_IA32_UCODE_REV, msr_content); val[1] =3D (uint32_t)(msr_content >> 32); =20 - spin_unlock_irqrestore(µcode_update_lock, flags); if ( val[1] !=3D mc_intel->hdr.rev ) { printk(KERN_ERR "microcode: CPU%d update from revision " --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Sun May 19 01:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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18 Aug 2019 18:22:31 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga001.jf.intel.com with ESMTP; 18 Aug 2019 18:22:30 -0700 X-Inumbo-ID: d1010542-c21f-11e9-aee9-bc764e2007e4 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,403,1559545200"; d="scan'208";a="261684035" From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 19 Aug 2019 09:25:28 +0800 Message-Id: <1566177928-19114-16-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566177928-19114-1-git-send-email-chao.gao@intel.com> References: <1566177928-19114-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v9 15/15] microcode: block #NMI handling when loading an ucode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" register an nmi callback. And this callback does busy-loop on threads which are waiting for loading completion. Control threads send NMI to slave threads to prevent NMI acceptance during ucode loading. Signed-off-by: Chao Gao --- Changes in v9: - control threads send NMI to all other threads. Slave threads will stay in the NMI handling to prevent NMI acceptance during ucode loading. Note that self-nmi is invalid according to SDM. - s/rep_nop/cpu_relax - remove debug message in microcode_nmi_callback(). Printing debug message would take long times and control thread may timeout. - rebase and fix conflicts Changes in v8: - new --- xen/arch/x86/microcode.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/microcode.c b/xen/arch/x86/microcode.c index 91f9e81..d943835 100644 --- a/xen/arch/x86/microcode.c +++ b/xen/arch/x86/microcode.c @@ -38,6 +38,7 @@ =20 #include #include +#include #include #include #include @@ -339,14 +340,8 @@ static int microcode_update_cpu(const struct microcode= _patch *patch) =20 static int slave_thread_fn(void) { - unsigned int cpu =3D smp_processor_id(); unsigned int master =3D cpumask_first(this_cpu(cpu_sibling_mask)); =20 - while ( loading_state !=3D LOADING_CALLIN ) - cpu_relax(); - - cpumask_set_cpu(cpu, &cpu_callin_map); - while ( loading_state !=3D LOADING_EXIT ) cpu_relax(); =20 @@ -399,6 +394,8 @@ static int control_thread_fn(const struct microcode_pat= ch *patch) =20 cpumask_set_cpu(cpu, &cpu_callin_map); =20 + smp_send_nmi_allbutself(); + /* Waiting for all threads calling in */ ret =3D wait_for_condition(wait_cpu_callin, (void *)(unsigned long)num_online_cpus(), @@ -481,12 +478,28 @@ static int do_microcode_update(void *patch) return ret; } =20 +static int microcode_nmi_callback(const struct cpu_user_regs *regs, int cp= u) +{ + /* The first thread of a core is to load an update. Don't block it. */ + if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu)) || + loading_state !=3D LOADING_CALLIN ) + return 0; + + cpumask_set_cpu(cpu, &cpu_callin_map); + + while ( loading_state !=3D LOADING_EXIT ) + cpu_relax(); + + return 0; +} + int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void) buf, unsigned long= len) { int ret; void *buffer; unsigned int cpu, updated; struct microcode_patch *patch; + nmi_callback_t *saved_nmi_callback; =20 if ( len !=3D (uint32_t)len ) return -E2BIG; @@ -551,6 +564,8 @@ int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void)= buf, unsigned long len) * watchdog timeout. */ watchdog_disable(); + + saved_nmi_callback =3D set_nmi_callback(microcode_nmi_callback); /* * Late loading dance. Why the heavy-handed stop_machine effort? * @@ -563,6 +578,7 @@ int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void)= buf, unsigned long len) * conservative and good. */ ret =3D stop_machine_run(do_microcode_update, patch, NR_CPUS); + set_nmi_callback(saved_nmi_callback); watchdog_enable(); =20 updated =3D atomic_read(&cpu_updated); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel