From nobody Mon Feb 9 18:18:21 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1558945738; cv=none; d=zoho.com; s=zohoarc; b=C5uoq0gy1GYoI/90I3uoeNeziVJ3VvLN6HHpqmICjPBcJilXJ08JB8Fjd/yqo1xjLexIGRkfSCuIXWvfsxEsvoRb10STk0T5Tp42QT7rVkRV8DdYkOCJikVlQyoTlxzE3xKcvPNKv8m5DfHPuPKFU1W53AxUmNL1WkRRy76wMCo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558945738; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=3uWZswc2CC5F3QIHYz/GPbNwdoNSdYqaAnXCA6qlqMw=; b=d/fcCNLUTGEnxwREh5nUBLnlhHRXP18iHRQhP2e5Gh5d3oKAvi33muKswWTDML4MfQlEklZPFt04qXIQv3IG7004Wif1YQ9cv0yF7ctArsFObx327nDFxdp5H4fkRpgV+xfWdnZDRdw5EuBwDsRLI+wua3Ml5DHqnMxWQ09KY24= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1558945738905292.84804728685026; Mon, 27 May 2019 01:28:58 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hVAys-0004GI-LP; Mon, 27 May 2019 08:27:42 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hVAyr-0004FG-F9 for xen-devel@lists.xenproject.org; Mon, 27 May 2019 08:27:41 +0000 Received: from mga12.intel.com (unknown [192.55.52.136]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 4a960c5d-8059-11e9-8980-bc764e045a96; Mon, 27 May 2019 08:27:40 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 May 2019 01:27:40 -0700 Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga005.jf.intel.com with ESMTP; 27 May 2019 01:27:38 -0700 X-Inumbo-ID: 4a960c5d-8059-11e9-8980-bc764e045a96 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 From: Chao Gao To: xen-devel@lists.xenproject.org Date: Mon, 27 May 2019 16:31:28 +0800 Message-Id: <1558945891-3015-8-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558945891-3015-1-git-send-email-chao.gao@intel.com> References: <1558945891-3015-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v7 07/10] microcode/intel: Writeback and invalidate caches before updating microcode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Sergey Dyasli , Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Updating microcode is less error prone when caches have been flushed and depending on what exactly the microcode is updating. For example, some of the issues around certain Broadwell parts can be addressed by doing a full cache flush. With parallel microcode update, the cost of this patch is hardly noticable. Although only BDX with an old microcode needs this fix, we would like to avoid future issues in case they come by later due to other reasons. [linux commit: 91df9fdf51492aec9fed6b4cbd33160886740f47] Signed-off-by: Chao Gao Cc: Ashok Raj --- Changes in v7: - explain why we do 'wbinvd' unconditionally rather than only for BDX in commit message Changes in v6: - new --- xen/arch/x86/microcode_intel.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index 650495d..bfb48ce 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -310,6 +310,12 @@ static int apply_microcode(const struct microcode_patc= h *patch) /* serialize access to the physical write to MSR 0x79 */ spin_lock_irqsave(µcode_update_lock, flags); =20 + /* + * Writeback and invalidate caches before updating microcode to avoid + * internal issues depending on what the microcode is updating. + */ + wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL); --=20 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel