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[85.223.141.74]) by smtp.gmail.com with ESMTPSA id k21sm2659652ljb.3.2019.05.02.10.00.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 May 2019 10:00:32 -0700 (PDT) X-Inumbo-ID: cc8050da-6cfb-11e9-843c-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fVhiWDUpJkVyDHyxs5otEWi551gqM+tZ24ZpPo7GxZs=; b=Tw9ZUteZoiAJkFKhWWBiBQVPYCxWCug4ZNYmRDA7O4F2g1d5Y8Ipm5hpBDosc6KcMi s+Y5EVgSQT9gGtR9nMfFcetCmVm4QTvkitu2Bmiz+z6eL1ORl6T//ifYPBJ3jRaEnQsN Ier8cwV9zrOI7ZIh97fiFR3Ht9DSvmemKeRn84YJiwlYtJBVOtCIMpjW7nC+W6DGwdI4 zPd8uYft8ejex1hO60LxfKuwxZ1yqV7LjDGRFzXAqsCQmvRiPL5/DZLvh7lTR0AXHNbX pNxkKxstYO6itOeMeM0Ehhs4lD5ammby4Nvtxl/Ot41X/M/2ozEPVliOSRQMTRtoZvP/ c7UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fVhiWDUpJkVyDHyxs5otEWi551gqM+tZ24ZpPo7GxZs=; b=APFeBueentOQ+ku1SATg3L8IxRSrRq1P5ECKSzb8vhz058bhE7FtK3C5YubXnnLCj6 uqfjNVyqmxtgammr5bCE5uSXgUVp6mji2u46UWvhjJ5xO/H/A0HbRUlzYZOOl4Rgtsrj Q2RiaF42uHIPn/9ypnb9sFy1mFmM9WHRhIx9/beZj41k0e9XPPzq7xWuHzKS6DhxAmqW 03ZG75zBP1oJHde0CchEB8HRzsaEeo1m7xQw5lP86HcaInI/gnCDRjsAmT+LjrKhZGQD VkyMJGAGGbntR2jwSanCFonpDwnTHYgQhlTmn4PR/1Xm1OHb4laOWHtTPQleDRG8HhLG DBvw== X-Gm-Message-State: APjAAAVOr36ik15Fny7LaWqnNfHX3bq1yG1p3kkBYYbXrFMJT1JOTbFV LkloQsyJzJJwNRSBr3EdncxjV9jhFo4= X-Google-Smtp-Source: APXvYqwh3fUuiOYt7CXPkbIFOdXrtUsHymVTAUKVf16uoGQshxdwjEd6fRdYtxU1CmmNXCs0V4MwNA== X-Received: by 2002:a2e:5b5c:: with SMTP id p89mr2449823ljb.177.1556816432782; Thu, 02 May 2019 10:00:32 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Thu, 2 May 2019 20:00:20 +0300 Message-Id: <1556816422-25185-3-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> References: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V5 2/4] xen/arm: drivers: scif: Add support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko For the driver to be able to handle SCIFA interface as well, this patch just adds the following: - SCIFA related macros - New element in "port_params" array to keep SCIFA specific things - SCIFA compatible string This patch makes possible to use existing driver for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). Signed-off-by: Oleksandr Tyshchenko Acked-by: Julien Grall --- Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only adds SCIFA support Changes in v4: - Remove overrun_bit (SCASSR_ORER) from error_mask Changes in v5: - Add Julien's A-b --- xen/drivers/char/scif-uart.c | 17 ++++++++++++++++- xen/include/asm-arm/scif-uart.h | 40 +++++++++++++++++++++++++++++++++++++= +-- 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 85483ee..fa0b827 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -1,7 +1,7 @@ /* * xen/drivers/char/scif-uart.c * - * Driver for SCIF (Serial communication interface with FIFO) + * Driver for SCIF(A) (Serial communication interface with FIFO (A)) * compatible UART. * * Oleksandr Tyshchenko @@ -46,6 +46,7 @@ static struct scif_uart { enum port_types { SCIF_PORT, + SCIFA_PORT, NR_PORTS, }; =20 @@ -74,6 +75,19 @@ static const struct port_params port_params[NR_PORTS] = =3D .irq_flags =3D SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, .fifo_size =3D 16, }, + + [SCIFA_PORT] =3D + { + .status_reg =3D SCIFA_SCASSR, + .tx_fifo_reg =3D SCIFA_SCAFTDR, + .rx_fifo_reg =3D SCIFA_SCAFRDR, + .overrun_reg =3D SCIFA_SCASSR, + .overrun_mask =3D SCASSR_ORER, + .error_mask =3D SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER, + .irq_flags =3D SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_E= RIE | + SCASCR_BRIE, + .fifo_size =3D 64, + }, }; =20 static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs = *regs) @@ -273,6 +287,7 @@ static struct uart_driver __read_mostly scif_uart_drive= r =3D { static const struct dt_device_match scif_uart_dt_match[] __initconst =3D { { .compatible =3D "renesas,scif", .data =3D (void *)SCIF_PORT }, + { .compatible =3D "renesas,scifa", .data =3D (void *)SCIFA_PORT }, { /* sentinel */ }, }; =20 diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uar= t.h index c343f2f..bce3404 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -2,7 +2,7 @@ * xen/include/asm-arm/scif-uart.h * * Common constant definition between early printk and the UART driver - * for the SCIF compatible UART. + * for the SCIF(A) compatible UART. * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -21,7 +21,7 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H =20 -/* Register offsets */ +/* Register offsets (SCIF) */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ #define SCIF_SCSCR (0x08) /* Serial control register */ @@ -79,6 +79,42 @@ #define SCFCR_TTRG10 (SCFCR_TTRG1) #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) =20 +/* Register offsets (SCIFA) */ +#define SCIFA_SCASMR (0x00) /* Serial mode register */ +#define SCIFA_SCABRR (0x04) /* Bit rate register */ +#define SCIFA_SCASCR (0x08) /* Serial control register */ +#define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ +#define SCIFA_SCAFER (0x10) /* FIFO error count register */ +#define SCIFA_SCASSR (0x14) /* Serial status register */ +#define SCIFA_SCAFCR (0x18) /* FIFO control register */ +#define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ +#define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ +#define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ +#define SCIFA_SCAPCR (0x30) /* Serial port control register */ +#define SCIFA_SCAPDR (0x34) /* Serial port data register */ + +/* Serial Control Register (SCASCR) */ +#define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ +#define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ +#define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enabl= e */ +#define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ +#define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ +#define SCASCR_TE (1 << 5) /* Transmit Enable */ +#define SCASCR_RE (1 << 4) /* Receive Enable */ +#define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ + +/* Serial Status Register (SCASSR) */ +#define SCASSR_ORER (1 << 9) /* Overrun Error */ +#define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ +#define SCASSR_ER (1 << 7) /* Receive Error */ +#define SCASSR_TEND (1 << 6) /* Transmission End */ +#define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ +#define SCASSR_BRK (1 << 4) /* Break Detect */ +#define SCASSR_FER (1 << 3) /* Framing Error */ +#define SCASSR_PER (1 << 2) /* Parity Error */ +#define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ +#define SCASSR_DR (1 << 0) /* Receive Data Ready */ + #endif /* __ASM_ARM_SCIF_UART_H */ =20 /* --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel