From nobody Fri May 3 20:58:26 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1556816506; cv=none; d=zoho.com; s=zohoarc; b=hYrTFX+4s35/658drlgckiJzvXqNfiJy3Y2nelnsakI14JlKMRY/tU7FX/UZNkENvHy/XmF1XDcc22aimzY5OrDmOSWlEbJzAhLS9Kmtiolg/zpx0FJKdZXXLoYKckq+iba/xiBCEivQAP6ZH0Iepi0NBJKm9l7SGYiRxq4+mbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556816506; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dgnlT4YsOcPJnik35Ggzwj4NZVtotytC3k8HWgMla7Y=; b=QwrA/7jt6yV33eoxCgXV6QzXsoV1F7QMBZhzuk3TcGkaIZgr9kAezt1w5SEWbLgmLDrjViLkvzK4JTaKoOgJM4OSB2KrH0Qs9S3XwQ79s/YAEThWazu+5PcJEhMOPxu16yxzdEqnUPOtmRJzPPFfHvr6Qm5WAK8qdDygI+tXByg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1556816506621508.7924087515387; Thu, 2 May 2019 10:01:46 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hMF4W-0001yq-9y; Thu, 02 May 2019 17:00:36 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hMF4V-0001yY-8M for xen-devel@lists.xenproject.org; Thu, 02 May 2019 17:00:35 +0000 Received: from mail-lj1-x243.google.com (unknown [2a00:1450:4864:20::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id cbe23d36-6cfb-11e9-843c-bc764e045a96; Thu, 02 May 2019 17:00:33 +0000 (UTC) Received: by mail-lj1-x243.google.com with SMTP id c6so2829958lji.11 for ; Thu, 02 May 2019 10:00:33 -0700 (PDT) Received: from otyshchenko.kyiv.epam.com (ll-74.141.223.85.sovam.net.ua. [85.223.141.74]) by smtp.gmail.com with ESMTPSA id k21sm2659652ljb.3.2019.05.02.10.00.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 May 2019 10:00:30 -0700 (PDT) X-Inumbo-ID: cbe23d36-6cfb-11e9-843c-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WDAJn3JGw8cKVqYDvlPeha1oFr2+9sty0MQxx3x0on4=; b=MiNV/PuNsddERYzRLwTcqJy8r6gG1OSBL91SfU3VSLv+E9kjD5v84jVK2SJKPkOC6B m6v91F216QRTSPyjX1MJz5vCFDTdubsy4r+VZCnCRNmMX+zFb4dBIpuWSuO3layw45AG phA2Ozk50+djexVLAd1PkJ15HREPtkWcczoCkM9c2Rr41x1kP4s8vuKuV18DVggSQNIs O2mDaKC+XJfKrAjpCVtMBn2Zk9fjfvnTzko2UqVsO1Mz/W7r7MR3rAPxAAAQDjGpx0Uv nfMJZV902xPXLIcm3075eq90DR/i7OriIXM9lRrXhI5Wc/Q/rtfAtlfHp6FA13hFDX6o YF0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WDAJn3JGw8cKVqYDvlPeha1oFr2+9sty0MQxx3x0on4=; b=nL4S1xz+qg2Qun3joI3tj87E3Bf7I5SxlAOAm0RZgz6H1YxtYHMuv3Cupyb9GHlVsB rFyNeulf5uO8BF/eWY0spO86HDpVxvLoOUoVA7v5QKPtJaVT5bPgNFO+vnajsA/rY1Gp 6Wp9p7LVVyyqDSv8dM1U11sXhXvMmx7Lit5fHrOEXtuuECub2Ih4VY7ELTih/drxrDZ2 eAmglpPCsaLom8J2adxhWHPUURgiGUJdZX6nNdXjm/qZnEmNXOCcuo94tEBB+Wnn+ZJ3 KIM1a3YOfC2eR6I76+Dvb2D0upH2SzfUePt5EQbyKLsdKGcpOwtD3x2WrrLiW5lm7SFq tzNg== X-Gm-Message-State: APjAAAVMtURSWLHapwayKvLM6zFd4P8dQC7igO1F0zY8NhVeHXwe/qLQ m5sy7CWTI2H+g/MSKvG/yRaaPL+GH8k= X-Google-Smtp-Source: APXvYqxRJx0hCOdthASPr2PyZgNcueOog6b0bzmvusK9fCPUdSFn/qndo2v8FIwIv0uYyDrPBaTdhg== X-Received: by 2002:a2e:9753:: with SMTP id f19mr2716497ljj.54.1556816431695; Thu, 02 May 2019 10:00:31 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Thu, 2 May 2019 20:00:19 +0300 Message-Id: <1556816422-25185-2-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> References: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V5 1/4] xen/arm: drivers: scif: Extend driver to handle other interfaces X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko Extend driver to be able to handle other SCIF(X) compatible interfaces as well. These interfaces have lot in common, but mostly differ in offsets and bits for some registers. For example, the main difference between SCIF and SCIFA interfaces from "scif-uart" driver's point of view: - Registers offset: serial status, receive/transmit FIFO data registers have different offset - Internal FIFO size: 64 bytes for SCIFA and 16 bytes for SCIF - Overrun bit location: serial status register for SCIFA and dedicated line status register for SCIF Introduce "port_params" array to keep interface specific things. The "data" field in struct dt_device_match is used for recognizing what interface is present on a target board. Please note, nothing has been technically changed for Renesas "Lager" and other supported boards (SCIF). Signed-off-by: Oleksandr Tyshchenko Acked-by: Julien Grall --- Changes in v2: - Name a enum for describing interfaces this driver supports - Use local variable for "params" where appropriate - Use "data" field in struct dt_device_match instead of calling dt_device_is_compatible() - Don't check for "overrun_reg !=3D status_reg" condition during initialization Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only reworks a driver - Drop "port_type" variable from scif_uart_init(), pass a pointer directly Changes in v4: - Add ASSERT(match) in scif_uart_init() - Drop "if ( params->overrun_reg !=3D params->status_reg )" check in scif_uart_interrupt() and scif_uart_init_postirq() - Add an explanation to commit message Changes in v5: - Add Julien's A-b --- xen/drivers/char/scif-uart.c | 114 ++++++++++++++++++++++++++++--------= ---- xen/include/asm-arm/scif-uart.h | 4 -- 2 files changed, 80 insertions(+), 38 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 465fb34..85483ee 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -40,16 +40,51 @@ static struct scif_uart { char __iomem *regs; struct irqaction irqaction; struct vuart_info vuart; + const struct port_params *params; } scif_com =3D {0}; =20 +enum port_types +{ + SCIF_PORT, + NR_PORTS, +}; + +struct port_params +{ + unsigned int status_reg; + unsigned int tx_fifo_reg; + unsigned int rx_fifo_reg; + unsigned int overrun_reg; + unsigned int overrun_mask; + unsigned int error_mask; + unsigned int irq_flags; + unsigned int fifo_size; +}; + +static const struct port_params port_params[NR_PORTS] =3D +{ + [SCIF_PORT] =3D + { + .status_reg =3D SCIF_SCFSR, + .tx_fifo_reg =3D SCIF_SCFTDR, + .rx_fifo_reg =3D SCIF_SCFRDR, + .overrun_reg =3D SCIF_SCLSR, + .overrun_mask =3D SCLSR_ORER, + .error_mask =3D SCFSR_PER | SCFSR_FER | SCFSR_BRK | SCFSR_ER, + .irq_flags =3D SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, + .fifo_size =3D 16, + }, +}; + static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs = *regs) { struct serial_port *port =3D data; struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; uint16_t status, ctrl; =20 ctrl =3D scif_readw(uart, SCIF_SCSCR); - status =3D scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND; + status =3D scif_readw(uart, params->status_reg) & ~SCFSR_TEND; /* Ignore next flag if TX Interrupt is disabled */ if ( !(ctrl & SCSCR_TIE) ) status &=3D ~SCFSR_TDFE; @@ -65,13 +100,13 @@ static void scif_uart_interrupt(int irq, void *data, s= truct cpu_user_regs *regs) serial_rx_interrupt(port, regs); =20 /* Error Interrupt */ - if ( status & SCIF_ERRORS ) - scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS); - if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER ) - scif_writew(uart, SCIF_SCLSR, 0); + if ( status & params->error_mask ) + scif_writew(uart, params->status_reg, ~params->error_mask); + if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) + scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 ctrl =3D scif_readw(uart, SCIF_SCSCR); - status =3D scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND; + status =3D scif_readw(uart, params->status_reg) & ~SCFSR_TEND; /* Ignore next flag if TX Interrupt is disabled */ if ( !(ctrl & SCSCR_TIE) ) status &=3D ~SCFSR_TDFE; @@ -81,12 +116,13 @@ static void scif_uart_interrupt(int irq, void *data, s= truct cpu_user_regs *regs) static void __init scif_uart_init_preirq(struct serial_port *port) { struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; =20 /* * Wait until last bit has been transmitted. This is needed for a smoo= th * transition when we come from early printk */ - while ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TEND) ); + while ( !(scif_readw(uart, params->status_reg) & SCFSR_TEND) ); =20 /* Disable TX/RX parts and all interrupts */ scif_writew(uart, SCIF_SCSCR, 0); @@ -95,10 +131,10 @@ static void __init scif_uart_init_preirq(struct serial= _port *port) scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST); =20 /* Clear all errors and flags */ - scif_readw(uart, SCIF_SCFSR); - scif_writew(uart, SCIF_SCFSR, 0); - scif_readw(uart, SCIF_SCLSR); - scif_writew(uart, SCIF_SCLSR, 0); + scif_readw(uart, params->status_reg); + scif_writew(uart, params->status_reg, 0); + scif_readw(uart, params->overrun_reg); + scif_writew(uart, params->overrun_reg, 0); =20 /* Setup trigger level for TX/RX FIFOs */ scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11); @@ -111,6 +147,7 @@ static void __init scif_uart_init_preirq(struct serial_= port *port) static void __init scif_uart_init_postirq(struct serial_port *port) { struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; int rc; =20 uart->irqaction.handler =3D scif_uart_interrupt; @@ -122,14 +159,14 @@ static void __init scif_uart_init_postirq(struct seri= al_port *port) uart->irq); =20 /* Clear all errors */ - if ( scif_readw(uart, SCIF_SCFSR) & SCIF_ERRORS ) - scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS); - if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER ) - scif_writew(uart, SCIF_SCLSR, 0); + if ( scif_readw(uart, params->status_reg) & params->error_mask ) + scif_writew(uart, params->status_reg, ~params->error_mask); + if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) + scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | - SCSCR_TIE | SCSCR_RIE | SCSCR_REIE); + params->irq_flags); } =20 static void scif_uart_suspend(struct serial_port *port) @@ -145,43 +182,47 @@ static void scif_uart_resume(struct serial_port *port) static int scif_uart_tx_ready(struct serial_port *port) { struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; uint16_t cnt; =20 /* Check for empty space in TX FIFO */ - if ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TDFE) ) + if ( !(scif_readw(uart, params->status_reg) & SCFSR_TDFE) ) return 0; =20 /* Check number of data bytes stored in TX FIFO */ cnt =3D scif_readw(uart, SCIF_SCFDR) >> 8; - ASSERT( cnt >=3D 0 && cnt <=3D SCIF_FIFO_MAX_SIZE ); + ASSERT( cnt >=3D 0 && cnt <=3D params->fifo_size ); =20 - return (SCIF_FIFO_MAX_SIZE - cnt); + return (params->fifo_size - cnt); } =20 static void scif_uart_putc(struct serial_port *port, char c) { struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; =20 - scif_writeb(uart, SCIF_SCFTDR, c); + scif_writeb(uart, params->tx_fifo_reg, c); /* Clear required TX flags */ - scif_writew(uart, SCIF_SCFSR, scif_readw(uart, SCIF_SCFSR) & - ~(SCFSR_TEND | SCFSR_TDFE)); + scif_writew(uart, params->status_reg, + scif_readw(uart, params->status_reg) & + ~(SCFSR_TEND | SCFSR_TDFE)); } =20 static int scif_uart_getc(struct serial_port *port, char *pc) { struct scif_uart *uart =3D port->uart; + const struct port_params *params =3D uart->params; =20 /* Check for available data bytes in RX FIFO */ - if ( !(scif_readw(uart, SCIF_SCFSR) & (SCFSR_RDF | SCFSR_DR)) ) + if ( !(scif_readw(uart, params->status_reg) & (SCFSR_RDF | SCFSR_DR)) ) return 0; =20 - *pc =3D scif_readb(uart, SCIF_SCFRDR); + *pc =3D scif_readb(uart, params->rx_fifo_reg); =20 /* dummy read */ - scif_readw(uart, SCIF_SCFSR); + scif_readw(uart, params->status_reg); /* Clear required RX flags */ - scif_writew(uart, SCIF_SCFSR, ~(SCFSR_RDF | SCFSR_DR)); + scif_writew(uart, params->status_reg, ~(SCFSR_RDF | SCFSR_DR)); =20 return 1; } @@ -229,9 +270,16 @@ static struct uart_driver __read_mostly scif_uart_driv= er =3D { .vuart_info =3D scif_vuart_info, }; =20 +static const struct dt_device_match scif_uart_dt_match[] __initconst =3D +{ + { .compatible =3D "renesas,scif", .data =3D (void *)SCIF_PORT }, + { /* sentinel */ }, +}; + static int __init scif_uart_init(struct dt_device_node *dev, const void *data) { + const struct dt_device_match *match; const char *config =3D data; struct scif_uart *uart; int res; @@ -265,10 +313,14 @@ static int __init scif_uart_init(struct dt_device_nod= e *dev, return -ENOMEM; } =20 + match =3D dt_match_node(scif_uart_dt_match, dev); + ASSERT( match ); + uart->params =3D &port_params[(enum port_types)match->data]; + uart->vuart.base_addr =3D addr; uart->vuart.size =3D size; - uart->vuart.data_off =3D SCIF_SCFTDR; - uart->vuart.status_off =3D SCIF_SCFSR; + uart->vuart.data_off =3D uart->params->tx_fifo_reg; + uart->vuart.status_off =3D uart->params->status_reg; uart->vuart.status =3D SCFSR_TDFE; =20 /* Register with generic serial driver */ @@ -279,12 +331,6 @@ static int __init scif_uart_init(struct dt_device_node= *dev, return 0; } =20 -static const struct dt_device_match scif_uart_dt_match[] __initconst =3D -{ - DT_MATCH_COMPATIBLE("renesas,scif"), - { /* sentinel */ }, -}; - DT_DEVICE_START(scif_uart, "SCIF UART", DEVICE_SERIAL) .dt_match =3D scif_uart_dt_match, .init =3D scif_uart_init, diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uar= t.h index 8137850..c343f2f 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -21,8 +21,6 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H =20 -#define SCIF_FIFO_MAX_SIZE 16 - /* Register offsets */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ @@ -57,8 +55,6 @@ #define SCFSR_RDF (1 << 1) /* Receive FIFO Data Full */ #define SCFSR_DR (1 << 0) /* Receive Data Ready */ =20 -#define SCIF_ERRORS (SCFSR_PER | SCFSR_FER | SCFSR_ER | SCFSR_BRK) - /* Line Status Register (SCLSR) */ #define SCLSR_TO (1 << 2) /* Timeout */ #define SCLSR_ORER (1 << 0) /* Overrun Error */ --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 3 20:58:26 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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[85.223.141.74]) by smtp.gmail.com with ESMTPSA id k21sm2659652ljb.3.2019.05.02.10.00.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 May 2019 10:00:32 -0700 (PDT) X-Inumbo-ID: cc8050da-6cfb-11e9-843c-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fVhiWDUpJkVyDHyxs5otEWi551gqM+tZ24ZpPo7GxZs=; b=Tw9ZUteZoiAJkFKhWWBiBQVPYCxWCug4ZNYmRDA7O4F2g1d5Y8Ipm5hpBDosc6KcMi s+Y5EVgSQT9gGtR9nMfFcetCmVm4QTvkitu2Bmiz+z6eL1ORl6T//ifYPBJ3jRaEnQsN Ier8cwV9zrOI7ZIh97fiFR3Ht9DSvmemKeRn84YJiwlYtJBVOtCIMpjW7nC+W6DGwdI4 zPd8uYft8ejex1hO60LxfKuwxZ1yqV7LjDGRFzXAqsCQmvRiPL5/DZLvh7lTR0AXHNbX pNxkKxstYO6itOeMeM0Ehhs4lD5ammby4Nvtxl/Ot41X/M/2ozEPVliOSRQMTRtoZvP/ c7UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fVhiWDUpJkVyDHyxs5otEWi551gqM+tZ24ZpPo7GxZs=; b=APFeBueentOQ+ku1SATg3L8IxRSrRq1P5ECKSzb8vhz058bhE7FtK3C5YubXnnLCj6 uqfjNVyqmxtgammr5bCE5uSXgUVp6mji2u46UWvhjJ5xO/H/A0HbRUlzYZOOl4Rgtsrj Q2RiaF42uHIPn/9ypnb9sFy1mFmM9WHRhIx9/beZj41k0e9XPPzq7xWuHzKS6DhxAmqW 03ZG75zBP1oJHde0CchEB8HRzsaEeo1m7xQw5lP86HcaInI/gnCDRjsAmT+LjrKhZGQD VkyMJGAGGbntR2jwSanCFonpDwnTHYgQhlTmn4PR/1Xm1OHb4laOWHtTPQleDRG8HhLG DBvw== X-Gm-Message-State: APjAAAVOr36ik15Fny7LaWqnNfHX3bq1yG1p3kkBYYbXrFMJT1JOTbFV LkloQsyJzJJwNRSBr3EdncxjV9jhFo4= X-Google-Smtp-Source: APXvYqwh3fUuiOYt7CXPkbIFOdXrtUsHymVTAUKVf16uoGQshxdwjEd6fRdYtxU1CmmNXCs0V4MwNA== X-Received: by 2002:a2e:5b5c:: with SMTP id p89mr2449823ljb.177.1556816432782; Thu, 02 May 2019 10:00:32 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Thu, 2 May 2019 20:00:20 +0300 Message-Id: <1556816422-25185-3-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> References: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V5 2/4] xen/arm: drivers: scif: Add support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko For the driver to be able to handle SCIFA interface as well, this patch just adds the following: - SCIFA related macros - New element in "port_params" array to keep SCIFA specific things - SCIFA compatible string This patch makes possible to use existing driver for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). Signed-off-by: Oleksandr Tyshchenko Acked-by: Julien Grall --- Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only adds SCIFA support Changes in v4: - Remove overrun_bit (SCASSR_ORER) from error_mask Changes in v5: - Add Julien's A-b --- xen/drivers/char/scif-uart.c | 17 ++++++++++++++++- xen/include/asm-arm/scif-uart.h | 40 +++++++++++++++++++++++++++++++++++++= +-- 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 85483ee..fa0b827 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -1,7 +1,7 @@ /* * xen/drivers/char/scif-uart.c * - * Driver for SCIF (Serial communication interface with FIFO) + * Driver for SCIF(A) (Serial communication interface with FIFO (A)) * compatible UART. * * Oleksandr Tyshchenko @@ -46,6 +46,7 @@ static struct scif_uart { enum port_types { SCIF_PORT, + SCIFA_PORT, NR_PORTS, }; =20 @@ -74,6 +75,19 @@ static const struct port_params port_params[NR_PORTS] = =3D .irq_flags =3D SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, .fifo_size =3D 16, }, + + [SCIFA_PORT] =3D + { + .status_reg =3D SCIFA_SCASSR, + .tx_fifo_reg =3D SCIFA_SCAFTDR, + .rx_fifo_reg =3D SCIFA_SCAFRDR, + .overrun_reg =3D SCIFA_SCASSR, + .overrun_mask =3D SCASSR_ORER, + .error_mask =3D SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER, + .irq_flags =3D SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_E= RIE | + SCASCR_BRIE, + .fifo_size =3D 64, + }, }; =20 static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs = *regs) @@ -273,6 +287,7 @@ static struct uart_driver __read_mostly scif_uart_drive= r =3D { static const struct dt_device_match scif_uart_dt_match[] __initconst =3D { { .compatible =3D "renesas,scif", .data =3D (void *)SCIF_PORT }, + { .compatible =3D "renesas,scifa", .data =3D (void *)SCIFA_PORT }, { /* sentinel */ }, }; =20 diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uar= t.h index c343f2f..bce3404 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -2,7 +2,7 @@ * xen/include/asm-arm/scif-uart.h * * Common constant definition between early printk and the UART driver - * for the SCIF compatible UART. + * for the SCIF(A) compatible UART. * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -21,7 +21,7 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H =20 -/* Register offsets */ +/* Register offsets (SCIF) */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ #define SCIF_SCSCR (0x08) /* Serial control register */ @@ -79,6 +79,42 @@ #define SCFCR_TTRG10 (SCFCR_TTRG1) #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) =20 +/* Register offsets (SCIFA) */ +#define SCIFA_SCASMR (0x00) /* Serial mode register */ +#define SCIFA_SCABRR (0x04) /* Bit rate register */ +#define SCIFA_SCASCR (0x08) /* Serial control register */ +#define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ +#define SCIFA_SCAFER (0x10) /* FIFO error count register */ +#define SCIFA_SCASSR (0x14) /* Serial status register */ +#define SCIFA_SCAFCR (0x18) /* FIFO control register */ +#define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ +#define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ +#define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ +#define SCIFA_SCAPCR (0x30) /* Serial port control register */ +#define SCIFA_SCAPDR (0x34) /* Serial port data register */ + +/* Serial Control Register (SCASCR) */ +#define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ +#define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ +#define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enabl= e */ +#define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ +#define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ +#define SCASCR_TE (1 << 5) /* Transmit Enable */ +#define SCASCR_RE (1 << 4) /* Receive Enable */ +#define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ + +/* Serial Status Register (SCASSR) */ +#define SCASSR_ORER (1 << 9) /* Overrun Error */ +#define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ +#define SCASSR_ER (1 << 7) /* Receive Error */ +#define SCASSR_TEND (1 << 6) /* Transmission End */ +#define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ +#define SCASSR_BRK (1 << 4) /* Break Detect */ +#define SCASSR_FER (1 << 3) /* Framing Error */ +#define SCASSR_PER (1 << 2) /* Parity Error */ +#define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ +#define SCASSR_DR (1 << 0) /* Receive Data Ready */ + #endif /* __ASM_ARM_SCIF_UART_H */ =20 /* --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 3 20:58:26 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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[85.223.141.74]) by smtp.gmail.com with ESMTPSA id k21sm2659652ljb.3.2019.05.02.10.00.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 May 2019 10:00:33 -0700 (PDT) X-Inumbo-ID: cd1dd1c2-6cfb-11e9-843c-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BUeJ4Nqs+OAGSA0yR8DXF/JEAPhi1bA5d5M1uVIU/18=; b=Yy17sJEbmxpCh6ZNPi0wMu1CFiTwyPjTVLdh2qGx0Kn0L3WWN/phTI+VRlfoffgB28 9gmfvMRIL+yHgHM8W07OJNQyMm/wu2cLTOr9ayGRb9tCRW4TEN2KbYLqZL+GjpzGJ/S5 QjlvAZXw2m+pizDWI5NoKXI7pr3nCOsabi0oSO+PZvnXyra6as8nOOmtw0sSSsoaOkn7 ZMtBTgp7ZfWgPvIKc6loY3yspnYwfgMfAYuPRGcL7J/DIqj871V5M4CYFlb19h2LcGb8 ezO8K4aCul/Wv1zq0lxOIFFNFes2rmqS4nkhCAfl2BOGl6JfqtEjNANbXypN3RQCBppt 4ZRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BUeJ4Nqs+OAGSA0yR8DXF/JEAPhi1bA5d5M1uVIU/18=; b=Rd7Z4VS5FkKrDe7iAvloCxVbiBEjH5jTSun2kh0IIlvvUWQB5i1wiKmT0mj8RJxFkx U9nKt3tWpzthJuHFBs4DIsoz6+nNbna+7YjXw02N6o8Pub7R6c0EbaGTFQVixJXq/sGC 2ZuHEGqqUaRIhz9gC1Fj93fAYd5VfQVxY6RBebDmV9t10p/+XYiPAAvWNb8SP4ltcuHP A5ghVctcIDhNC6DBZfI4OxzBz/eUWTnZk/gSSy8eGLGdUCnS4i/K8IDt7vzuZMEI0Z5V UPiD65GMiP0ObV58Hu87NQmBF2hyprF5ruNPj7wP/bXH062fA+neYme2epYj6uhdt84j Nq8w== X-Gm-Message-State: APjAAAVXac+BsCybe44ehl6VlmdojLSJM2GhGV3GO0h/HORXqCOY28NT /BaECe8FuHDSnTnhxXX/x62CT3SxtcM= X-Google-Smtp-Source: APXvYqxEKeCnfExweq06DNDXPrsdAwjgeIPHshlRd5YxxG1NxqhzEqPKTG1QLYIvVCzEytqzyVJixg== X-Received: by 2002:a2e:988e:: with SMTP id b14mr2495104ljj.126.1556816433836; Thu, 02 May 2019 10:00:33 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Thu, 2 May 2019 20:00:21 +0300 Message-Id: <1556816422-25185-4-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> References: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V5 3/4] xen/arm: Extend SCIF early prink code to handle other interfaces X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko Extend early prink code to be able to handle other SCIF(X) compatible interfaces as well. These interfaces have lot in common, but mostly differ in offsets and bits for some registers. Introduce "EARLY_PRINTK_VERSION" config option to choose which interface version should be used (to properly apply register offsets). Please note, nothing has been technically changed for Renesas "Lager" and other supported boards (SCIF). The "EARLY_PRINTK_VERSION" option for that board should be empty: CONFIG_EARLY_PRINTK=3Dscif,0xe6e60000 Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v3: - It was decided not to introduce new debug-scifa.inc for handling SCIFA interface, but to extend existing debug-scif.inc for handling both interfaces. This patch is a result of splitting an initial patch "xen/arm: Add SCIFA UART support for early printk" and only reworks a code Changes in v4: - Update docs/misc/arm/early-printk.txt with the new option Changes in v5: - Cosmetic fixes (text and comments in code) --- docs/misc/arm/early-printk.txt | 5 +++++ xen/arch/arm/Rules.mk | 7 +++++++ xen/arch/arm/arm32/debug-scif.inc | 17 +++++++++++------ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index b23c54f..89e081e 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -27,6 +27,11 @@ CONFIG_EARLY_PRINTK=3D,, If is not given then the code will not try to initialize the UART, so that bootloader or firmware settings can be used for maximum compatibility. + - scif,, + - SCIF is, optionally, the interface version of the UART. + + If is not given then the default interface version (SCIF) + will be used. - For all other uarts there are no additional options. =20 As a convenience it is also possible to select from a list of diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index f264592..3d9a0ed 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -68,6 +68,13 @@ EARLY_PRINTK_INIT_UART :=3D y EARLY_PRINTK_BAUD :=3D $(word 3,$(EARLY_PRINTK_CFG)) endif endif +ifeq ($(EARLY_PRINTK_INC),scif) +ifneq ($(word 3,$(EARLY_PRINTK_CFG)),) +CFLAGS-y +=3D -DEARLY_PRINTK_VERSION_$(word 3,$(EARLY_PRINTK_CFG)) +else +CFLAGS-y +=3D -DEARLY_PRINTK_VERSION_NONE +endif +endif =20 ifneq ($(EARLY_PRINTK_INC),) EARLY_PRINTK :=3D y diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-s= cif.inc index 143f05d..6f60e01 100644 --- a/xen/arch/arm/arm32/debug-scif.inc +++ b/xen/arch/arm/arm32/debug-scif.inc @@ -19,28 +19,33 @@ =20 #include =20 +#ifdef EARLY_PRINTK_VERSION_NONE +#define STATUS_REG SCIF_SCFSR +#define TX_FIFO_REG SCIF_SCFTDR +#endif + /* - * SCIF UART wait UART to be ready to transmit + * Wait UART to be ready to transmit * rb: register which contains the UART base address * rc: scratch register */ .macro early_uart_ready rb rc 1: - ldrh \rc, [\rb, #SCIF_SCFSR] /* <- SCFSR (status register) */ + ldrh \rc, [\rb, #STATUS_REG] /* Read status register */ tst \rc, #SCFSR_TDFE /* Check TDFE bit */ beq 1b /* Wait for the UART to be ready = */ .endm =20 /* - * SCIF UART transmit character + * UART transmit character * rb: register which contains the UART base address * rt: register which contains the character to transmit */ .macro early_uart_transmit rb rt - strb \rt, [\rb, #SCIF_SCFTDR] /* -> SCFTDR (dat= a register) */ - ldrh \rt, [\rb, #SCIF_SCFSR] /* <- SCFSR (stat= us register) */ + strb \rt, [\rb, #TX_FIFO_REG] /* Write data reg= ister */ + ldrh \rt, [\rb, #STATUS_REG] /* Read status re= gister */ and \rt, \rt, #(~(SCFSR_TEND | SCFSR_TDFE)) /* Clear TEND and= TDFE bits */ - strh \rt, [\rb, #SCIF_SCFSR] /* -> SCFSR (stat= us register) */ + strh \rt, [\rb, #STATUS_REG] /* Write status r= egister */ .endm =20 /* --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 3 20:58:26 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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[85.223.141.74]) by smtp.gmail.com with ESMTPSA id k21sm2659652ljb.3.2019.05.02.10.00.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 May 2019 10:00:34 -0700 (PDT) X-Inumbo-ID: cdbdba25-6cfb-11e9-843c-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q6GomBEQElMWf1Og+4zLHwzVXgNb3k6k7PmdnX3q3Vs=; b=APJs+rwTRmAy/uShLJ10RqnbiQ8vf/ls9nIf+lO6FgdRa7XdSCusZFiupm00GxzGZ8 YrC0O/8Jfm9FeNCVU/xXre0Ph3dwJaFYuf/Hcd3Qu/ImhMkBQ+I8p2a9uzJ1DobX2Yt1 9gepUuY9Qu3Z1AEwFIlIIfrxOwzYG/ZZMqcpcfLiRlIlDwRsK9qy9cqm4iW8zVZ2vI0e MpVmY+Lf2BsKR35HurR/HW5JIfjY+ozsctg+21022W7ONoG2ZB+hYikYKVteC5Gcm074 DDrDFhTWnxLmp8T+Jiz9GV96n3i/0/gj+w0k6Aq2S4DgzOj2fNAtEcWenWaNXmqnUC3v XC4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q6GomBEQElMWf1Og+4zLHwzVXgNb3k6k7PmdnX3q3Vs=; b=aZNAix3B8CGva4mF2c1mpWvBD/oid+4mUa1KM9zHPz8I48da8QfnL+tBlnLyY0Sa9W cekz6pBnw3jhlc+SzmG7YG3020brci4Dw6+OwE9y/9bmERvheqUwz/SWKuF0k7a3aTwI IWNWu/w2RNf7zqb7/KGtlX+v1pG89mY4pqfHPYQiZU1yc07QhnZQbE7SJUjivf92MvWP IiRk8p7etI/2CJ9sBRUPZ6ajOreq764reJBWzDYIhmyWWlZiFIBOzTUe8HWbdHe9rzW2 KkcHSSkXJTLEHnTwBNOQRjcHDXfyncMFULJJ12cpVsJlgEgAMS4YKWc2/hoiSGZX6scG lXtA== X-Gm-Message-State: APjAAAV7CWxzhHWzoLotvYv1PP0qLSc666Fb2bUzrUG7iCAru9WdlBfS J7ZRkc6ILm0yla3tkG05/2LrKT3XL+Y= X-Google-Smtp-Source: APXvYqy1WbgcZIzZMT9N9BIuc09OJjwOSVdhD0wjUxqaNcu1RCYbyxB5zQNsI7JNKBprEDuSmjLHQg== X-Received: by 2002:a19:7402:: with SMTP id v2mr2580582lfe.53.1556816434890; Thu, 02 May 2019 10:00:34 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Thu, 2 May 2019 20:00:22 +0300 Message-Id: <1556816422-25185-5-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> References: <1556816422-25185-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V5 4/4] xen/arm: Add early printk support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko This patch makes possible to use existing early prink code for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). The "EARLY_PRINTK_VERSION" for that board should be 'A': CONFIG_EARLY_PRINTK=3Dscif,0xe6c40000,A Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall Acked-by: Julien Grall --- Changes in v3: - It was decided not to introduce new debug-scifa.inc for handling SCIFA interface, but to extend existing debug-scif.inc for handling both interfaces. This patch is a result of splitting an initial patch "xen/arm: Add SCIFA UART support for early printk" and only adds a support. Changes in v4: - Drop SCIF(A) from comments Changes in v5: - Cosmetic fixes (comments in code) --- xen/arch/arm/arm32/debug-scif.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-s= cif.inc index 6f60e01..3f01c90 100644 --- a/xen/arch/arm/arm32/debug-scif.inc +++ b/xen/arch/arm/arm32/debug-scif.inc @@ -1,7 +1,7 @@ /* * xen/arch/arm/arm32/debug-scif.inc * - * SCIF specific debug code + * SCIF(A) specific debug code * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -22,6 +22,9 @@ #ifdef EARLY_PRINTK_VERSION_NONE #define STATUS_REG SCIF_SCFSR #define TX_FIFO_REG SCIF_SCFTDR +#elif EARLY_PRINTK_VERSION_A +#define STATUS_REG SCIFA_SCASSR +#define TX_FIFO_REG SCIFA_SCAFTDR #endif =20 /* --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel