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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id u8sm950273lfi.83.2019.04.17.07.59.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 Apr 2019 07:59:51 -0700 (PDT) X-Inumbo-ID: 74d0db0a-6121-11e9-92d7-bc764e045a96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GGW6lz0d+TJYKyfVW8KXFaIPKaSqBVU7ZqzfmEp2d8s=; b=Uxtd2kjBFoWpkIrslNTeFf2cR9PkLss+EYPngOFzH3oBE/Fp+JBdmn+WsnAaKGVBkW R92KaYyNbYL/DMl9y+vdiySru/hp/6RI5g1UM2dQkFLHeQq3GUblWH04XQoZ//LNLq65 FNCQAhVgZT6h4Mc+lclvIqCjcllzXV8pBlyItIUm8WRQBD36n6d/ZBWdhJ+5HudbQIM7 Vhj+kuUEI7mTAnMe/yJyVa0TWzyNsrqF/YLk7OFlFdvDHqJCx2q/JgYJdrAcfl0Cqx8Q 6P/6odQhSlQdgFCzYSSXcaGJsc7T1HI5MPcalMoUe3sN7NLVwhveUs9PQDvTmdWgv5Qd WlHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GGW6lz0d+TJYKyfVW8KXFaIPKaSqBVU7ZqzfmEp2d8s=; b=L3X0fHClaxq9UAEEfYvoAnKf2Mg+D8Y+k/780T06UxvEli0hD08tV7g+/vbbGh1X7o pAo8a9SQEB2S/YqxWsbN38eG+P9nR9Q9dw6J8rLx7i79Rry8PnR2KLGbrXv+NpaCGwu5 JPWtnuC0PaGpv9Blub9m6tjPn1dph779pkszweSZV02ZlngC+pXM4pipTblpXVx3JwFo nS3WBUh0lksO3EowEhu+3ljNUR0nvhDGr2u3KYvWfcWn+gWfdmgC25CNd6s2tcA00sgy WAKQGefWDyfb9yEF+/C9gyfIee2Di5OD7odbAOj0EcHk0CCu63D45jL4a0UA99pn4XJ1 3Uyw== X-Gm-Message-State: APjAAAVhEh5oNGoNtkc8oh9Vvi56zPULLiH6Ec/g4YFJ7dohPdGkciWN MxDsbdW2u9ZKKqmgJEMic0g+JxNOLgA= X-Google-Smtp-Source: APXvYqycQ9X6K3e738J9sTvLxwzM8jb2vB/4UNA9l+LIv6zuq0lA6eTlJdNV+7obuljYX+UR9mSHzg== X-Received: by 2002:a19:ed04:: with SMTP id y4mr102162lfy.165.1555513192452; Wed, 17 Apr 2019 07:59:52 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Wed, 17 Apr 2019 17:59:33 +0300 Message-Id: <1555513175-7596-4-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555513175-7596-1-git-send-email-olekstysh@gmail.com> References: <1555513175-7596-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V4 3/5] xen/arm: drivers: scif: Add support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Oleksandr Tyshchenko For the driver to be able to handle SCIFA interface as well, this patch just adds the following: - SCIFA related macros - New element in "port_params" array to keep SCIFA specific things - SCIFA compatible string This patch makes possible to use existing driver for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall Acked-by: Julien Grall --- Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only adds SCIFA support Changes in v4: - Remove overrun_bit (SCASSR_ORER) from error_mask --- xen/drivers/char/scif-uart.c | 17 ++++++++++++++++- xen/include/asm-arm/scif-uart.h | 40 +++++++++++++++++++++++++++++++++++++= +-- 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 85483ee..fa0b827 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -1,7 +1,7 @@ /* * xen/drivers/char/scif-uart.c * - * Driver for SCIF (Serial communication interface with FIFO) + * Driver for SCIF(A) (Serial communication interface with FIFO (A)) * compatible UART. * * Oleksandr Tyshchenko @@ -46,6 +46,7 @@ static struct scif_uart { enum port_types { SCIF_PORT, + SCIFA_PORT, NR_PORTS, }; =20 @@ -74,6 +75,19 @@ static const struct port_params port_params[NR_PORTS] = =3D .irq_flags =3D SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, .fifo_size =3D 16, }, + + [SCIFA_PORT] =3D + { + .status_reg =3D SCIFA_SCASSR, + .tx_fifo_reg =3D SCIFA_SCAFTDR, + .rx_fifo_reg =3D SCIFA_SCAFRDR, + .overrun_reg =3D SCIFA_SCASSR, + .overrun_mask =3D SCASSR_ORER, + .error_mask =3D SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER, + .irq_flags =3D SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_E= RIE | + SCASCR_BRIE, + .fifo_size =3D 64, + }, }; =20 static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs = *regs) @@ -273,6 +287,7 @@ static struct uart_driver __read_mostly scif_uart_drive= r =3D { static const struct dt_device_match scif_uart_dt_match[] __initconst =3D { { .compatible =3D "renesas,scif", .data =3D (void *)SCIF_PORT }, + { .compatible =3D "renesas,scifa", .data =3D (void *)SCIFA_PORT }, { /* sentinel */ }, }; =20 diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uar= t.h index c343f2f..bce3404 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -2,7 +2,7 @@ * xen/include/asm-arm/scif-uart.h * * Common constant definition between early printk and the UART driver - * for the SCIF compatible UART. + * for the SCIF(A) compatible UART. * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -21,7 +21,7 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H =20 -/* Register offsets */ +/* Register offsets (SCIF) */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ #define SCIF_SCSCR (0x08) /* Serial control register */ @@ -79,6 +79,42 @@ #define SCFCR_TTRG10 (SCFCR_TTRG1) #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) =20 +/* Register offsets (SCIFA) */ +#define SCIFA_SCASMR (0x00) /* Serial mode register */ +#define SCIFA_SCABRR (0x04) /* Bit rate register */ +#define SCIFA_SCASCR (0x08) /* Serial control register */ +#define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ +#define SCIFA_SCAFER (0x10) /* FIFO error count register */ +#define SCIFA_SCASSR (0x14) /* Serial status register */ +#define SCIFA_SCAFCR (0x18) /* FIFO control register */ +#define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ +#define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ +#define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ +#define SCIFA_SCAPCR (0x30) /* Serial port control register */ +#define SCIFA_SCAPDR (0x34) /* Serial port data register */ + +/* Serial Control Register (SCASCR) */ +#define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ +#define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ +#define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enabl= e */ +#define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ +#define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ +#define SCASCR_TE (1 << 5) /* Transmit Enable */ +#define SCASCR_RE (1 << 4) /* Receive Enable */ +#define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ + +/* Serial Status Register (SCASSR) */ +#define SCASSR_ORER (1 << 9) /* Overrun Error */ +#define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ +#define SCASSR_ER (1 << 7) /* Receive Error */ +#define SCASSR_TEND (1 << 6) /* Transmission End */ +#define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ +#define SCASSR_BRK (1 << 4) /* Break Detect */ +#define SCASSR_FER (1 << 3) /* Framing Error */ +#define SCASSR_PER (1 << 2) /* Parity Error */ +#define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ +#define SCASSR_DR (1 << 0) /* Receive Data Ready */ + #endif /* __ASM_ARM_SCIF_UART_H */ =20 /* --=20 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel