From nobody Fri Mar 29 12:52:40 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1555172697; cv=none; d=zoho.com; s=zohoarc; b=HkIZvXtEktl8OQFXjyI6aIw+ZNIx9i9e11+bG2GVqJqZyOA4Xil5q4HhxgxaEmg4oyfeiIb2Vc3dH2eVY2hZGtDQT2bkweo+BAqYFf+Xeil9uUwUz1WcSYD0FgsqwGNmm8jm5dr2ZjzKo4WEn9StXKqy+qIDOyZDRPX7//tNbQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1555172697; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wJ1LZyq/nicWJ+WmT2Ao2yZG/1Ni9BRqhKepkfeWLP4=; b=SwTaI4WoM5xkAxXh1dGeFd4jxHi6tIJhufdaVtzWqnV8XHM+lwU1Ki4fBtwXn2FIMpwbBLZyxedXc1ypZqkSib6F35sxaqSBrlpcSu02TABGV7a5wvQ0Rnzcr0SN3TTPXtMMtCHz3LPw0/WE9I0Kve74Tfid+z1XIdv9wlUdkR8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1555172697282773.8888370211043; Sat, 13 Apr 2019 09:24:57 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hFLRK-0005FV-Up; Sat, 13 Apr 2019 16:23:38 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hFLRJ-0005FH-MX for xen-devel@lists.xenproject.org; Sat, 13 Apr 2019 16:23:37 +0000 Received: from SMTP03.CITRIX.COM (unknown [162.221.156.55]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 7d460082-5e08-11e9-92d7-bc764e045a96; Sat, 13 Apr 2019 16:23:36 +0000 (UTC) X-Inumbo-ID: 7d460082-5e08-11e9-92d7-bc764e045a96 X-IronPort-AV: E=Sophos;i="5.60,345,1549929600"; d="scan'208";a="83508410" From: Andrew Cooper To: Xen-devel Date: Sat, 13 Apr 2019 17:22:10 +0100 Message-ID: <1555172532-23814-2-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> References: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/3] x86/spec-ctrl: Reposition the XPTI command line parsing logic X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" It has ended up in the middle of the mitigation calculation logic. Move it= to be beside the other command line parsing. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/spec_ctrl.c | 134 +++++++++++++++++++++++--------------------= ---- 1 file changed, 67 insertions(+), 67 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 4fd09f8..88b56f9 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -173,6 +173,73 @@ static int __init parse_spec_ctrl(const char *s) } custom_param("spec-ctrl", parse_spec_ctrl); =20 +int8_t __read_mostly opt_xpti_hwdom =3D -1; +int8_t __read_mostly opt_xpti_domu =3D -1; + +static __init void xpti_init_default(uint64_t caps) +{ + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + caps =3D ARCH_CAPS_RDCL_NO; + + if ( caps & ARCH_CAPS_RDCL_NO ) + { + if ( opt_xpti_hwdom < 0 ) + opt_xpti_hwdom =3D 0; + if ( opt_xpti_domu < 0 ) + opt_xpti_domu =3D 0; + } + else + { + if ( opt_xpti_hwdom < 0 ) + opt_xpti_hwdom =3D 1; + if ( opt_xpti_domu < 0 ) + opt_xpti_domu =3D 1; + } +} + +static __init int parse_xpti(const char *s) +{ + const char *ss; + int val, rc =3D 0; + + /* Interpret 'xpti' alone in its positive boolean form. */ + if ( *s =3D=3D '\0' ) + opt_xpti_hwdom =3D opt_xpti_domu =3D 1; + + do { + ss =3D strchr(s, ','); + if ( !ss ) + ss =3D strchr(s, '\0'); + + switch ( parse_bool(s, ss) ) + { + case 0: + opt_xpti_hwdom =3D opt_xpti_domu =3D 0; + break; + + case 1: + opt_xpti_hwdom =3D opt_xpti_domu =3D 1; + break; + + default: + if ( !strcmp(s, "default") ) + opt_xpti_hwdom =3D opt_xpti_domu =3D -1; + else if ( (val =3D parse_boolean("dom0", s, ss)) >=3D 0 ) + opt_xpti_hwdom =3D val; + else if ( (val =3D parse_boolean("domu", s, ss)) >=3D 0 ) + opt_xpti_domu =3D val; + else if ( *s ) + rc =3D -EINVAL; + break; + } + + s =3D ss + 1; + } while ( *ss ); + + return rc; +} +custom_param("xpti", parse_xpti); + int8_t __read_mostly opt_pv_l1tf_hwdom =3D -1; int8_t __read_mostly opt_pv_l1tf_domu =3D -1; =20 @@ -634,73 +701,6 @@ static __init void l1tf_calculations(uint64_t caps) : (3ul << (paddr_bits - 2)))); } =20 -int8_t __read_mostly opt_xpti_hwdom =3D -1; -int8_t __read_mostly opt_xpti_domu =3D -1; - -static __init void xpti_init_default(uint64_t caps) -{ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) - caps =3D ARCH_CAPS_RDCL_NO; - - if ( caps & ARCH_CAPS_RDCL_NO ) - { - if ( opt_xpti_hwdom < 0 ) - opt_xpti_hwdom =3D 0; - if ( opt_xpti_domu < 0 ) - opt_xpti_domu =3D 0; - } - else - { - if ( opt_xpti_hwdom < 0 ) - opt_xpti_hwdom =3D 1; - if ( opt_xpti_domu < 0 ) - opt_xpti_domu =3D 1; - } -} - -static __init int parse_xpti(const char *s) -{ - const char *ss; - int val, rc =3D 0; - - /* Interpret 'xpti' alone in its positive boolean form. */ - if ( *s =3D=3D '\0' ) - opt_xpti_hwdom =3D opt_xpti_domu =3D 1; - - do { - ss =3D strchr(s, ','); - if ( !ss ) - ss =3D strchr(s, '\0'); - - switch ( parse_bool(s, ss) ) - { - case 0: - opt_xpti_hwdom =3D opt_xpti_domu =3D 0; - break; - - case 1: - opt_xpti_hwdom =3D opt_xpti_domu =3D 1; - break; - - default: - if ( !strcmp(s, "default") ) - opt_xpti_hwdom =3D opt_xpti_domu =3D -1; - else if ( (val =3D parse_boolean("dom0", s, ss)) >=3D 0 ) - opt_xpti_hwdom =3D val; - else if ( (val =3D parse_boolean("domu", s, ss)) >=3D 0 ) - opt_xpti_domu =3D val; - else if ( *s ) - rc =3D -EINVAL; - break; - } - - s =3D ss + 1; - } while ( *ss ); - - return rc; -} -custom_param("xpti", parse_xpti); - void __init init_speculation_mitigations(void) { enum ind_thunk thunk =3D THUNK_DEFAULT; --=20 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri Mar 29 12:52:40 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; 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Sat, 13 Apr 2019 09:25:00 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hFLRK-0005FO-Mi; Sat, 13 Apr 2019 16:23:38 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hFLRJ-0005F8-Bk for xen-devel@lists.xenproject.org; Sat, 13 Apr 2019 16:23:37 +0000 Received: from SMTP03.CITRIX.COM (unknown [162.221.156.55]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 7cd49322-5e08-11e9-92d7-bc764e045a96; Sat, 13 Apr 2019 16:23:36 +0000 (UTC) X-Inumbo-ID: 7cd49322-5e08-11e9-92d7-bc764e045a96 X-IronPort-AV: E=Sophos;i="5.60,345,1549929600"; d="scan'208";a="83508406" From: Andrew Cooper To: Xen-devel Date: Sat, 13 Apr 2019 17:22:11 +0100 Message-ID: <1555172532-23814-3-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> References: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/3] x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This is a model specific register which details the current configuration cores and threads in the package. Because of how Hyperthread and Core configuration works works in firmware, the MSR it is de-facto constant and will remain unchanged until the next system reset. It is a read only MSR, and for now, reject guest attempts to read it, to av= oid the system setting leaking into guest context. Further CPUID/MSR work is required before we can start virtualising a consistent topology to the gues= t. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 Observant people will notice that in the latest SDM at the time of writing, version 069, this MSR is listed in single table for Haswell generation Xeon= 's, and that the thread and core count fields are the wrong way around. I'm informed that this MSR has existed since the Nehalem era (except for so= me of the early in-order Atoms), has had consistent behaviour in that time, and that the documentation will be addressed in future SDM revisions. --- xen/arch/x86/msr.c | 2 ++ xen/include/asm-x86/msr-index.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 815d599..948d07d 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -131,6 +131,7 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uin= t64_t *val) case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_INTEL_CORE_THREAD_COUNT: case MSR_TSX_FORCE_ABORT: /* Not offered to guests. */ goto gp_fault; @@ -267,6 +268,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) { uint64_t rsvd; =20 + case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* Read-only */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index 11512d4..389f95f 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -32,6 +32,10 @@ #define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \ EFER_SVME | EFER_FFXSE) =20 +#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 +#define MSR_CTC_THREAD_MASK 0x0000ffff +#define MSR_CTC_CORE_MASK 0xffff0000 + /* Speculation Controls. */ #define MSR_SPEC_CTRL 0x00000048 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) --=20 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri Mar 29 12:52:40 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; 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d="scan'208";a="83508409" From: Andrew Cooper To: Xen-devel Date: Sat, 13 Apr 2019 17:22:12 +0100 Message-ID: <1555172532-23814-4-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> References: <1555172532-23814-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 3/3] x86/boot: Detect the firmware SMT setting correctly on Intel hardware X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" While boot_cpu_data.x86_num_siblings is an accurate value to use on AMD hardware, it isn't on Intel when the user has disabled Hyperthreading in the firmware. As a result, a user which has chosen to disable HT still gets nagged on L1TF-vulnerable hardware when they haven't chosen an explicit smt=3D setting. Make use of the largely-undocumented MSR_INTEL_CORE_THREAD_COUNT which in practice exists since Nehalem, when booting on real hardware. Fall back to using the ACPI table APIC IDs. While adjusting this logic, fix a latent bug in amd_get_topology(). The thread count field in CPUID.0x8000001e.ebx is documented as 8 bits wide, rather than 2 bits wide. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/amd.c | 2 +- xen/arch/x86/spec_ctrl.c | 50 ++++++++++++++++++++++++++++++++++++++++++++= +--- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index e19a5ea..23de258 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -507,7 +507,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c) u32 eax, ebx, ecx, edx; =20 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - c->x86_num_siblings =3D ((ebx >> 8) & 0x3) + 1; + c->x86_num_siblings =3D ((ebx >> 8) & 0xff) + 1; =20 if (c->x86 < 0x17) c->compute_unit_id =3D ebx & 0xFF; diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 88b56f9..be7f896 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -58,7 +58,7 @@ uint8_t __read_mostly default_xen_spec_ctrl; uint8_t __read_mostly default_spec_ctrl_flags; =20 paddr_t __read_mostly l1tf_addr_mask, __read_mostly l1tf_safe_maddr; -static bool __initdata cpu_has_bug_l1tf; +static bool __initdata cpu_has_bug_l1tf, hw_smt_enabled; static unsigned int __initdata l1d_maxphysaddr; =20 static int __init parse_spec_ctrl(const char *s) @@ -284,6 +284,49 @@ static __init int parse_pv_l1tf(const char *s) } custom_param("pv-l1tf", parse_pv_l1tf); =20 +static void __init detect_smt_status(void) +{ + uint64_t val; + unsigned int cpu; + + /* + * x86_num_siblings defaults to 1 in the absence of other information,= and + * is adjusted based on other topology information found in CPUID leav= es. + * + * On AMD hardware, it will be the current SMT configuration. On Intel + * hardware, it will represent the maximum capability, rather than the + * current configuration. + */ + if ( boot_cpu_data.x86_num_siblings < 2 ) + return; + + /* + * Intel Nehalem and later hardware does have an MSR which reports the + * current count of cores/threads in the package. + * + * At the time of writing, it is almost completely undocumented, so is= n't + * virtualised reliably. + */ + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && !cpu_has_hype= rvisor && + !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, val) ) + { + hw_smt_enabled =3D (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D + MASK_EXTR(val, MSR_CTC_THREAD_MASK)); + return; + } + + /* + * Search over the CPUs reported in the ACPI tables. Any whose APIC ID + * has a non-zero thread id component indicates that SMT is active. + */ + for_each_present_cpu ( cpu ) + if ( x86_cpu_to_apicid[cpu] & (boot_cpu_data.x86_num_siblings - 1)= ) + { + hw_smt_enabled =3D true; + return; + } +} + static void __init print_details(enum ind_thunk thunk, uint64_t caps) { unsigned int _7d0 =3D 0, e8b =3D 0, tmp; @@ -710,6 +753,8 @@ void __init init_speculation_mitigations(void) if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 + detect_smt_status(); + /* * Has the user specified any custom BTI mitigations? If so, follow t= heir * instructions exactly and disable all heuristics. @@ -886,8 +931,7 @@ void __init init_speculation_mitigations(void) * However, if we are on affected hardware, with HT enabled, and the u= ser * hasn't explicitly chosen whether to use HT or not, nag them to do s= o. */ - if ( opt_smt =3D=3D -1 && cpu_has_bug_l1tf && !pv_shim && - boot_cpu_data.x86_num_siblings > 1 ) + if ( opt_smt =3D=3D -1 && cpu_has_bug_l1tf && !pv_shim && hw_smt_enabl= ed ) warning_add( "Booted on L1TF-vulnerable hardware with SMT/Hyperthreading\n" "enabled. Please assess your configuration and choose an\n" --=20 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel