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[109.243.64.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018556bsm929934566b.156.2025.04.08.08.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 08:57:31 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2e9ceea1-1492-11f0-9eaa-5ba50f476ded DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744127852; x=1744732652; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IiCk6l0j5WiAsBCvt03FXOQepiOD85wA7EDe/CpLmKg=; b=gQU13qDOttBKEnlHvx+1Mfx58cnepl9OuiFpJiNcmb6bGTh3Hdm3G/LRP0XeelWG6o zAUfkSa6kLyRR4bMtU1znQHijvLxOFpWt6RMLXCMtF5uqLw5cvuu3GVkrmmDAmUN2+Tc +9zcdcOuR0RW/Z5S1uedvSnpfI/QnfcFqmQaVywVYXwT6Qs6IgryZpShD/JRbwsyJY0R Zmxc5vvymMrX8+jAmhWkw1uQGlmt8rNNdCCW2E9fhYwo+Ybp8iPx0uvFeZqJI0+7aHi9 4nCFhm4kkYitu2gKFeRciwxOhXIB71/THbZBF+X0yX81zJ3RD3gRoNMn7EJuvzFO90Xv I06Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744127852; x=1744732652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IiCk6l0j5WiAsBCvt03FXOQepiOD85wA7EDe/CpLmKg=; b=RpHm+z6N9zjnUHV0rIRmABQsv+4BH/RLjdqI9v7IvWb3qbVu5T7miPVmxe3NRK/eYR kTYQPiES8hwVC9deJq9IMvz2CQ3N2XihtpGRXQ31BdeUeFKM1rwdqvxTWsMRbuJH6wqs jgt2vIFHXd6W6klF9NFVre+p3xTtIGjcTkuztJ8ndC2/v30z5u4SdQnkxN/vnh8t4IRw Qz8rbJ5iNs5nwDHtKDnvAKhYCCUICfZJFwpaBi73+rdeW3Xzem8TPU9v8j1Togm4scp0 weonPHtWG3xBxBeDDsjsTzYUtDxNWHqwoirn1sG1kn18OQvIMzOvfQDZdFl8kIP7S9Oz YLEw== X-Gm-Message-State: AOJu0YysUJQMXUWec/RCJ3neOleig4983uHKyy0ilu0Wml7MX3NznQHj 91FPzutkKDPsZVwJsWtnlMcIm2fp92+AgiasRFKNvFpV0N/+zTv5LN0E0g== X-Gm-Gg: ASbGncsXavRx6U6zS8W0MvIXPSQ0BG9n+e6FI8dKkzE9uYkQUbaaRfjR/u05694ayBm 5o3Hwr/rj9AFUltwRfDRhaWk5wDFnTMHP6kSq/vLyBNbIQsQ/m4DsyN+IX2hS8EuaDjG1RDlDnh DDKEk1YjsotMHNUlMJoE8NL/VWSsZUzmceHoQvXPfYfnMaGkLXBMdAu+QUYQYOvw9/RszATkHS7 p84bntBV0JAqAhamAdQCdS0TToPY62Y0TTn56nnzEx/zRmgA4gQGxIuvbE/2baU9NDT4ZMKhr6+ fLhA7EfMgenI47b4GttQEUM3i2Pxw0BWRQHI3i178ZfrKDY60MmOTOIV9P8A8Ynr5jAoceG3uNh jzWFWVsiMv6SCzQ== X-Google-Smtp-Source: AGHT+IGgpSlMZNNIp0rd6Ulo0pZO/vslcVWFFOm8JSDbN+R8a0ns3rXs1/gaM3I5T7VDk++uygeImQ== X-Received: by 2002:a17:907:6d29:b0:ac1:f19a:c0a0 with SMTP id a640c23a62f3a-ac7d177475emr1383649066b.20.1744127851981; Tue, 08 Apr 2025 08:57:31 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v1 07/14] xen/riscv: Introduce intc_hw_operations abstraction Date: Tue, 8 Apr 2025 17:57:12 +0200 Message-ID: <139b37478b4ca7e2ec3a04b73f462197227f57fa.1744126720.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1744127882698019100 Content-Type: text/plain; charset="utf-8" Introduce the `intc_hw_operations` structure to encapsulate interrupt controller-specific data and operations. This structure includes: - A pointer to interrupt controller information (`intc_info`) - Callbacks to initialize the controller and set IRQ type/priority - A reference to an interupt controller descriptor (`host_irq_type`) Also introduce generic helper functions: - `intc_init()`: Initializes the interrupt controller - `register_intc_ops()`: Registers the `intc_hw_operations` implementation - `intc_route_irq_to_xen()`: Configures IRQ routing to Xen, setting handler, type, and priority Most of these functions act as thin wrappers around the corresponding callbacks in `intc_hw_operations`. This abstraction lays the groundwork for supporting multiple interrupt controller types (e.g., PLIC, APLIC) in extensible way. This patch is based on the changes from [1]. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7cfb4bd4748ca2= 68142497ac5c327d2766fb342d Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/intc.h | 23 ++++++++++++++ xen/arch/riscv/intc.c | 51 +++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 52ba196d87..0d498b10f4 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -17,6 +17,29 @@ struct intc_info { const struct dt_device_node *node; }; =20 +struct intc_hw_operations { + /* Hold intc hw information */ + const struct intc_info *info; + /* Initialize the intc and the boot CPU */ + int (*init)(void); + + /* hw_irq_controller to enable/disable/eoi host irq */ + hw_irq_controller *host_irq_type; + + /* Set IRQ type */ + void (*set_irq_type)(struct irq_desc *desc, unsigned int type); + /* Set IRQ priority */ + void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority); + +}; + void intc_preinit(void); =20 +void intc_init(void); + +void register_intc_ops(const struct intc_hw_operations *ops); + +struct irq_desc; +void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index 4061a3c457..8274897d8c 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -1,9 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 #include +#include #include #include +#include #include +#include + +#include + +static const struct intc_hw_operations *intc_hw_ops; + +void register_intc_ops(const struct intc_hw_operations *ops) +{ + intc_hw_ops =3D ops; +} =20 void __init intc_preinit(void) { @@ -12,3 +24,42 @@ void __init intc_preinit(void) else panic("ACPI interrupt controller preinit() isn't implemented\n"); } + +void __init intc_init(void) +{ + ASSERT(intc_hw_ops); + + if ( intc_hw_ops->init() ) + panic("Failed to initialize the interrupt controller drivers\n"); +} + +/* desc->irq needs to be disabled before calling this function */ +static void intc_set_irq_type(struct irq_desc *desc, unsigned int type) +{ + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(type !=3D IRQ_TYPE_INVALID); + ASSERT(intc_hw_ops && intc_hw_ops->set_irq_type); + + intc_hw_ops->set_irq_type(desc, type); +} + +static void intc_set_irq_priority(struct irq_desc *desc, unsigned int prio= rity) +{ + ASSERT(intc_hw_ops && intc_hw_ops->set_irq_priority); + + intc_hw_ops->set_irq_priority(desc, priority); +} + +void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) +{ + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); + ASSERT(spin_is_locked(&desc->lock)); + /* Can't route interrupts that don't exist */ + ASSERT(intc_hw_ops && desc->irq < intc_hw_ops->info->nr_irqs); + + desc->handler =3D intc_hw_ops->host_irq_type; + + intc_set_irq_type(desc, desc->arch.type); + intc_set_irq_priority(desc, priority); +} --=20 2.49.0