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charset="utf-8" Provide support for this insn, which is a prereq to FRED. CPUID-wise introduce both its and FRED's bit at this occasion, thus allowing to also express the dependency right away. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- Instead of ->read_segment() we could of course also use ->read_msr() to fetch the original GS base. I don't think I can see a clear advantage of either approach; the way it's done it matches how we handle SWAPGS. For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). --- v2: Use X86_EXC_*. Add comments. --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -235,6 +235,8 @@ int libxl_cpuid_parse_config(libxl_cpuid {"fzrm", 0x00000007, 1, CPUID_REG_EAX, 10, 1}, {"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1}, {"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1}, + {"fred", 0x00000007, 1, CPUID_REG_EAX, 17, 1}, + {"lkgs", 0x00000007, 1, CPUID_REG_EAX, 18, 1}, {"wrmsrns", 0x00000007, 1, CPUID_REG_EAX, 19, 1}, {"avx-ifma", 0x00000007, 1, CPUID_REG_EAX, 23, 1}, =20 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -190,7 +190,8 @@ static const char *const str_7a1[32] =3D [10] =3D "fzrm", [11] =3D "fsrs", [12] =3D "fsrcs", =20 - /* 18 */ [19] =3D "wrmsrns", + /* 16 */ [17] =3D "fred", + [18] =3D "lkgs", [19] =3D "wrmsrns", =20 /* 22 */ [23] =3D "avx-ifma", }; --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -666,6 +666,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt= ); } =20 +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -675,8 +679,30 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p =3D 1; + +#ifdef __x86_64__ + if ( seg =3D=3D x86_seg_gs ) + reg->base =3D gs_base; +#endif + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg =3D=3D x86_seg_gs ) + gs_base =3D reg->base; + return X86EMUL_OKAY; } +#endif =20 static int read_msr( unsigned int reg, @@ -689,6 +715,20 @@ static int read_msr( *val =3D ctxt->addr_size > 32 ? 0x500 /* LME|LMA */ : 0; return X86EMUL_OKAY; =20 +#ifdef __x86_64__ + case 0xc0000101: /* GS_BASE */ + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base; + return X86EMUL_OKAY; + + case 0xc0000102: /* SHADOW_GS_BASE */ + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base_shadow; + return X86EMUL_OKAY; +#endif + case 0xc0000103: /* TSC_AUX */ #define TSC_AUX_VALUE 0xCACACACA *val =3D TSC_AUX_VALUE; @@ -698,6 +738,31 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } =20 +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt) +{ + switch ( reg ) + { + case 0xc0000101: /* GS_BASE */ + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base =3D val; + return X86EMUL_OKAY; + + case 0xc0000102: /* SHADOW_GS_BASE */ + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow =3D val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 =20 @@ -1331,6 +1396,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment =3D write_segment; + emulops.write_msr =3D write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] =3D 0x0f; instr[1] =3D 0x01; instr[2] =3D 0xf8; + regs.eip =3D (unsigned long)&instr[0]; + gs_base =3D 0xffffeeeecccc8888UL; + gs_base_shadow =3D 0x0000111122224444UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[3]) || + (gs_base !=3D 0x0000111122224444UL) || + (gs_base_shadow !=3D 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x00; instr[3] =3D = 0x72; instr[4] =3D 0x02; + regs.eip =3D (unsigned long)&instr[0]; + regs.edx =3D (unsigned long)res; + res[0] =3D 0x00004444; + res[1] =3D 0x8888cccc; + i =3D cp.extd.nscb; cp.extd.nscb =3D true; /* for AMD */ + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (gs_base !=3D 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cp.extd.nscb =3D i; + emulops.write_segment =3D NULL; + emulops.write_msr =3D NULL; #endif printf("okay\n"); =20 --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -86,6 +86,7 @@ bool emul_test_init(void) cp.feat.adx =3D true; cp.feat.avx512pf =3D cp.feat.avx512f; cp.feat.rdpid =3D true; + cp.feat.lkgs =3D true; cp.feat.wrmsrns =3D true; cp.extd.clzero =3D true; =20 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -734,8 +734,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |=3D DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |=3D SrcMem16; + s->desc |=3D SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -583,6 +583,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2853,8 +2853,35 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, X86_EXC_UD); + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx !=3D vex_f2, + X86_EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_= UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_segment || !ops->read_msr || + !ops->write_segment || !ops->write_msr); + if ( (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->read_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + dst.orig_val =3D sreg.base; /* Preserve full GS Base. */ + if ( (rc =3D protmode_load_seg(x86_seg_gs, src.val, false, &sr= eg, + ctxt, ops)) !=3D X86EMUL_OKAY || + /* Write (32-bit) base into SHADOW_GS. */ + (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + sreg.base =3D dst.orig_val; /* Reinstate full GS Base. */ + if ( (rc =3D ops->write_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + { + /* Best effort unwind (i.e. no real error checking). */ + if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, + ctxt) =3D=3D X86EMUL_EXCEPTION ) + x86_emul_reset_event(ctxt); + goto done; + } break; } break; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -281,6 +281,8 @@ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) / XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ +XEN_CPUFEATURE(FRED, 10*32+17) /* Flexible Return and Event Deli= very */ +XEN_CPUFEATURE(LKGS, 10*32+18) /*S Load Kernel GS Base */ XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ =20 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -295,6 +295,9 @@ def crunch_numbers(state): =20 # In principle the TSXLDTRK insns could also be considered indepen= dent. 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charset="utf-8" Unconditionally wire this through the ->rmw() hook. Since x86_emul_rmw() now wants to construct and invoke a stub, make stub_exn available to it via a new field in the emulator state structure. Signed-off-by: Jan Beulich --- v2: Use X86_EXC_*. Move past introduction of stub_exn in struct x86_emulate_state. Keep feature at just "a" for now. --- SDE: -grr or -srf --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -232,6 +232,7 @@ int libxl_cpuid_parse_config(libxl_cpuid =20 {"avx-vnni", 0x00000007, 1, CPUID_REG_EAX, 4, 1}, {"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1}, + {"cmpccxadd", 0x00000007, 1, CPUID_REG_EAX, 7, 1}, {"fzrm", 0x00000007, 1, CPUID_REG_EAX, 10, 1}, {"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1}, {"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -186,6 +186,7 @@ static const char *const str_7d0[32] =3D static const char *const str_7a1[32] =3D { [ 4] =3D "avx-vnni", [ 5] =3D "avx512-bf16", + /* 6 */ [ 7] =3D "cmpccxadd", =20 [10] =3D "fzrm", [11] =3D "fsrs", [12] =3D "fsrcs", --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1403,6 +1403,22 @@ static const struct vex { { { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */ { { 0xde }, 2, T, R, pfx_66, WIG, Ln }, /* vaesdec */ { { 0xdf }, 2, T, R, pfx_66, WIG, Ln }, /* vaesdeclast */ + { { 0xe0 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpoxadd */ + { { 0xe1 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpnoxadd */ + { { 0xe2 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpbxadd */ + { { 0xe3 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpnbxadd */ + { { 0xe4 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpexadd */ + { { 0xe5 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpnexadd */ + { { 0xe6 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpbexadd */ + { { 0xe7 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpaxadd */ + { { 0xe8 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpsxadd */ + { { 0xe9 }, 2, F, W, pfx_66, Wn, L0 }, /* cmpnsxadd */ + { { 0xea }, 2, F, W, pfx_66, Wn, L0 }, /* cmppxadd */ + { { 0xeb }, 2, F, W, pfx_66, Wn, L0 }, /* cmpnpxadd */ + { { 0xec }, 2, F, W, pfx_66, Wn, L0 }, /* cmplxadd */ + { { 0xed }, 2, F, W, pfx_66, Wn, L0 }, /* cmpgexadd */ + { { 0xee }, 2, F, W, pfx_66, Wn, L0 }, /* cmplexadd */ + { { 0xef }, 2, F, W, pfx_66, Wn, L0 }, /* cmpgxadd */ { { 0xf2 }, 2, T, R, pfx_no, Wn, L0 }, /* andn */ { { 0xf3, 0x08 }, 2, T, R, pfx_no, Wn, L0 }, /* blsr */ { { 0xf3, 0x10 }, 2, T, R, pfx_no, Wn, L0 }, /* blsmsk */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -1398,6 +1398,78 @@ int main(int argc, char **argv) } printf("okay\n"); =20 + printf("%-40s", "Testing cmpbxadd %rbx,%r9,(%rdx)..."); + if ( stack_exec && cpu_has_cmpccxadd ) + { + instr[0] =3D 0xc4; instr[1] =3D 0x62; instr[2] =3D 0xe1; instr[3] = =3D 0xe2; instr[4] =3D 0x0a; + regs.rip =3D (unsigned long)&instr[0]; + regs.eflags =3D EFLAGS_ALWAYS_SET; + res[0] =3D 0x11223344; + res[1] =3D 0x01020304; + regs.rdx =3D (unsigned long)res; + regs.r9 =3D 0x0001020300112233UL; + regs.rbx =3D 0x0101010101010101UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (regs.r9 !=3D 0x0102030411223344UL) || + (regs.rbx !=3D 0x0101010101010101UL) || + ((regs.eflags & EFLAGS_MASK) !=3D + (X86_EFLAGS_PF | EFLAGS_ALWAYS_SET)) || + (res[0] !=3D 0x11223344) || + (res[1] !=3D 0x01020304) ) + goto fail; + + regs.rip =3D (unsigned long)&instr[0]; + regs.r9 <<=3D 8; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (regs.r9 !=3D 0x0102030411223344UL) || + (regs.rbx !=3D 0x0101010101010101UL) || + ((regs.eflags & EFLAGS_MASK) !=3D + (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_SF | + EFLAGS_ALWAYS_SET)) || + (res[0] !=3D 0x12233445) || + (res[1] !=3D 0x02030405) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing cmpsxadd %r9d,%ebx,4(%r10)..."); + instr[1] =3D 0xc2; instr[2] =3D 0x31; instr[3] =3D 0xe8; instr[4] = =3D 0x5a; instr[5] =3D 0x04; + regs.rip =3D (unsigned long)&instr[0]; + res[2] =3D res[0] =3D ~0; + regs.r10 =3D (unsigned long)res; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[6]) || + (regs.r9 !=3D 0x0102030411223344UL) || + (regs.rbx !=3D 0x02030405) || + ((regs.eflags & EFLAGS_MASK) !=3D EFLAGS_ALWAYS_SET) || + (res[0] + 1) || + (res[1] !=3D 0x02030405) || + (res[2] + 1) ) + goto fail; + + regs.rip =3D (unsigned long)&instr[0]; + regs.rbx <<=3D 8; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[6]) || + (regs.r9 !=3D 0x0102030411223344UL) || + (regs.rbx !=3D 0x02030405) || + ((regs.eflags & EFLAGS_MASK) !=3D + (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_SF | + EFLAGS_ALWAYS_SET)) || + (res[0] + 1) || + (res[1] !=3D 0x13253749) || + (res[2] + 1) ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + emulops.write_segment =3D write_segment; emulops.write_msr =3D write_msr; =20 --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -185,6 +185,7 @@ void wrpkru(unsigned int val); #define cpu_has_serialize cp.feat.serialize #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) +#define cpu_has_cmpccxadd cp.feat.cmpccxadd #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) #define cpu_has_avx_vnni_int8 (cp.feat.avx_vnni_int8 && xcr0_mask(6)) #define cpu_has_avx_ne_convert (cp.feat.avx_ne_convert && xcr0_mask(6)) --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -170,6 +170,7 @@ extern struct cpuinfo_x86 boot_cpu_data; /* CPUID level 0x00000007:1.eax */ #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) #define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) +#define cpu_has_cmpccxadd boot_cpu_has(X86_FEATURE_CMPCCXADD) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) =20 /* CPUID level 0x00000007:1.edx */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -433,6 +433,7 @@ static const struct ext0f38_table { [0xcf] =3D { .simd_size =3D simd_packed_int, .d8s =3D d8s_vl }, [0xdb] =3D { .simd_size =3D simd_packed_int, .two_op =3D 1 }, [0xdc ... 0xdf] =3D { .simd_size =3D simd_packed_int, .d8s =3D d8s_vl = }, + [0xe0 ... 0xef] =3D { .to_mem =3D 1 }, [0xf0] =3D { .two_op =3D 1 }, [0xf1] =3D { .to_mem =3D 1, .two_op =3D 1 }, [0xf2 ... 0xf3] =3D {}, @@ -924,6 +925,8 @@ decode_0f38(struct x86_emulate_state *s, ctxt->opcode |=3D MASK_INSR(s->vex.pfx, X86EMUL_OPC_PFX_MASK); break; =20 + case X86EMUL_OPC_VEX_66(0, 0xe0) ... + X86EMUL_OPC_VEX_66(0, 0xef): /* cmpxadd */ case X86EMUL_OPC_VEX(0, 0xf2): /* andn */ case X86EMUL_OPC_VEX(0, 0xf3): /* Grp 17 */ case X86EMUL_OPC_VEX(0, 0xf5): /* bzhi */ --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -253,6 +253,7 @@ struct x86_emulate_state { rmw_btc, rmw_btr, rmw_bts, + rmw_cmpccxadd, rmw_dec, rmw_inc, rmw_neg, @@ -583,6 +584,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) +#define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) #define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6888,6 +6888,15 @@ x86_emulate( =20 #endif /* !X86EMUL_NO_SIMD */ =20 + case X86EMUL_OPC_VEX_66(0x0f38, 0xe0) ... + X86EMUL_OPC_VEX_66(0x0f38, 0xef): /* cmpxadd r,r,m */ + generate_exception_if(!mode_64bit() || dst.type !=3D OP_MEM || vex= .l, + X86_EXC_UD); + host_and_vcpu_must_have(cmpccxadd); + fail_if(!ops->rmw); + state->rmw =3D rmw_cmpccxadd; + break; + case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */ case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */ vcpu_must_have(movbe); @@ -7949,14 +7958,20 @@ x86_emulate( { ea.val =3D src.val; op_bytes =3D dst.bytes; + state->stub_exn =3D &stub_exn; rc =3D ops->rmw(dst.mem.seg, dst.mem.off, dst.bytes, &_regs.eflags, state, ctxt); +#ifdef __XEN__ + if ( rc =3D=3D X86EMUL_stub_failure ) + goto emulation_stub_failure; +#endif if ( rc !=3D X86EMUL_OKAY ) goto done; =20 /* Some operations require a register to be written. */ switch ( state->rmw ) { + case rmw_cmpccxadd: case rmw_xchg: case rmw_xadd: switch ( dst.bytes ) @@ -8233,6 +8248,7 @@ int x86_emul_rmw( uint32_t *eflags, struct x86_emulate_state *state, struct x86_emulate_ctxt *ctxt) +#define stub_exn (*state->stub_exn) /* for invoke_stub() */ { unsigned long *dst =3D ptr; =20 @@ -8298,6 +8314,37 @@ int x86_emul_rmw( #undef BINOP #undef SHIFT =20 +#ifdef __x86_64__ + case rmw_cmpccxadd: + { + struct x86_emulate_stub stub =3D {}; + uint8_t *buf =3D get_stub(stub); + typeof(state->vex) *pvex =3D container_of(buf + 1, typeof(state->v= ex), + raw[0]); + unsigned long dummy; + + buf[0] =3D 0xc4; + *pvex =3D state->vex; + pvex->b =3D 1; + pvex->r =3D 1; + pvex->reg =3D 0xf; /* rAX */ + buf[3] =3D ctxt->opcode; + buf[4] =3D 0x11; /* reg=3DrDX r/m=3D(%RCX) */ + buf[5] =3D 0xc3; + + *eflags &=3D ~EFLAGS_MASK; + invoke_stub("", + _POST_EFLAGS("[eflags]", "[mask]", "[tmp]"), + "+m" (*dst), "+d" (state->ea.val), + [tmp] "=3D&r" (dummy), [eflags] "+g" (*eflags) + : "a" (*decode_vex_gpr(state->vex.reg, ctxt->regs, ctx= t)), + "c" (dst), [mask] "i" (EFLAGS_MASK)); + + put_stub(stub); + break; + } +#endif + case rmw_not: switch ( state->op_bytes ) { @@ -8393,7 +8440,13 @@ int x86_emul_rmw( #undef JCXZ =20 return X86EMUL_OKAY; + +#if defined(__XEN__) && defined(__x86_64__) + emulation_stub_failure: + return X86EMUL_stub_failure; +#endif } +#undef stub_exn =20 static void __init __maybe_unused build_assertions(void) { --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -278,6 +278,7 @@ XEN_CPUFEATURE(SSBD, 9*32+31) / /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ +XEN_CPUFEATURE(CMPCCXADD, 10*32+ 7) /*a CMPccXADD Instructions */ XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ From nobody Sat May 18 21:45:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This is a prereq to enabling the MSRLIST feature. Note that the PROCBASED_CTLS3 MSR is different from other VMX feature reporting MSRs, in that all 64 bits report allowed 1-settings. vVMX code is left alone, though, for the time being. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -164,6 +164,7 @@ static int cf_check parse_ept_param_runt u32 vmx_pin_based_exec_control __read_mostly; u32 vmx_cpu_based_exec_control __read_mostly; u32 vmx_secondary_exec_control __read_mostly; +uint64_t vmx_tertiary_exec_control __read_mostly; u32 vmx_vmexit_control __read_mostly; u32 vmx_vmentry_control __read_mostly; u64 vmx_ept_vpid_cap __read_mostly; @@ -229,10 +230,32 @@ static u32 adjust_vmx_controls( return ctl; } =20 -static bool_t cap_check(const char *name, u32 expected, u32 saw) +static uint64_t adjust_vmx_controls2( + const char *name, uint64_t ctl_min, uint64_t ctl_opt, unsigned int msr, + bool *mismatch) +{ + uint64_t vmx_msr, ctl =3D ctl_min | ctl_opt; + + rdmsrl(msr, vmx_msr); + + ctl &=3D vmx_msr; /* bit =3D=3D 0 =3D=3D> must be zero */ + + /* Ensure minimum (required) set of control bits are supported. */ + if ( ctl_min & ~ctl ) + { + *mismatch =3D true; + printk("VMX: CPU%u has insufficient %s (%#lx; requires %#lx)\n", + smp_processor_id(), name, ctl, ctl_min); + } + + return ctl; +} + +static bool cap_check( + const char *name, unsigned long expected, unsigned long saw) { if ( saw !=3D expected ) - printk("VMX %s: saw %#x expected %#x\n", name, saw, expected); + printk("VMX %s: saw %#lx expected %#lx\n", name, saw, expected); return saw !=3D expected; } =20 @@ -242,6 +265,7 @@ static int vmx_init_vmcs_config(bool bsp u32 _vmx_pin_based_exec_control; u32 _vmx_cpu_based_exec_control; u32 _vmx_secondary_exec_control =3D 0; + uint64_t _vmx_tertiary_exec_control =3D 0; u64 _vmx_ept_vpid_cap =3D 0; u64 _vmx_misc_cap =3D 0; u32 _vmx_vmexit_control; @@ -275,7 +299,8 @@ static int vmx_init_vmcs_config(bool bsp opt =3D (CPU_BASED_ACTIVATE_MSR_BITMAP | CPU_BASED_TPR_SHADOW | CPU_BASED_MONITOR_TRAP_FLAG | - CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); + CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | + CPU_BASED_ACTIVATE_TERTIARY_CONTROLS); _vmx_cpu_based_exec_control =3D adjust_vmx_controls( "CPU-Based Exec Control", min, opt, MSR_IA32_VMX_PROCBASED_CTLS, &mismatch); @@ -339,6 +364,15 @@ static int vmx_init_vmcs_config(bool bsp MSR_IA32_VMX_PROCBASED_CTLS2, &mismatch); } =20 + if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROL= S ) + { + uint64_t opt =3D 0; + + _vmx_tertiary_exec_control =3D adjust_vmx_controls2( + "Tertiary Exec Control", 0, opt, + MSR_IA32_VMX_PROCBASED_CTLS3, &mismatch); + } + /* The IA32_VMX_EPT_VPID_CAP MSR exists only when EPT or VPID availabl= e */ if ( _vmx_secondary_exec_control & (SECONDARY_EXEC_ENABLE_EPT | SECONDARY_EXEC_ENABLE_VPID) ) @@ -469,6 +503,7 @@ static int vmx_init_vmcs_config(bool bsp vmx_pin_based_exec_control =3D _vmx_pin_based_exec_control; vmx_cpu_based_exec_control =3D _vmx_cpu_based_exec_control; vmx_secondary_exec_control =3D _vmx_secondary_exec_control; + vmx_tertiary_exec_control =3D _vmx_tertiary_exec_control; vmx_ept_vpid_cap =3D _vmx_ept_vpid_cap; vmx_vmexit_control =3D _vmx_vmexit_control; vmx_vmentry_control =3D _vmx_vmentry_control; @@ -505,6 +540,9 @@ static int vmx_init_vmcs_config(bool bsp "Secondary Exec Control", vmx_secondary_exec_control, _vmx_secondary_exec_control); mismatch |=3D cap_check( + "Tertiary Exec Control", + vmx_tertiary_exec_control, _vmx_tertiary_exec_control); + mismatch |=3D cap_check( "VMExit Control", vmx_vmexit_control, _vmx_vmexit_control); mismatch |=3D cap_check( @@ -1082,6 +1120,7 @@ static int construct_vmcs(struct vcpu *v v->arch.hvm.vmx.exec_control |=3D CPU_BASED_RDTSC_EXITING; =20 v->arch.hvm.vmx.secondary_exec_control =3D vmx_secondary_exec_control; + v->arch.hvm.vmx.tertiary_exec_control =3D vmx_tertiary_exec_control; =20 /* * Disable features which we don't want active by default: @@ -1136,6 +1175,10 @@ static int construct_vmcs(struct vcpu *v __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm.vmx.secondary_exec_control); =20 + if ( cpu_has_vmx_tertiary_exec_control ) + __vmwrite(TERTIARY_VM_EXEC_CONTROL, + v->arch.hvm.vmx.tertiary_exec_control); + /* MSR access bitmap. */ if ( cpu_has_vmx_msr_bitmap ) { @@ -2071,10 +2114,12 @@ void vmcs_dump_vcpu(struct vcpu *v) vmr(HOST_PERF_GLOBAL_CTRL)); =20 printk("*** Control State ***\n"); - printk("PinBased=3D%08x CPUBased=3D%08x SecondaryExec=3D%08x\n", + printk("PinBased=3D%08x CPUBased=3D%08x\n", vmr32(PIN_BASED_VM_EXEC_CONTROL), - vmr32(CPU_BASED_VM_EXEC_CONTROL), - vmr32(SECONDARY_VM_EXEC_CONTROL)); + vmr32(CPU_BASED_VM_EXEC_CONTROL)); + printk("SecondaryExec=3D%08x TertiaryExec=3D%08lx\n", + vmr32(SECONDARY_VM_EXEC_CONTROL), + vmr(TERTIARY_VM_EXEC_CONTROL)); printk("EntryControls=3D%08x ExitControls=3D%08x\n", vmentry_ctl, vmex= it_ctl); printk("ExceptionBitmap=3D%08x PFECmask=3D%08x PFECmatch=3D%08x\n", vmr32(EXCEPTION_BITMAP), --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -114,6 +114,7 @@ struct vmx_vcpu { /* Cache of cpu execution control. */ u32 exec_control; u32 secondary_exec_control; + uint64_t tertiary_exec_control; u32 exception_bitmap; =20 uint64_t shadow_gs; @@ -196,6 +197,7 @@ void vmx_vmcs_reload(struct vcpu *v); #define CPU_BASED_RDTSC_EXITING 0x00001000 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 +#define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS 0x00020000 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 #define CPU_BASED_TPR_SHADOW 0x00200000 @@ -260,6 +262,13 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 extern u32 vmx_secondary_exec_control; =20 +#define TERTIARY_EXEC_LOADIWKEY_EXITING BIT(0, UL) +#define TERTIARY_EXEC_ENABLE_HLAT BIT(1, UL) +#define TERTIARY_EXEC_EPT_PAGING_WRITE BIT(2, UL) +#define TERTIARY_EXEC_GUEST_PAGING_VERIFY BIT(3, UL) +#define TERTIARY_EXEC_IPI_VIRT BIT(4, UL) +extern uint64_t vmx_tertiary_exec_control; + #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 #define VMX_EPT_WALK_LENGTH_4_SUPPORTED 0x00000040 #define VMX_EPT_MEMORY_TYPE_UC 0x00000100 @@ -295,6 +304,8 @@ extern u64 vmx_ept_vpid_cap; (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP) #define cpu_has_vmx_secondary_exec_control \ (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) +#define cpu_has_vmx_tertiary_exec_control \ + (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) #define cpu_has_vmx_ept \ (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) #define cpu_has_vmx_dt_exiting \ @@ -418,6 +429,7 @@ enum vmcs_field { VIRT_EXCEPTION_INFO =3D 0x0000202a, XSS_EXIT_BITMAP =3D 0x0000202c, TSC_MULTIPLIER =3D 0x00002032, + TERTIARY_VM_EXEC_CONTROL =3D 0x00002034, GUEST_PHYSICAL_ADDRESS =3D 0x00002400, VMCS_LINK_POINTER =3D 0x00002800, GUEST_IA32_DEBUGCTL =3D 0x00002802, --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -320,6 +320,7 @@ #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 #define MSR_IA32_VMX_VMFUNC 0x491 +#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492 =20 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -760,6 +760,12 @@ void vmx_update_secondary_exec_control(s v->arch.hvm.vmx.secondary_exec_control); } =20 +void vmx_update_tertiary_exec_control(struct vcpu *v) +{ + __vmwrite(TERTIARY_VM_EXEC_CONTROL, + v->arch.hvm.vmx.tertiary_exec_control); +} + void vmx_update_exception_bitmap(struct vcpu *v) { u32 bitmap =3D unlikely(v->arch.hvm.vmx.vmx_realmode) --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -80,6 +80,7 @@ void vmx_realmode(struct cpu_user_regs * void vmx_update_exception_bitmap(struct vcpu *v); void vmx_update_cpu_exec_control(struct vcpu *v); void vmx_update_secondary_exec_control(struct vcpu *v); +void vmx_update_tertiary_exec_control(struct vcpu *v); =20 #define POSTED_INTR_ON 0 #define POSTED_INTR_SN 1 From nobody Sat May 18 21:45:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" These are "compound" instructions to issue a series of RDMSR / WRMSR respectively. In the emulator we can therefore implement them by using the existing msr_{read,write}() hooks. The memory accesses utilize that the HVM ->read() / ->write() hooks are already linear-address (x86_seg_none) aware (by way of hvmemul_virtual_to_linear() handling this case). Preemption is being checked for in WRMSRLIST handling only, as only MSR writes are expected to possibly take long. Signed-off-by: Jan Beulich --- TODO: Once VMX tertiary execution control bit is known (see //todo) further adjust cpufeatureset.h. RFC: In vmx_vmexit_handler() handling is forwarded to the emulator blindly. Alternatively we could consult the exit qualification and process just a single MSR at a time (without involving the emulator), exiting back to the guest after every iteration. (I don't think a mix of both models makes a lot of sense.) With the VMX side of the spec still unclear (tertiary execution control bit still unspecified in ISE 048) we can't enable the insn yet for (HVM) guest use. The precise behavior of MSR_BARRIER is also not spelled out, so the (minimal) implementation is a guess for now. --- v2: Use X86_EXC_*. Add preemption checking to WRMSRLIST handling. Remove the feature from "max" when the VMX counterpart isn't available. --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -240,6 +240,7 @@ int libxl_cpuid_parse_config(libxl_cpuid {"lkgs", 0x00000007, 1, CPUID_REG_EAX, 18, 1}, {"wrmsrns", 0x00000007, 1, CPUID_REG_EAX, 19, 1}, {"avx-ifma", 0x00000007, 1, CPUID_REG_EAX, 23, 1}, + {"msrlist", 0x00000007, 1, CPUID_REG_EAX, 27, 1}, =20 {"avx-vnni-int8",0x00000007, 1, CPUID_REG_EDX, 4, 1}, {"avx-ne-convert",0x00000007, 1, CPUID_REG_EDX, 5, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -195,6 +195,8 @@ static const char *const str_7a1[32] =3D [18] =3D "lkgs", [19] =3D "wrmsrns", =20 /* 22 */ [23] =3D "avx-ifma", + + /* 26 */ [27] =3D "msrlist", }; =20 static const char *const str_e21a[32] =3D --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -342,6 +342,8 @@ static const struct { { { 0x01, 0xc4 }, { 2, 2 }, F, N }, /* vmxoff */ { { 0x01, 0xc5 }, { 2, 2 }, F, N }, /* pconfig */ { { 0x01, 0xc6 }, { 2, 2 }, F, N }, /* wrmsrns */ + { { 0x01, 0xc6 }, { 0, 2 }, F, W, pfx_f2 }, /* rdmsrlist */ + { { 0x01, 0xc6 }, { 0, 2 }, F, R, pfx_f3 }, /* wrmsrlist */ { { 0x01, 0xc8 }, { 2, 2 }, F, N }, /* monitor */ { { 0x01, 0xc9 }, { 2, 2 }, F, N }, /* mwait */ { { 0x01, 0xca }, { 2, 2 }, F, N }, /* clac */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -589,6 +589,7 @@ static int read( default: if ( !is_x86_user_segment(seg) ) return X86EMUL_UNHANDLEABLE; + case x86_seg_none: bytes_read +=3D bytes; break; } @@ -619,7 +620,7 @@ static int write( if ( verbose ) printf("** %s(%u, %p,, %u,)\n", __func__, seg, (void *)offset, byt= es); =20 - if ( !is_x86_user_segment(seg) ) + if ( !is_x86_user_segment(seg) && seg !=3D x86_seg_none ) return X86EMUL_UNHANDLEABLE; memcpy((void *)offset, p_data, bytes); return X86EMUL_OKAY; @@ -711,6 +712,10 @@ static int read_msr( { switch ( reg ) { + case 0x0000002f: /* BARRIER */ + *val =3D 0; + return X86EMUL_OKAY; + case 0xc0000080: /* EFER */ *val =3D ctxt->addr_size > 32 ? 0x500 /* LME|LMA */ : 0; return X86EMUL_OKAY; @@ -1499,9 +1504,53 @@ int main(int argc, char **argv) (gs_base !=3D 0x0000111122224444UL) || gs_base_shadow ) goto fail; + printf("okay\n"); =20 cp.extd.nscb =3D i; emulops.write_segment =3D NULL; + + printf("%-40s", "Testing rdmsrlist..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x01; instr[3] =3D = 0xc6; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D (unsigned long)(res + 0x80); + regs.rdi =3D (unsigned long)(res + 0x80 + 0x40 * 2); + regs.rcx =3D 0x0002000100008000UL; + gs_base_shadow =3D 0x0000222244446666UL; + memset(res + 0x80, ~0, 0x40 * 8 * 2); + res[0x80 + 0x0f * 2] =3D 0xc0000101; /* GS_BASE */ + res[0x80 + 0x0f * 2 + 1] =3D 0; + res[0x80 + 0x20 * 2] =3D 0xc0000102; /* SHADOW_GS_BASE */ + res[0x80 + 0x20 * 2 + 1] =3D 0; + res[0x80 + 0x31 * 2] =3D 0x2f; /* BARRIER */ + res[0x80 + 0x31 * 2 + 1] =3D 0; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[4]) || + regs.rcx || + (res[0x80 + (0x40 + 0x0f) * 2] !=3D (unsigned int)gs_base) || + (res[0x80 + (0x40 + 0x0f) * 2 + 1] !=3D (gs_base >> (8 * sizeof(i= nt)))) || + (res[0x80 + (0x40 + 0x20) * 2] !=3D (unsigned int)gs_base_shadow)= || + (res[0x80 + (0x40 + 0x20) * 2 + 1] !=3D (gs_base_shadow >> (8 * s= izeof(int)))) || + res[0x80 + (0x40 + 0x31) * 2] || res[0x80 + (0x40 + 0x31) * 2 + 1= ] ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing wrmsrlist..."); + instr[0] =3D 0xf3; instr[1] =3D 0x0f; instr[2] =3D 0x01; instr[3] =3D = 0xc6; + regs.eip =3D (unsigned long)&instr[0]; + regs.rsi -=3D 0x11 * 8; + regs.rdi -=3D 0x11 * 8; + regs.rcx =3D 0x0002000100000000UL; + res[0x80 + 0x0f * 2] =3D 0xc0000102; /* SHADOW_GS_BASE */ + res[0x80 + 0x20 * 2] =3D 0xc0000101; /* GS_BASE */ + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[4]) || + regs.rcx || + (gs_base !=3D 0x0000222244446666UL) || + (gs_base_shadow !=3D 0x0000111122224444UL) ) + goto fail; + emulops.write_msr =3D NULL; #endif printf("okay\n"); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -88,6 +88,7 @@ bool emul_test_init(void) cp.feat.rdpid =3D true; cp.feat.lkgs =3D true; cp.feat.wrmsrns =3D true; + cp.feat.msrlist =3D true; cp.extd.clzero =3D true; =20 if ( cpu_has_xsave ) --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -601,6 +601,9 @@ static void __init calculate_hvm_max_pol __clear_bit(X86_FEATURE_XSAVES, fs); } =20 + if ( !cpu_has_vmx_msrlist ) + __clear_bit(X86_FEATURE_MSRLIST, fs); + /* * Xen doesn't use PKS, so the guest support for it has opted to not u= se * the VMCS load/save controls for efficiency reasons. This depends on --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -830,6 +830,20 @@ static void cf_check vmx_cpuid_policy_ch else vmx_set_msr_intercept(v, MSR_PKRS, VMX_MSR_RW); =20 + if ( cp->feat.msrlist ) + { + vmx_clear_msr_intercept(v, MSR_BARRIER, VMX_MSR_RW); + v->arch.hvm.vmx.tertiary_exec_control |=3D TERTIARY_EXEC_ENABLE_MS= RLIST; + vmx_update_tertiary_exec_control(v); + } + else if ( v->arch.hvm.vmx.tertiary_exec_control & + TERTIARY_EXEC_ENABLE_MSRLIST ) + { + vmx_set_msr_intercept(v, MSR_BARRIER, VMX_MSR_RW); + v->arch.hvm.vmx.tertiary_exec_control &=3D ~TERTIARY_EXEC_ENABLE_M= SRLIST; + vmx_update_tertiary_exec_control(v); + } + out: vmx_vmcs_exit(v); =20 @@ -3700,6 +3714,22 @@ gp_fault: return X86EMUL_EXCEPTION; } =20 +static bool cf_check is_msrlist( + const struct x86_emulate_state *state, const struct x86_emulate_ctxt *= ctxt) +{ + + if ( ctxt->opcode =3D=3D X86EMUL_OPC(0x0f, 0x01) ) + { + unsigned int rm, reg; + int mode =3D x86_insn_modrm(state, &rm, ®); + + /* This also includes WRMSRNS; should be okay. */ + return mode =3D=3D 3 && rm =3D=3D 6 && !reg; + } + + return false; +} + static void vmx_do_extint(struct cpu_user_regs *regs) { unsigned long vector; @@ -4507,6 +4537,17 @@ void vmx_vmexit_handler(struct cpu_user_ } break; =20 + case EXIT_REASON_RDMSRLIST: + case EXIT_REASON_WRMSRLIST: + if ( vmx_guest_x86_mode(v) !=3D 8 || !currd->arch.cpuid->feat.msrl= ist ) + { + ASSERT_UNREACHABLE(); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); + } + else if ( !hvm_emulate_one_insn(is_msrlist, "MSR list") ) + hvm_inject_hw_exception(X86_EXC_GP, 0); + break; + case EXIT_REASON_VMXOFF: case EXIT_REASON_VMXON: case EXIT_REASON_VMCLEAR: --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -267,6 +267,7 @@ extern u32 vmx_secondary_exec_control; #define TERTIARY_EXEC_EPT_PAGING_WRITE BIT(2, UL) #define TERTIARY_EXEC_GUEST_PAGING_VERIFY BIT(3, UL) #define TERTIARY_EXEC_IPI_VIRT BIT(4, UL) +#define TERTIARY_EXEC_ENABLE_MSRLIST 0//todo extern uint64_t vmx_tertiary_exec_control; =20 #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -352,6 +353,8 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_BUS_LOCK_DETECTION) #define cpu_has_vmx_notify_vm_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) +#define cpu_has_vmx_msrlist \ + (vmx_tertiary_exec_control & TERTIARY_EXEC_ENABLE_MSRLIST) =20 #define VMCS_RID_TYPE_MASK 0x80000000 =20 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -201,6 +201,8 @@ static inline void pi_clear_sn(struct pi #define EXIT_REASON_XRSTORS 64 #define EXIT_REASON_BUS_LOCK 74 #define EXIT_REASON_NOTIFY 75 +#define EXIT_REASON_RDMSRLIST 78 +#define EXIT_REASON_WRMSRLIST 79 /* Remember to also update VMX_PERF_EXIT_REASON_SIZE! */ =20 /* --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -24,6 +24,8 @@ #define APIC_BASE_ENABLE (_AC(1, ULL) << 11) #define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL =20 +#define MSR_BARRIER 0x0000002f + #define MSR_TEST_CTRL 0x00000033 #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) #define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) --- a/xen/arch/x86/include/asm/perfc_defn.h +++ b/xen/arch/x86/include/asm/perfc_defn.h @@ -6,7 +6,7 @@ PERFCOUNTER_ARRAY(exceptions, =20 #ifdef CONFIG_HVM =20 -#define VMX_PERF_EXIT_REASON_SIZE 76 +#define VMX_PERF_EXIT_REASON_SIZE 80 #define VMEXIT_NPF_PERFC 143 #define SVM_PERF_EXIT_REASON_SIZE (VMEXIT_NPF_PERFC + 1) PERFCOUNTER_ARRAY(vmexits, "vmexits", --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -72,6 +72,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t case MSR_AMD_PPIN: goto gp_fault; =20 + case MSR_BARRIER: + if ( !cp->feat.msrlist ) + goto gp_fault; + *val =3D 0; + break; + case MSR_IA32_FEATURE_CONTROL: /* * Architecturally, availability of this MSR is enumerated by the @@ -341,6 +347,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t uint64_t rsvd; =20 /* Read-only */ + case MSR_BARRIER: case MSR_IA32_PLATFORM_ID: case MSR_CORE_CAPABILITIES: case MSR_INTEL_CORE_THREAD_COUNT: --- a/xen/arch/x86/x86_emulate/0f01.c +++ b/xen/arch/x86/x86_emulate/0f01.c @@ -11,6 +11,7 @@ #include "private.h" =20 #ifdef __XEN__ +#include #include #endif =20 @@ -28,6 +29,7 @@ int x86emul_0f01(struct x86_emulate_stat switch ( s->modrm ) { unsigned long base, limit, cr0, cr0w, cr4; + unsigned int n; struct segment_register sreg; uint64_t msr_val; =20 @@ -42,6 +44,64 @@ int x86emul_0f01(struct x86_emulate_stat ((uint64_t)regs->r(dx) << 32) | regs->eax, ctxt); goto done; + + case vex_f3: /* wrmsrlist */ + vcpu_must_have(msrlist); + generate_exception_if(!mode_64bit(), X86_EXC_UD); + generate_exception_if(!mode_ring0() || (regs->r(si) & 7) || + (regs->r(di) & 7), + X86_EXC_GP, 0); + fail_if(!ops->write_msr); + while ( regs->r(cx) ) + { + n =3D __builtin_ffsl(regs->r(cx)) - 1; + if ( (rc =3D ops->read(x86_seg_none, regs->r(si) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= ) + break; + generate_exception_if(msr_val !=3D (uint32_t)msr_val, + X86_EXC_GP, 0); + base =3D msr_val; + if ( (rc =3D ops->read(x86_seg_none, regs->r(di) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= || + (rc =3D ops->write_msr(base, msr_val, ctxt)) !=3D X86= EMUL_OKAY ) + break; + regs->r(cx) &=3D ~(1UL << n); + +#ifdef __XEN__ + if ( regs->r(cx) && local_events_need_delivery() ) + { + rc =3D X86EMUL_RETRY; + break; + } +#endif + } + goto done; + + case vex_f2: /* rdmsrlist */ + vcpu_must_have(msrlist); + generate_exception_if(!mode_64bit(), X86_EXC_UD); + generate_exception_if(!mode_ring0() || (regs->r(si) & 7) || + (regs->r(di) & 7), + X86_EXC_GP, 0); + fail_if(!ops->read_msr || !ops->write); + while ( regs->r(cx) ) + { + n =3D __builtin_ffsl(regs->r(cx)) - 1; + if ( (rc =3D ops->read(x86_seg_none, regs->r(si) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= ) + break; + generate_exception_if(msr_val !=3D (uint32_t)msr_val, + X86_EXC_GP, 0); + if ( (rc =3D ops->read_msr(msr_val, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->write(x86_seg_none, regs->r(di) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKA= Y ) + break; + regs->r(cx) &=3D ~(1UL << n); + } + if ( rc !=3D X86EMUL_OKAY ) + ctxt->regs->r(cx) =3D regs->r(cx); + goto done; } generate_exception(X86_EXC_UD); =20 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -588,6 +588,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) +#define vcpu_has_msrlist() (ctxt->cpuid->feat.msrlist) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) =20 --- a/xen/arch/x86/x86_emulate/util.c +++ b/xen/arch/x86/x86_emulate/util.c @@ -100,6 +100,9 @@ bool cf_check x86_insn_is_mem_access(con break; =20 case X86EMUL_OPC(0x0f, 0x01): + /* {RD,WR}MSRLIST */ + if ( mode_64bit() && s->modrm =3D=3D 0xc6 ) + return s->vex.pfx >=3D vex_f3; /* Cover CLZERO. */ return (s->modrm_rm & 7) =3D=3D 4 && (s->modrm_reg & 7) =3D=3D 7; } @@ -160,7 +163,11 @@ bool cf_check x86_insn_is_mem_write(cons case 0xff: /* Grp5 */ break; =20 - case X86EMUL_OPC(0x0f, 0x01): /* CLZERO is the odd one. */ + case X86EMUL_OPC(0x0f, 0x01): + /* RDMSRLIST */ + if ( mode_64bit() && s->modrm =3D=3D 0xc6 ) + return s->vex.pfx =3D=3D vex_f2; + /* CLZERO is another odd one. */ return (s->modrm_rm & 7) =3D=3D 4 && (s->modrm_reg & 7) =3D=3D= 7; =20 default: --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -286,6 +286,7 @@ XEN_CPUFEATURE(FRED, 10*32+17) / XEN_CPUFEATURE(LKGS, 10*32+18) /*S Load Kernel GS Base */ XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ +XEN_CPUFEATURE(MSRLIST, 10*32+27) /* MSR list instructions */ =20 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializin= g */