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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:22 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 50147560-5fd7-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256383; x=1724861183; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eIHhs5IXiWMtLXpZ4bVpcdEviO9myYu2vT9d0eE7bZY=; b=NrHgAFgaZGQ5NaUhdRTGs9gRRhpUjgWB/MXm2BqgaN9avVgaruc2/2CGnnu520KV8s MnnNZNyF/yrZMuDDKqqnzHHqNRknjcIo0Neoy8MFpfIJMenRUFq20K1mAH3M51LJMFjt 8JkRKcFmZg+x5Q5lviNbMN/uiucBUaFV6m94fj1VoZRXwBXvtiX5trjJJObZNZKRep6h 6HiJQX7Y9S9PN6OKYTVQNxmwjSHX3Z/dtqgTM8tfW8oMwP9ZqOASX4INI4tZcPPRnPmE 7HmWELLM0RlHzw51I/ZG61BC6vsyPzKJhZuTAe8Y0S1qIWqk8EcvwVvyy8zepuBk0OSv DYPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256383; x=1724861183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eIHhs5IXiWMtLXpZ4bVpcdEviO9myYu2vT9d0eE7bZY=; b=F+q5Rwl5CnJf2Sd6NRfNDzN7jjFHA5OhMXJ9ExGtJY3izp6AaAPoCme2eMFNfeud/0 4qwBxq73QPl88yqa8zP9PCYRId185fZuo4GjwFC9K650m5saMIiIkkzRFE+EdxtRkF3H w8RtKVL0bgOJKqXn+/JvA9yYfG6L76dyvnHDoJJLEx06ttnEcKgKH/0tD/c/gogU8yg/ toJjeHhCsZkphjap9GOe93bctoBRt+bOP31L+IuR29ajqOUc5/NArEHWdI/m3URE5lyd 34RkpzWq9FYCWlf7zsn1W4VYj/iODgz07+ktVsjpgxKBWsV7z1J3XCltvbT21IEjd46w Bc5g== X-Gm-Message-State: AOJu0Yx9SseI4pP5KLbvUCSIK+esaBfmAZfzP4LrwmhUcQ2lbq6QsbEt svZDnyEodwDtT9a6Nrgr6HZyAOB3f2zAvaKLVIDD/2OsTz9MD+PSqSR4Qw== X-Google-Smtp-Source: AGHT+IG6t1lR0jPw4fuojzNy3cEPAh/mC8nhkhX+GydsIroadODO5JHSLlrqrXr7W6b2SoluyjhMnQ== X-Received: by 2002:a05:6512:b10:b0:52e:fc7b:39cb with SMTP id 2adb3069b0e04-533485599aamr1902798e87.26.1724256382485; Wed, 21 Aug 2024 09:06:22 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 4/7] xen/riscv: introduce functionality to work with CPU info Date: Wed, 21 Aug 2024 18:06:13 +0200 Message-ID: <03a703996ae7300a9eda54283711b19c42a7d116.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256412097116600 Content-Type: text/plain; charset="utf-8" Introduce struct pcpu_info to store pCPU-related information. Initially, it includes only processor_id and hart id, but it will be extended to include guest CPU information and temporary variables for saving/restoring vCPU registers. Add set_processor_id() and get_processor_id() functions to set and retrieve the processor_id stored in pcpu_info. Introduce cpuid_to_hartid_map() to convert Xen logical CPUs to hart IDs (physical CPU IDs). Define smp_processor_id() to provide accurate information, replacing the previous "dummy" value of 0. Initialize tp registers to point to pcpu_info[0]. Set processor_id to 0 for logical CPU 0 and store the physical CPU ID in pcpu_info[0]. Signed-off-by: Oleksii Kurochko --- Changes in V5: - add hart_id to pcpu_info; - add comments to pcpu_info members. - define INVALID_HARTID as ULONG_MAX as mhart_id register has MXLEN which = is equal to 32 for RV-32 and 64 for RV-64. - add hart_id to pcpu_info structure. - drop cpuid_to_hartid_map[] and use pcpu_info[] for the same purpose. - introduce new function setup_tp(cpuid). - add the FIXME commit on top of pcpu_info[]. - setup TP register before start_xen() being called. - update the commit message. - change "commit message" to "comment" in "Changes in V4" in "update the c= omment above the code of TP..." --- Changes in V4: - wrap id with () inside set_processor_id(). - code style fixes - update BUG_ON(id > NR_CPUS) in smp_processor_id() and drop the comment above BUG_ON(). - s/__cpuid_to_hartid_map/cpuid_to_hartid_map - s/cpuid_to_hartid_map/cpuid_to_harti ( here cpuid_to_hartid_map is the n= ame of the macros ). - update the comment above the code of TP register initialization in start_xen(). - s/smp_setup_processor_id/smp_setup_bootcpu_id - update the commit message. - cleanup headers which are included in --- Changes in V3: - new patch. --- xen/arch/riscv/Makefile | 2 ++ xen/arch/riscv/include/asm/processor.h | 29 ++++++++++++++++++++++++-- xen/arch/riscv/include/asm/smp.h | 11 ++++++++++ xen/arch/riscv/riscv64/head.S | 4 ++++ xen/arch/riscv/setup.c | 5 +++++ xen/arch/riscv/smp.c | 21 +++++++++++++++++++ xen/arch/riscv/smpboot.c | 8 +++++++ 7 files changed, 78 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/smp.c create mode 100644 xen/arch/riscv/smpboot.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 81b77b13d6..334fd24547 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,8 @@ obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o +obj-y +=3D smp.o +obj-y +=3D smpboot.o obj-y +=3D stubs.o obj-y +=3D traps.o obj-y +=3D vm_event.o diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index 3ae164c265..98c45afb6c 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,8 +12,33 @@ =20 #ifndef __ASSEMBLY__ =20 -/* TODO: need to be implemeted */ -#define smp_processor_id() 0 +#include + +register struct pcpu_info *tp asm ("tp"); + +struct pcpu_info { + unsigned int processor_id; /* Xen CPU id */ + unsigned long hart_id; /* physical CPU id */ +}; + +/* tp points to one of these */ +extern struct pcpu_info pcpu_info[NR_CPUS]; + +#define get_processor_id() (tp->processor_id) +#define set_processor_id(id) do { \ + tp->processor_id =3D (id); \ +} while (0) + +static inline unsigned int smp_processor_id(void) +{ + unsigned int id; + + id =3D get_processor_id(); + + BUG_ON(id > NR_CPUS); + + return id; +} =20 /* On stack VCPU state */ struct cpu_user_regs diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/= smp.h index b1ea91b1eb..2b719616ee 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -5,6 +5,10 @@ #include #include =20 +#include + +#define INVALID_HARTID ULONG_MAX + DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); =20 @@ -14,6 +18,13 @@ DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); */ #define park_offline_cpus false =20 +void smp_set_bootcpu_id(unsigned long boot_cpu_hartid); + +/* + * Mapping between linux logical cpu index and hartid. + */ +#define cpuid_to_hartid(cpu) pcpu_info[cpu].hart_id + #endif =20 /* diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 3261e9fce8..9e5b9a0708 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -55,6 +55,10 @@ FUNC(start) */ jal reset_stack =20 + /* Xen's boot cpu id is equal to 0 so setup TP register for it */ + mv a0, x0 + jal setup_tp + /* restore hart_id ( bootcpu_id ) and dtb address */ mv a0, s0 mv a1, s1 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 13f0e8c77d..e15f34509c 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -8,6 +8,7 @@ #include =20 #include +#include #include =20 void arch_get_xen_caps(xen_capabilities_info_t *info) @@ -40,6 +41,10 @@ void __init noreturn start_xen(unsigned long bootcpu_id, { remove_identity_mapping(); =20 + set_processor_id(0); + + smp_set_bootcpu_id(bootcpu_id); + trap_init(); =20 #ifdef CONFIG_SELF_TESTS diff --git a/xen/arch/riscv/smp.c b/xen/arch/riscv/smp.c new file mode 100644 index 0000000000..478ea5aeab --- /dev/null +++ b/xen/arch/riscv/smp.c @@ -0,0 +1,21 @@ +#include + +/* + * FIXME: make pcpu_info[] dynamically allocated when necessary + * functionality will be ready + */ +/* tp points to one of these per cpu */ +struct pcpu_info pcpu_info[NR_CPUS] =3D { { 0, INVALID_HARTID } }; + +void setup_tp(unsigned int cpuid) +{ + /* + * tp register contains an address of physical cpu information. + * So write physical CPU info of cpuid to tp register. + * It will be used later by get_processor_id() ( look at + * ): + * #define get_processor_id() (tp->processor_id) + */ + asm volatile ( "mv tp, %0" + :: "r" ((unsigned long)&pcpu_info[cpuid]) : "memory" ); +} diff --git a/xen/arch/riscv/smpboot.c b/xen/arch/riscv/smpboot.c new file mode 100644 index 0000000000..34319f8875 --- /dev/null +++ b/xen/arch/riscv/smpboot.c @@ -0,0 +1,8 @@ +#include +#include +#include + +void __init smp_set_bootcpu_id(unsigned long boot_cpu_hartid) +{ + cpuid_to_hartid(0) =3D boot_cpu_hartid; +} --=20 2.46.0