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charset="utf-8" From: Artem Bityutskiy Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky= Lake Xeon: if package C6 is disabled, adjust C6 exit latency and target residenc= y to match core C6 values, instead of using the default package C6 values. Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3a= 9cf77b60dc Make sure a contradictory "preferred-cstates" wouldn't cause bypassing of the added logic. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1267,12 +1267,12 @@ static void __init skx_idle_state_table_ */ static void __init spr_idle_state_table_update(void) { - /* Check if user prefers C1E over C1. */ - if (preferred_states_mask & BIT(2, U)) { - if (preferred_states_mask & BIT(1, U)) - /* Both can't be enabled, stick to the defaults. */ - return; + uint64_t msr; =20 + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U) && + /* Both can't be enabled, stick to the defaults. */ + !(preferred_states_mask & BIT(1, U))) { spr_cstates[0].flags |=3D CPUIDLE_FLAG_DISABLED; spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_DISABLED; =20 @@ -1280,6 +1280,19 @@ static void __init spr_idle_state_table_ idle_cpu_spr.disable_promotion_to_c1e =3D false; idle_cpu_spr.enable_promotion_to_c1e =3D true; } + + /* + * By default, the C6 state assumes the worst-case scenario of package + * C6. However, if PC6 is disabled, we update the numbers to match + * core C6. + */ + rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* Limit value 2 and above allow for PC6. */ + if ((msr & 0x7) < 2) { + spr_cstates[2].exit_latency =3D 190; + spr_cstates[2].target_residency =3D 600; + } } =20 /*