From nobody Sat Apr 20 03:47:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1648924160610193.16507210484406; Sat, 2 Apr 2022 11:29:20 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 0A3BB16E3D15; Sat, 2 Apr 2022 18:29:16 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 9558E16E36D9 for ; Sat, 2 Apr 2022 18:28:57 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by mailout02.t-online.de (Postfix) with SMTP id 83BA85C04; Sat, 2 Apr 2022 20:28:50 +0200 (CEST) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) with (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384 encrypted) esmtp id 1naiUJ-13Ruj30; Sat, 2 Apr 2022 20:28:39 +0200 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) id 5EE8B2006C3; Sat, 2 Apr 2022 20:28:39 +0200 (CEST) From: =?UTF-8?q?Volker=20R=C3=BCmelin?= To: Kevin O'Connor , Gerd Hoffmann Date: Sat, 2 Apr 2022 20:28:38 +0200 Message-Id: <20220402182839.7251-1-vr_qemu@t-online.de> In-Reply-To: References: MIME-Version: 1.0 X-TOI-EXPURGATEID: 150726::1648924119-00000271-E0984827/0/0 CLEAN NORMAL X-TOI-MSGID: de13737c-be6e-4eed-a92d-073eea1291aa Message-ID-Hash: AMFWHHWXLNT4DRVEB4D5WIYGSPH4FXE3 X-Message-ID-Hash: AMFWHHWXLNT4DRVEB4D5WIYGSPH4FXE3 X-MailFrom: volker.ruemelin@t-online.de X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: seabios@seabios.org X-Mailman-Version: 3.3.5rc1 Precedence: list Subject: [SeaBIOS] [PATCH v3 1/2] pci: refactor the pci_config_*() functions List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: ---- X-ZM-MESSAGEID: 1648924163353100001 Split out the Standard PCI Configuration Access Mechanism pci_ioconfig_*() functions from the pci_config_*() functions. The standard PCI CAM functions will be used in the next patch. Reviewed-by: Gerd Hoffmann Signed-off-by: Volker R=C3=BCmelin --- src/hw/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++------------ src/hw/pci.h | 12 +++++++++++- 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 3df1dae..f13cbde 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -26,63 +26,93 @@ static u32 ioconfig_cmd(u16 bdf, u32 addr) return 0x80000000 | (bdf << 8) | (addr & 0xfc); } =20 +void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + outl(val, PORT_PCI_DATA); +} + void pci_config_writel(u16 bdf, u32 addr, u32 val) { if (!MODESEGMENT && mmconfig) { writel(mmconfig_addr(bdf, addr), val); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - outl(val, PORT_PCI_DATA); + pci_ioconfig_writel(bdf, addr, val); } } =20 +void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + outw(val, PORT_PCI_DATA + (addr & 2)); +} + void pci_config_writew(u16 bdf, u32 addr, u16 val) { if (!MODESEGMENT && mmconfig) { writew(mmconfig_addr(bdf, addr), val); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - outw(val, PORT_PCI_DATA + (addr & 2)); + pci_ioconfig_writew(bdf, addr, val); } } =20 +void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + outb(val, PORT_PCI_DATA + (addr & 3)); +} + void pci_config_writeb(u16 bdf, u32 addr, u8 val) { if (!MODESEGMENT && mmconfig) { writeb(mmconfig_addr(bdf, addr), val); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - outb(val, PORT_PCI_DATA + (addr & 3)); + pci_ioconfig_writeb(bdf, addr, val); } } =20 +u32 pci_ioconfig_readl(u16 bdf, u32 addr) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + return inl(PORT_PCI_DATA); +} + u32 pci_config_readl(u16 bdf, u32 addr) { if (!MODESEGMENT && mmconfig) { return readl(mmconfig_addr(bdf, addr)); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - return inl(PORT_PCI_DATA); + return pci_ioconfig_readl(bdf, addr); } } =20 +u16 pci_ioconfig_readw(u16 bdf, u32 addr) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + return inw(PORT_PCI_DATA + (addr & 2)); +} + u16 pci_config_readw(u16 bdf, u32 addr) { if (!MODESEGMENT && mmconfig) { return readw(mmconfig_addr(bdf, addr)); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - return inw(PORT_PCI_DATA + (addr & 2)); + return pci_ioconfig_readw(bdf, addr); } } =20 +u8 pci_ioconfig_readb(u16 bdf, u32 addr) +{ + outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); + return inb(PORT_PCI_DATA + (addr & 3)); +} + u8 pci_config_readb(u16 bdf, u32 addr) { if (!MODESEGMENT && mmconfig) { return readb(mmconfig_addr(bdf, addr)); } else { - outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); - return inb(PORT_PCI_DATA + (addr & 3)); + return pci_ioconfig_readb(bdf, addr); } } =20 diff --git a/src/hw/pci.h b/src/hw/pci.h index 01c51f7..ee6acaf 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -32,6 +32,15 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devf= n) { ; BDF >=3D 0 \ ; BDF=3Dpci_next(BDF, (BUS))) =20 +// standard PCI configration access mechanism +void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val); +void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val); +void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); +u32 pci_ioconfig_readl(u16 bdf, u32 addr); +u16 pci_ioconfig_readw(u16 bdf, u32 addr); +u8 pci_ioconfig_readb(u16 bdf, u32 addr); + +// PCI configuration access using either PCI CAM or PCIe ECAM void pci_config_writel(u16 bdf, u32 addr, u32 val); void pci_config_writew(u16 bdf, u32 addr, u16 val); void pci_config_writeb(u16 bdf, u32 addr, u8 val); @@ -39,9 +48,10 @@ u32 pci_config_readl(u16 bdf, u32 addr); u16 pci_config_readw(u16 bdf, u32 addr); u8 pci_config_readb(u16 bdf, u32 addr); void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); -void pci_enable_mmconfig(u64 addr, const char *name); u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); int pci_next(int bdf, int bus); + +void pci_enable_mmconfig(u64 addr, const char *name); int pci_probe_host(void); void pci_reboot(void); =20 --=20 2.34.1 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org From nobody Sat Apr 20 03:47:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; 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Sat, 2 Apr 2022 20:28:42 +0200 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) id 60D002006C4; Sat, 2 Apr 2022 20:28:39 +0200 (CEST) From: =?UTF-8?q?Volker=20R=C3=BCmelin?= To: Kevin O'Connor , Gerd Hoffmann Date: Sat, 2 Apr 2022 20:28:39 +0200 Message-Id: <20220402182839.7251-2-vr_qemu@t-online.de> In-Reply-To: References: MIME-Version: 1.0 X-TOI-EXPURGATEID: 150726::1648924122-000116DC-ACCF254F/0/0 CLEAN NORMAL X-TOI-MSGID: 89baa2f5-3c3b-4e73-8809-880ed4290183 Message-ID-Hash: MOHRQ5324GRB6B3VH3NX3M56YBSEJXFA X-Message-ID-Hash: MOHRQ5324GRB6B3VH3NX3M56YBSEJXFA X-MailFrom: volker.ruemelin@t-online.de X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: seabios@seabios.org X-Mailman-Version: 3.3.5rc1 Precedence: list Subject: [SeaBIOS] [PATCH v3 2/2] reset: force standard PCI configuration access List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZM-MESSAGEID: 1648924149086100001 After a reset of a QEMU -machine q35 guest, the PCI Express Enhanced Configuration Mechanism is disabled and the variable mmconfig no longer matches the configuration register PCIEXBAR of the Q35 chipset. Until the variable mmconfig is reset to 0, all pci_config_*() functions no longer work. The variable mmconfig is located in one of the read-only C-F segments. To reset it the pci_config_*() functions are needed, but they do not work. Replace all pci_config_*() calls with Standard PCI Configuration Mechanism pci_ioconfig_*() calls until mmconfig is overwritten with 0 by a fresh copy of the BIOS. This fixes In resume (status=3D0) In 32bit resume Attempting a hard reboot Unable to unlock ram - bridge not found and a reset loop with QEMU -accel tcg. Signed-off-by: Volker R=C3=BCmelin --- src/fw/shadow.c | 14 +++++++------- src/hw/pci.c | 27 +++++++++++++++++++++++++++ src/hw/pci.h | 6 ++++++ 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/src/fw/shadow.c b/src/fw/shadow.c index 4c627a8..8930616 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -32,8 +32,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) { // Read in current PAM settings from pci config space union pamdata_u pamdata; - pamdata.data32[0] =3D pci_config_readl(bdf, ALIGN_DOWN(pam0, 4)); - pamdata.data32[1] =3D pci_config_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); + pamdata.data32[0] =3D pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4)); + pamdata.data32[1] =3D pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); u8 *pam =3D &pamdata.data8[pam0 & 0x03]; =20 // Make ram from 0xc0000-0xf0000 writable @@ -46,8 +46,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) pam[0] =3D 0x30; =20 // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); + pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); =20 if (!ram_present) // Copy bios. @@ -59,7 +59,7 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) static void make_bios_writable_intel(u16 bdf, u32 pam0) { - int reg =3D pci_config_readb(bdf, pam0); + int reg =3D pci_ioconfig_readb(bdf, pam0); if (!(reg & 0x10)) { // QEMU doesn't fully implement the piix shadow capabilities - // if ram isn't backing the bios segment when shadowing is @@ -125,8 +125,8 @@ make_bios_writable(void) // At this point, statically allocated variables can't be written, // so do this search manually. int bdf; - foreachbdf(bdf, 0) { - u32 vendev =3D pci_config_readl(bdf, PCI_VENDOR_ID); + pci_ioconfig_foreachbdf(bdf, 0) { + u32 vendev =3D pci_ioconfig_readl(bdf, PCI_VENDOR_ID); u16 vendor =3D vendev & 0xffff, device =3D vendev >> 16; if (vendor =3D=3D PCI_VENDOR_ID_INTEL && device =3D=3D PCI_DEVICE_ID_INTEL_82441) { diff --git a/src/hw/pci.c b/src/hw/pci.c index f13cbde..8eda84b 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -157,6 +157,33 @@ u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) return 0; } =20 +// Helper function for pci_ioconfig_foreachbdf() macro - return next device +int pci_ioconfig_next(int bdf, int bus) +{ + if (pci_bdf_to_fn(bdf) =3D=3D 0 + && (pci_ioconfig_readb(bdf, PCI_HEADER_TYPE) & 0x80) =3D=3D 0) + // Last found device wasn't a multi-function device - skip to + // the next device. + bdf +=3D 8; + else + bdf +=3D 1; + + for (;;) { + if (pci_bdf_to_bus(bdf) !=3D bus) + return -1; + + u16 v =3D pci_ioconfig_readw(bdf, PCI_VENDOR_ID); + if (v !=3D 0x0000 && v !=3D 0xffff) + // Device is present. + return bdf; + + if (pci_bdf_to_fn(bdf) =3D=3D 0) + bdf +=3D 8; + else + bdf +=3D 1; + } +} + // Helper function for foreachbdf() macro - return next device int pci_next(int bdf, int bus) diff --git a/src/hw/pci.h b/src/hw/pci.h index ee6acaf..b2f5baf 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -27,6 +27,11 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devf= n) { return (bus << 8) | devfn; } =20 +#define pci_ioconfig_foreachbdf(BDF, BUS) \ + for (BDF=3Dpci_ioconfig_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ + ; BDF >=3D 0 \ + ; BDF=3Dpci_ioconfig_next(BDF, (BUS))) + #define foreachbdf(BDF, BUS) \ for (BDF=3Dpci_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ ; BDF >=3D 0 \ @@ -39,6 +44,7 @@ void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); u32 pci_ioconfig_readl(u16 bdf, u32 addr); u16 pci_ioconfig_readw(u16 bdf, u32 addr); u8 pci_ioconfig_readb(u16 bdf, u32 addr); +int pci_ioconfig_next(int bdf, int bus); =20 // PCI configuration access using either PCI CAM or PCIe ECAM void pci_config_writel(u16 bdf, u32 addr, u32 val); --=20 2.34.1 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org