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charset="gb2312" Content-Transfer-Encoding: quoted-printable

Currently, pci region on busses= [0] may be migrate to

64-bit mmio space. this will ca= use a mistake to read/write

device config space<= /span>

 

example:

A modern virtio device map to 6= 4-bit mmio space will set

mode to VP_ACCESS_PCICFG, But t= he real device cap is

VIRTIO_PCI_CAP_COMMON_CFG, we c= an not access the cap

rightly.

 

If this is a virtio blk/scsi de= vice as system disk, VM

will not be booted on the devic= e.

 

A simple solution is make devic= e use the 32-bit address

space as much as possible.=

 

This patch changes the placemen= t of the PCI bars.

 

[1] commit 0e21548b15e2 ("= virtio: pci cfg access")

 

Signed-off-by: hulang <hulan= g13@huawei.com>

---

src/fw/pciinit.c | 16 ++= ;+++++++++++++-

1 file changed, 15 insertions(&= #43;), 1 deletion(-)

 

diff --git a/src/fw/pciinit.c b= /src/fw/pciinit.c

index b3e359d7..2e9544dc 100644=

--- a/src/fw/pciinit.c

+++ b/src/fw/pciini= t.c

@@ -1100,8 +1100,12 @@ stat= ic void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r= )

{

     struct= hlist_node *n;

     struct= pci_region_entry *entry;

+    u64 r_e= nd =3D r->base + pci_region_sum(r)

+

     hlist_= for_each_entry_safe(entry, n, &r->list, node) {

     &= nbsp;   u64 addr =3D r->base;

+    &n= bsp;   if (addr + entry->size >=3D r_end)

+    &n= bsp;       continue;

     &= nbsp;   r->base +=3D entry->size;

     &= nbsp;   if (entry->bar =3D=3D -1)

     &= nbsp;       // Update bus base address if ent= ry is a bridge region

@@ -1114,6 +1118,8 @@ stati= c void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)=

 static void pci_bios_map_= devices(struct pci_bus *busses)

{

+    int bus= ;

+

     if (pc= i_bios_init_root_regions_io(busses))

     &= nbsp;   panic("PCI: out of I/O address space\n");<= /o:p>

@@ -1122,6 +1128,15 @@ stat= ic void pci_bios_map_devices(struct pci_bus *busses)

     &= nbsp;   struct pci_region r64_mem, r64_pref;

     &= nbsp;   r64_mem.list.first =3D NULL;

     &= nbsp;   r64_pref.list.first =3D NULL;

+

+    &n= bsp;   // try map pci region to 32bit

+    &n= bsp;   for (bus =3D 0; bus<=3DMaxPCIBus; bus++) {=

+    &n= bsp;       int type;

+    &n= bsp;       for (type =3D 0; type < PCI_REG= ION_TYPE_COUNT; type++)

+    &n= bsp;           pci_region= _map_entries(busses, &busses[bus].r[type]);

+    &n= bsp;   }

+

+    &n= bsp;   // map remaining pci region to 64bit

     &= nbsp;   pci_region_migrate_64bit_entries(&busses[0].r[PCI_REG= ION_TYPE_MEM],

     &= nbsp;            &nb= sp;            =            &r64_= mem);

     &= nbsp;   pci_region_migrate_64bit_entries(&busses[0].r[PCI_REG= ION_TYPE_PREFMEM],

@@ -1166,7 +1181,6 @@ stati= c void pci_bios_map_devices(struct pci_bus *busses)

     &= nbsp;   pcimem64_start =3D 0;

     }=

     // Map= regions on each device.

-    int bus;

     for (b= us =3D 0; bus<=3DMaxPCIBus; bus++) {

     &= nbsp;   int type;

     &= nbsp;   for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type= 3;+)

--

2.33.0

 

 

Best Regards<= /b>=A3=A1=

=BA=FA =C0=CB Hu<= /span> Lang

=BB=AA=CE=AA=D4=C6=BC=C6=CB=E3=B9=AB=CB=BE =B5=C2= =BF=C6 =C8=ED=BC=FE=BF=AA=B7=A2=B9=A4=B3=CC=CA=A6

Espace<= span style=3D"font-family:"=CE=A2=C8=ED=D1=C5=BA=DA",sans-serif;c= olor:gray">=A3=BAh30028282=

Mobile<= span style=3D"font-family:"=CE=A2=C8=ED=D1=C5=BA=DA",sans-serif;c= olor:gray">=A3=BA+86 18212092054<= o:p>

<= b>E-mail=A3=BA<= /b> hulang11@huawei.com=

www.fescoadecco.com

=B0=EC=B9=AB=B5=D8=D6=B7=A3=BA=BA=BC=D6=DD=CA=D0=B1=F5=BD=AD=C7=F8=BD=AD=CA=E7=C2=B7=BB= =AA=CE=AA=D1=D0=BE=BF=CB=F9Z6-4-B06R-087S

 

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