From nobody Thu Dec 26 20:18:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1732114293518340.0174144865101; Wed, 20 Nov 2024 06:51:33 -0800 (PST) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id C9C75E13B0; Wed, 20 Nov 2024 14:51:27 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 15229E1471 for ; Wed, 20 Nov 2024 14:51:11 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) for ; Wed, 20 Nov 2024 06:51:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1732114269; x=1732719069; darn=seabios.org; h=to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=POu9oDmcrq0A4e9nvgjpZe7XXifc1jKz34fNAokZlMI=; b=GfmZ2+DS0V7uxk+qOe3+YeiFkFkVV8XryfPxXFO3+tF6QpFyfhRRNxzpiLSAgfDsQE qGH8mY+ngJfvziLbN74VAdk9g4UMY0uCu04CcugaWnC0yN+dsQU9O9XzhUL03rEkck7m BYAUaV1alMyrF660pqEM0zBxG/DuQ1yJugYNSA0crQ9YcMaIBdKmlni2lWv1Jy1M+vRD tZtVhLCk2jeprm2jeznjvyxQJUqeuYFgvclA4ZmACQz/qB+N1pwVyDIWD182cndyspOw KbSvqXAkE29XTHodaEzRHh0LS9Eg4dy1tQOkm4fYF7019OAs+eclkDSm4ge0wIpeNoox YPaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732114269; x=1732719069; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=POu9oDmcrq0A4e9nvgjpZe7XXifc1jKz34fNAokZlMI=; b=BREyChLawDGq1BBCKv91+Rk/GUKTgZFA522cmQ+3aUHX5zK6aS/vibYtZrHe06yqnv /3eNipqaNARHBzSKnnPyUEnMvh/mwPkemFvBjHCmlm7/u3smzFctIgJOtT6EsRL3AOHZ yVYNF9ku8IYV/SxfKUpipUYdJJLzcCzc1kpVsnQkCaUECmfgGd3bDl9JpLAXAG2xw1Zi hqUgw/wd5xtZ6SBHyI3rSnjUaYAsBdl/k5NgWmUzdLWxP7WSb1eJkv0f9T1uOyHffFlc 0OWL6APZrVB0wH0dqfbX21GPBFNJep3f7OR2JWVjEQ3pl5UUnnlGCMdMqPV+sMmLbuvR p0YA== X-Gm-Message-State: AOJu0YxMzH2QdBQAVI+0qJo1vL5cSvOGJ/Y/tgqSgnRFNgyRq+X6xUcK jbblWKewgYD378ToKbjH9pBBi+OsAWHPAVawR1ENcigmEKQGE4DRIag60rFNGsYFr6y/28LnfJS GvRhK7FynbtaFEdxKJuowVZf+GPrRyRHMnlA= X-Google-Smtp-Source: AGHT+IH3bAnOvnI6Pq2vX4c76Uz2exd4GS/lRDD5/Iy0BoeBvs1XELAgKwzc5E+sxIwjUYGHA9tP+HN6jwoHp4YmuSA= X-Received: by 2002:a05:6e02:20cb:b0:3a7:4700:7c1 with SMTP id e9e14a558f8ab-3a7864ed432mr35796545ab.12.1732114269419; Wed, 20 Nov 2024 06:51:09 -0800 (PST) MIME-Version: 1.0 From: Timothy Kenno Handojo Date: Wed, 20 Nov 2024 21:50:58 +0700 Message-ID: To: seabios@seabios.org Message-ID-Hash: 4CWL2NEIXDPVDPBJ6MDNWLONPSJ3ERJF X-Message-ID-Hash: 4CWL2NEIXDPVDPBJ6MDNWLONPSJ3ERJF X-MailFrom: kennohan@gmail.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH] NVRAM bootorder List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1732114295179116600 Content-Type: text/plain; charset="utf-8" This change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. Tested on QEMU Q35 From 055a831ed9872b99bf6d060c70b495e286ded1ba Mon Sep 17 00:00:00 2001 From: Timothy Kenno Handojo Date: Thu, 31 Oct 2024 08:11:38 +0700 Subject: [PATCH] boot: Allow setting bootorder from CMOS entry The original bootorder from CBFS remains, but takes lower priority. Signed-off-by: Timothy Kenno Handojo --- Makefile | 2 +- src/boot.c | 9 +++- src/nvram.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/nvram.h | 37 +++++++++++++++ 4 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 src/nvram.c create mode 100644 src/nvram.h diff --git a/Makefile b/Makefile index d3341870..48f0b9ac 100644 --- a/Makefile +++ b/Makefile @@ -46,7 +46,7 @@ SRC32FLAT=3D$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c \ fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c + hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c nvram.c SRC32SEG=3Dstring.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio= .c DIRS=3Dsrc src/hw src/fw vgasrc diff --git a/src/boot.c b/src/boot.c index 1effd802..0689d7de 100644 --- a/src/boot.c +++ b/src/boot.c @@ -21,6 +21,8 @@ #include "string.h" // memset #include "util.h" // irqtimer_calc #include "tcgbios.h" // tpm_* +#include "nvram.h" // get_nvram_bootorder + /**************************************************************** * Helper search functions @@ -250,8 +252,13 @@ loadBootOrder(void) { if (!CONFIG_BOOTORDER) return; + char *f =3D NULL; + + f =3D get_nvram_bootorder(); + + if (!f) + f =3D romfile_loadfile("bootorder", NULL); - char *f =3D romfile_loadfile("bootorder", NULL); if (!f) return; diff --git a/src/nvram.c b/src/nvram.c new file mode 100644 index 00000000..0634cf9c --- /dev/null +++ b/src/nvram.c @@ -0,0 +1,130 @@ +#include "nvram.h" +#include "string.h" // memcmp, strlen +#include "malloc.h" // malloc_low +#include "x86.h" // inb, outb +#include "output.h" // dprintf +#include "util.h" // cb_header, find_cb_table, find_cb_subtable + +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 +#define CB_TAG_OPTION 0x00c9 +#define CB_TAG_OPTION_CHECKSUM 0x00cc + + +u8 nvram_read(u8 addr){ + u16 rtc_port =3D addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + return inb(rtc_port + 1); +} + +void nvram_write(u8 val, u8 addr) +{ + u16 rtc_port =3D addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + outb(val, rtc_port + 1); +} + +struct nvram_accessor { + u8 (*read)(u8 reg); + void (*write)(u8 val, u8 reg); +}; + +struct nvram_accessor *use_nvram =3D &(struct nvram_accessor) { + nvram_read, + nvram_write +}; + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) +{ + struct cb_cmos_entries *cmos_entry, *next; + int len =3D name ? strlen(name) : 0; + + /* CMOS entries are located right after the option table */ + cmos_entry =3D (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length); + while (cmos_entry) { + if (memcmp((const char*)cmos_entry->name, name, len) =3D=3D 0) + return cmos_entry; + next =3D (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + cmos_entry =3D (next->tag =3D=3D CB_TAG_OPTION) ? next : NULL; + } + + dprintf(1, "ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +{ + u8 *value =3D valptr; + int offs =3D 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=3D(bitnum / 8); + bit=3D(bitnum % 8); + + /* Handle single byte or less */ + if(len <=3D 8) { + reg8 =3D nvram->read(addr); + reg8 >>=3D bit; + value[0] =3D reg8 & ((1 << len) -1); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -=3D 8; + value[offs++]=3Dnvram->read(addr++); + } + + return 0; +} + +int options_checksum_valid(const struct nvram_accessor *nvram, struct cb_cmos_checksum *option_checksum) +{ + int i; + int checksum_location =3D option_checksum->location / 8; + u16 checksum =3D 0, checksum_old; + + for(i =3D option_checksum->range_start; i <=3D option_checksum->range_end; i++) { + checksum +=3D nvram->read(i); + } + + checksum_old =3D ((nvram->read(checksum_location)<<8) | nvram->read(checksum_location+1)); + + return (checksum_old =3D=3D checksum); +} + +void *get_nvram_bootorder() +{ + const char *name =3D "bootorder"; + struct cb_header *cbh =3D find_cb_table(); + + if (!cbh) + return NULL; + struct cb_cmos_option_table *option_table =3D find_cb_subtable(cbh, CB_TAG_CMOS_OPTION_TABLE); + struct cb_cmos_checksum *option_checksum =3D find_cb_subtable(cbh, CB_TAG_OPTION_CHECKSUM); + if (option_table =3D=3D NULL) { + dprintf(1, "Could not find coreboot option table.\n"); + return NULL; + } + + struct cb_cmos_entries *cmos_entry =3D lookup_cmos_entry(option_table,= name); + + if (!cmos_entry) + return NULL; + int cmos_length =3D cmos_entry->length; + + /* extra byte to ensure 0-terminated strings */ + void *buf =3D malloc_low(cmos_length+1); + memset(buf, 0, cmos_length+1); + + if(!options_checksum_valid(use_nvram, option_checksum)) { + dprintf(1, "Invalid option checksum.\n"); + return NULL; + } + get_cmos_value(use_nvram, cmos_entry->bit, cmos_entry->length, buf); + + return buf; +} diff --git a/src/nvram.h b/src/nvram.h new file mode 100644 index 00000000..4c9d559e --- /dev/null +++ b/src/nvram.h @@ -0,0 +1,37 @@ +#ifndef __NVRAM_H +#define __NVRAM_H + +#include "types.h" // u32, u8 + +#define RTC_PORT_STANDARD 0x70 +#define RTC_PORT_EXTENDED 0x72 + +struct cb_cmos_option_table { + u32 tag; + u32 size; + u32 header_length; +}; + +#define CB_CMOS_MAX_NAME_LENGTH 32 +struct cb_cmos_entries { + u32 tag; + u32 size; + u32 bit; + u32 length; + u32 config; + u32 config_id; + u8 name[CB_CMOS_MAX_NAME_LENGTH]; +}; + +struct cb_cmos_checksum { + u32 tag; + u32 size; + u32 range_start; + u32 range_end; + u32 location; + u32 type; +}; + +void *get_nvram_bootorder(); + +#endif \ No newline at end of file --=20 2.39.5 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org